rtc-sunxi.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * An RTC driver for Allwinner A10/A20
  4. *
  5. * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/fs.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/rtc.h>
  20. #include <linux/types.h>
  21. #define SUNXI_LOSC_CTRL 0x0000
  22. #define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
  23. #define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
  24. #define SUNXI_RTC_YMD 0x0004
  25. #define SUNXI_RTC_HMS 0x0008
  26. #define SUNXI_ALRM_DHMS 0x000c
  27. #define SUNXI_ALRM_EN 0x0014
  28. #define SUNXI_ALRM_EN_CNT_EN BIT(8)
  29. #define SUNXI_ALRM_IRQ_EN 0x0018
  30. #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
  31. #define SUNXI_ALRM_IRQ_STA 0x001c
  32. #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
  33. #define SUNXI_MASK_DH 0x0000001f
  34. #define SUNXI_MASK_SM 0x0000003f
  35. #define SUNXI_MASK_M 0x0000000f
  36. #define SUNXI_MASK_LY 0x00000001
  37. #define SUNXI_MASK_D 0x00000ffe
  38. #define SUNXI_MASK_M 0x0000000f
  39. #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
  40. >> (shift))
  41. #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
  42. /*
  43. * Get date values
  44. */
  45. #define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
  46. #define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
  47. #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
  48. /*
  49. * Get time values
  50. */
  51. #define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
  52. #define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
  53. #define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
  54. /*
  55. * Get alarm values
  56. */
  57. #define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
  58. #define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
  59. #define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
  60. /*
  61. * Set date values
  62. */
  63. #define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
  64. #define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
  65. #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
  66. #define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
  67. /*
  68. * Set time values
  69. */
  70. #define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
  71. #define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
  72. #define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
  73. /*
  74. * Set alarm values
  75. */
  76. #define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
  77. #define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
  78. #define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
  79. #define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
  80. /*
  81. * Time unit conversions
  82. */
  83. #define SEC_IN_MIN 60
  84. #define SEC_IN_HOUR (60 * SEC_IN_MIN)
  85. #define SEC_IN_DAY (24 * SEC_IN_HOUR)
  86. /*
  87. * The year parameter passed to the driver is usually an offset relative to
  88. * the year 1900. This macro is used to convert this offset to another one
  89. * relative to the minimum year allowed by the hardware.
  90. */
  91. #define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
  92. /*
  93. * min and max year are arbitrary set considering the limited range of the
  94. * hardware register field
  95. */
  96. struct sunxi_rtc_data_year {
  97. unsigned int min; /* min year allowed */
  98. unsigned int max; /* max year allowed */
  99. unsigned int mask; /* mask for the year field */
  100. unsigned char leap_shift; /* bit shift to get the leap year */
  101. };
  102. static const struct sunxi_rtc_data_year data_year_param[] = {
  103. [0] = {
  104. .min = 2010,
  105. .max = 2073,
  106. .mask = 0x3f,
  107. .leap_shift = 22,
  108. },
  109. [1] = {
  110. .min = 1970,
  111. .max = 2225,
  112. .mask = 0xff,
  113. .leap_shift = 24,
  114. },
  115. };
  116. struct sunxi_rtc_dev {
  117. struct rtc_device *rtc;
  118. struct device *dev;
  119. const struct sunxi_rtc_data_year *data_year;
  120. void __iomem *base;
  121. int irq;
  122. };
  123. static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
  124. {
  125. struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
  126. u32 val;
  127. val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
  128. if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
  129. val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
  130. writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
  131. rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
  132. return IRQ_HANDLED;
  133. }
  134. return IRQ_NONE;
  135. }
  136. static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
  137. {
  138. u32 alrm_val = 0;
  139. u32 alrm_irq_val = 0;
  140. if (to) {
  141. alrm_val = readl(chip->base + SUNXI_ALRM_EN);
  142. alrm_val |= SUNXI_ALRM_EN_CNT_EN;
  143. alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
  144. alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
  145. } else {
  146. writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
  147. chip->base + SUNXI_ALRM_IRQ_STA);
  148. }
  149. writel(alrm_val, chip->base + SUNXI_ALRM_EN);
  150. writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
  151. }
  152. static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  153. {
  154. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  155. struct rtc_time *alrm_tm = &wkalrm->time;
  156. u32 alrm;
  157. u32 alrm_en;
  158. u32 date;
  159. alrm = readl(chip->base + SUNXI_ALRM_DHMS);
  160. date = readl(chip->base + SUNXI_RTC_YMD);
  161. alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
  162. alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
  163. alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
  164. alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
  165. alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
  166. alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
  167. chip->data_year->mask);
  168. alrm_tm->tm_mon -= 1;
  169. /*
  170. * switch from (data_year->min)-relative offset to
  171. * a (1900)-relative one
  172. */
  173. alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
  174. alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
  175. if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
  176. wkalrm->enabled = 1;
  177. return 0;
  178. }
  179. static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  180. {
  181. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  182. u32 date, time;
  183. /*
  184. * read again in case it changes
  185. */
  186. do {
  187. date = readl(chip->base + SUNXI_RTC_YMD);
  188. time = readl(chip->base + SUNXI_RTC_HMS);
  189. } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
  190. (time != readl(chip->base + SUNXI_RTC_HMS)));
  191. rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
  192. rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
  193. rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
  194. rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
  195. rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
  196. rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
  197. chip->data_year->mask);
  198. rtc_tm->tm_mon -= 1;
  199. /*
  200. * switch from (data_year->min)-relative offset to
  201. * a (1900)-relative one
  202. */
  203. rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
  204. return 0;
  205. }
  206. static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  207. {
  208. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  209. struct rtc_time *alrm_tm = &wkalrm->time;
  210. struct rtc_time tm_now;
  211. u32 alrm;
  212. time64_t diff;
  213. unsigned long time_gap;
  214. unsigned long time_gap_day;
  215. unsigned long time_gap_hour;
  216. unsigned long time_gap_min;
  217. int ret;
  218. ret = sunxi_rtc_gettime(dev, &tm_now);
  219. if (ret < 0) {
  220. dev_err(dev, "Error in getting time\n");
  221. return -EINVAL;
  222. }
  223. diff = rtc_tm_sub(alrm_tm, &tm_now);
  224. if (diff <= 0) {
  225. dev_err(dev, "Date to set in the past\n");
  226. return -EINVAL;
  227. }
  228. if (diff > 255 * SEC_IN_DAY) {
  229. dev_err(dev, "Day must be in the range 0 - 255\n");
  230. return -EINVAL;
  231. }
  232. time_gap = diff;
  233. time_gap_day = time_gap / SEC_IN_DAY;
  234. time_gap -= time_gap_day * SEC_IN_DAY;
  235. time_gap_hour = time_gap / SEC_IN_HOUR;
  236. time_gap -= time_gap_hour * SEC_IN_HOUR;
  237. time_gap_min = time_gap / SEC_IN_MIN;
  238. time_gap -= time_gap_min * SEC_IN_MIN;
  239. sunxi_rtc_setaie(0, chip);
  240. writel(0, chip->base + SUNXI_ALRM_DHMS);
  241. usleep_range(100, 300);
  242. alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
  243. SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
  244. SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
  245. SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
  246. writel(alrm, chip->base + SUNXI_ALRM_DHMS);
  247. writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
  248. writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
  249. sunxi_rtc_setaie(wkalrm->enabled, chip);
  250. return 0;
  251. }
  252. static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
  253. unsigned int mask, unsigned int ms_timeout)
  254. {
  255. const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
  256. u32 reg;
  257. do {
  258. reg = readl(chip->base + offset);
  259. reg &= mask;
  260. if (reg == mask)
  261. return 0;
  262. } while (time_before(jiffies, timeout));
  263. return -ETIMEDOUT;
  264. }
  265. static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
  266. {
  267. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  268. u32 date = 0;
  269. u32 time = 0;
  270. unsigned int year;
  271. /*
  272. * the input rtc_tm->tm_year is the offset relative to 1900. We use
  273. * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
  274. * allowed by the hardware
  275. */
  276. year = rtc_tm->tm_year + 1900;
  277. if (year < chip->data_year->min || year > chip->data_year->max) {
  278. dev_err(dev, "rtc only supports year in range %u - %u\n",
  279. chip->data_year->min, chip->data_year->max);
  280. return -EINVAL;
  281. }
  282. rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
  283. rtc_tm->tm_mon += 1;
  284. date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
  285. SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
  286. SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
  287. chip->data_year->mask);
  288. if (is_leap_year(year))
  289. date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
  290. time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
  291. SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
  292. SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
  293. writel(0, chip->base + SUNXI_RTC_HMS);
  294. writel(0, chip->base + SUNXI_RTC_YMD);
  295. writel(time, chip->base + SUNXI_RTC_HMS);
  296. /*
  297. * After writing the RTC HH-MM-SS register, the
  298. * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
  299. * be cleared until the real writing operation is finished
  300. */
  301. if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
  302. SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
  303. dev_err(dev, "Failed to set rtc time.\n");
  304. return -1;
  305. }
  306. writel(date, chip->base + SUNXI_RTC_YMD);
  307. /*
  308. * After writing the RTC YY-MM-DD register, the
  309. * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
  310. * be cleared until the real writing operation is finished
  311. */
  312. if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
  313. SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
  314. dev_err(dev, "Failed to set rtc time.\n");
  315. return -1;
  316. }
  317. return 0;
  318. }
  319. static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  320. {
  321. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  322. if (!enabled)
  323. sunxi_rtc_setaie(enabled, chip);
  324. return 0;
  325. }
  326. static const struct rtc_class_ops sunxi_rtc_ops = {
  327. .read_time = sunxi_rtc_gettime,
  328. .set_time = sunxi_rtc_settime,
  329. .read_alarm = sunxi_rtc_getalarm,
  330. .set_alarm = sunxi_rtc_setalarm,
  331. .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
  332. };
  333. static const struct of_device_id sunxi_rtc_dt_ids[] = {
  334. { .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
  335. { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
  336. { /* sentinel */ },
  337. };
  338. MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
  339. static int sunxi_rtc_probe(struct platform_device *pdev)
  340. {
  341. struct sunxi_rtc_dev *chip;
  342. int ret;
  343. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  344. if (!chip)
  345. return -ENOMEM;
  346. platform_set_drvdata(pdev, chip);
  347. chip->dev = &pdev->dev;
  348. chip->rtc = devm_rtc_allocate_device(&pdev->dev);
  349. if (IS_ERR(chip->rtc))
  350. return PTR_ERR(chip->rtc);
  351. chip->base = devm_platform_ioremap_resource(pdev, 0);
  352. if (IS_ERR(chip->base))
  353. return PTR_ERR(chip->base);
  354. chip->irq = platform_get_irq(pdev, 0);
  355. if (chip->irq < 0)
  356. return chip->irq;
  357. ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
  358. 0, dev_name(&pdev->dev), chip);
  359. if (ret) {
  360. dev_err(&pdev->dev, "Could not request IRQ\n");
  361. return ret;
  362. }
  363. chip->data_year = of_device_get_match_data(&pdev->dev);
  364. if (!chip->data_year) {
  365. dev_err(&pdev->dev, "Unable to setup RTC data\n");
  366. return -ENODEV;
  367. }
  368. /* clear the alarm count value */
  369. writel(0, chip->base + SUNXI_ALRM_DHMS);
  370. /* disable alarm, not generate irq pending */
  371. writel(0, chip->base + SUNXI_ALRM_EN);
  372. /* disable alarm week/cnt irq, unset to cpu */
  373. writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
  374. /* clear alarm week/cnt irq pending */
  375. writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
  376. SUNXI_ALRM_IRQ_STA);
  377. chip->rtc->ops = &sunxi_rtc_ops;
  378. return rtc_register_device(chip->rtc);
  379. }
  380. static struct platform_driver sunxi_rtc_driver = {
  381. .probe = sunxi_rtc_probe,
  382. .driver = {
  383. .name = "sunxi-rtc",
  384. .of_match_table = sunxi_rtc_dt_ids,
  385. },
  386. };
  387. module_platform_driver(sunxi_rtc_driver);
  388. MODULE_DESCRIPTION("sunxi RTC driver");
  389. MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
  390. MODULE_LICENSE("GPL");