rtc-sun6i.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * An RTC driver for Allwinner A31/A23
  4. *
  5. * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
  6. *
  7. * based on rtc-sunxi.c
  8. *
  9. * An RTC driver for Allwinner A10/A20
  10. *
  11. * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/fs.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_device.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/rtc.h>
  28. #include <linux/slab.h>
  29. #include <linux/types.h>
  30. /* Control register */
  31. #define SUN6I_LOSC_CTRL 0x0000
  32. #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
  33. #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
  34. #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
  35. #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
  36. #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
  37. #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
  38. #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
  39. #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
  40. #define SUN6I_LOSC_CLK_PRESCAL 0x0008
  41. /* RTC */
  42. #define SUN6I_RTC_YMD 0x0010
  43. #define SUN6I_RTC_HMS 0x0014
  44. /* Alarm 0 (counter) */
  45. #define SUN6I_ALRM_COUNTER 0x0020
  46. #define SUN6I_ALRM_CUR_VAL 0x0024
  47. #define SUN6I_ALRM_EN 0x0028
  48. #define SUN6I_ALRM_EN_CNT_EN BIT(0)
  49. #define SUN6I_ALRM_IRQ_EN 0x002c
  50. #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
  51. #define SUN6I_ALRM_IRQ_STA 0x0030
  52. #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
  53. /* Alarm 1 (wall clock) */
  54. #define SUN6I_ALRM1_EN 0x0044
  55. #define SUN6I_ALRM1_IRQ_EN 0x0048
  56. #define SUN6I_ALRM1_IRQ_STA 0x004c
  57. #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
  58. /* Alarm config */
  59. #define SUN6I_ALARM_CONFIG 0x0050
  60. #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
  61. #define SUN6I_LOSC_OUT_GATING 0x0060
  62. #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
  63. /*
  64. * Get date values
  65. */
  66. #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
  67. #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
  68. #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
  69. #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
  70. /*
  71. * Get time values
  72. */
  73. #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
  74. #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
  75. #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
  76. /*
  77. * Set date values
  78. */
  79. #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
  80. #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
  81. #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
  82. #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
  83. /*
  84. * Set time values
  85. */
  86. #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
  87. #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
  88. #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
  89. /*
  90. * The year parameter passed to the driver is usually an offset relative to
  91. * the year 1900. This macro is used to convert this offset to another one
  92. * relative to the minimum year allowed by the hardware.
  93. *
  94. * The year range is 1970 - 2033. This range is selected to match Allwinner's
  95. * driver, even though it is somewhat limited.
  96. */
  97. #define SUN6I_YEAR_MIN 1970
  98. #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
  99. /*
  100. * There are other differences between models, including:
  101. *
  102. * - number of GPIO pins that can be configured to hold a certain level
  103. * - crypto-key related registers (H5, H6)
  104. * - boot process related (super standby, secondary processor entry address)
  105. * registers (R40, H6)
  106. * - SYS power domain controls (R40)
  107. * - DCXO controls (H6)
  108. * - RC oscillator calibration (H6)
  109. *
  110. * These functions are not covered by this driver.
  111. */
  112. struct sun6i_rtc_clk_data {
  113. unsigned long rc_osc_rate;
  114. unsigned int fixed_prescaler : 16;
  115. unsigned int has_prescaler : 1;
  116. unsigned int has_out_clk : 1;
  117. unsigned int export_iosc : 1;
  118. unsigned int has_losc_en : 1;
  119. unsigned int has_auto_swt : 1;
  120. };
  121. struct sun6i_rtc_dev {
  122. struct rtc_device *rtc;
  123. const struct sun6i_rtc_clk_data *data;
  124. void __iomem *base;
  125. int irq;
  126. unsigned long alarm;
  127. struct clk_hw hw;
  128. struct clk_hw *int_osc;
  129. struct clk *losc;
  130. struct clk *ext_losc;
  131. spinlock_t lock;
  132. };
  133. static struct sun6i_rtc_dev *sun6i_rtc;
  134. static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
  135. unsigned long parent_rate)
  136. {
  137. struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
  138. u32 val = 0;
  139. val = readl(rtc->base + SUN6I_LOSC_CTRL);
  140. if (val & SUN6I_LOSC_CTRL_EXT_OSC)
  141. return parent_rate;
  142. if (rtc->data->fixed_prescaler)
  143. parent_rate /= rtc->data->fixed_prescaler;
  144. if (rtc->data->has_prescaler) {
  145. val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
  146. val &= GENMASK(4, 0);
  147. }
  148. return parent_rate / (val + 1);
  149. }
  150. static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
  151. {
  152. struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
  153. return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
  154. }
  155. static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
  156. {
  157. struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
  158. unsigned long flags;
  159. u32 val;
  160. if (index > 1)
  161. return -EINVAL;
  162. spin_lock_irqsave(&rtc->lock, flags);
  163. val = readl(rtc->base + SUN6I_LOSC_CTRL);
  164. val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
  165. val |= SUN6I_LOSC_CTRL_KEY;
  166. val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
  167. if (rtc->data->has_losc_en) {
  168. val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
  169. val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
  170. }
  171. writel(val, rtc->base + SUN6I_LOSC_CTRL);
  172. spin_unlock_irqrestore(&rtc->lock, flags);
  173. return 0;
  174. }
  175. static const struct clk_ops sun6i_rtc_osc_ops = {
  176. .recalc_rate = sun6i_rtc_osc_recalc_rate,
  177. .get_parent = sun6i_rtc_osc_get_parent,
  178. .set_parent = sun6i_rtc_osc_set_parent,
  179. };
  180. static void __init sun6i_rtc_clk_init(struct device_node *node,
  181. const struct sun6i_rtc_clk_data *data)
  182. {
  183. struct clk_hw_onecell_data *clk_data;
  184. struct sun6i_rtc_dev *rtc;
  185. struct clk_init_data init = {
  186. .ops = &sun6i_rtc_osc_ops,
  187. .name = "losc",
  188. };
  189. const char *iosc_name = "rtc-int-osc";
  190. const char *clkout_name = "osc32k-out";
  191. const char *parents[2];
  192. u32 reg;
  193. rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
  194. if (!rtc)
  195. return;
  196. rtc->data = data;
  197. clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
  198. if (!clk_data) {
  199. kfree(rtc);
  200. return;
  201. }
  202. spin_lock_init(&rtc->lock);
  203. rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
  204. if (IS_ERR(rtc->base)) {
  205. pr_crit("Can't map RTC registers");
  206. goto err;
  207. }
  208. reg = SUN6I_LOSC_CTRL_KEY;
  209. if (rtc->data->has_auto_swt) {
  210. /* Bypass auto-switch to int osc, on ext losc failure */
  211. reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
  212. writel(reg, rtc->base + SUN6I_LOSC_CTRL);
  213. }
  214. /* Switch to the external, more precise, oscillator, if present */
  215. if (of_get_property(node, "clocks", NULL)) {
  216. reg |= SUN6I_LOSC_CTRL_EXT_OSC;
  217. if (rtc->data->has_losc_en)
  218. reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
  219. }
  220. writel(reg, rtc->base + SUN6I_LOSC_CTRL);
  221. /* Yes, I know, this is ugly. */
  222. sun6i_rtc = rtc;
  223. /* Only read IOSC name from device tree if it is exported */
  224. if (rtc->data->export_iosc)
  225. of_property_read_string_index(node, "clock-output-names", 2,
  226. &iosc_name);
  227. rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
  228. iosc_name,
  229. NULL, 0,
  230. rtc->data->rc_osc_rate,
  231. 300000000);
  232. if (IS_ERR(rtc->int_osc)) {
  233. pr_crit("Couldn't register the internal oscillator\n");
  234. goto err;
  235. }
  236. parents[0] = clk_hw_get_name(rtc->int_osc);
  237. /* If there is no external oscillator, this will be NULL and ... */
  238. parents[1] = of_clk_get_parent_name(node, 0);
  239. rtc->hw.init = &init;
  240. init.parent_names = parents;
  241. /* ... number of clock parents will be 1. */
  242. init.num_parents = of_clk_get_parent_count(node) + 1;
  243. of_property_read_string_index(node, "clock-output-names", 0,
  244. &init.name);
  245. rtc->losc = clk_register(NULL, &rtc->hw);
  246. if (IS_ERR(rtc->losc)) {
  247. pr_crit("Couldn't register the LOSC clock\n");
  248. goto err_register;
  249. }
  250. of_property_read_string_index(node, "clock-output-names", 1,
  251. &clkout_name);
  252. rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
  253. 0, rtc->base + SUN6I_LOSC_OUT_GATING,
  254. SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
  255. &rtc->lock);
  256. if (IS_ERR(rtc->ext_losc)) {
  257. pr_crit("Couldn't register the LOSC external gate\n");
  258. goto err_register;
  259. }
  260. clk_data->num = 2;
  261. clk_data->hws[0] = &rtc->hw;
  262. clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
  263. if (rtc->data->export_iosc) {
  264. clk_data->hws[2] = rtc->int_osc;
  265. clk_data->num = 3;
  266. }
  267. of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  268. return;
  269. err_register:
  270. clk_hw_unregister_fixed_rate(rtc->int_osc);
  271. err:
  272. kfree(clk_data);
  273. }
  274. static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
  275. .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
  276. .has_prescaler = 1,
  277. };
  278. static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
  279. {
  280. sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
  281. }
  282. CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
  283. sun6i_a31_rtc_clk_init);
  284. static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
  285. .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
  286. .has_prescaler = 1,
  287. .has_out_clk = 1,
  288. };
  289. static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
  290. {
  291. sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
  292. }
  293. CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
  294. sun8i_a23_rtc_clk_init);
  295. static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
  296. .rc_osc_rate = 16000000,
  297. .fixed_prescaler = 32,
  298. .has_prescaler = 1,
  299. .has_out_clk = 1,
  300. .export_iosc = 1,
  301. };
  302. static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
  303. {
  304. sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
  305. }
  306. CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
  307. sun8i_h3_rtc_clk_init);
  308. /* As far as we are concerned, clocks for H5 are the same as H3 */
  309. CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
  310. sun8i_h3_rtc_clk_init);
  311. static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
  312. .rc_osc_rate = 16000000,
  313. .fixed_prescaler = 32,
  314. .has_prescaler = 1,
  315. .has_out_clk = 1,
  316. .export_iosc = 1,
  317. .has_losc_en = 1,
  318. .has_auto_swt = 1,
  319. };
  320. static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
  321. {
  322. sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
  323. }
  324. CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
  325. sun50i_h6_rtc_clk_init);
  326. /*
  327. * The R40 user manual is self-conflicting on whether the prescaler is
  328. * fixed or configurable. The clock diagram shows it as fixed, but there
  329. * is also a configurable divider in the RTC block.
  330. */
  331. static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
  332. .rc_osc_rate = 16000000,
  333. .fixed_prescaler = 512,
  334. };
  335. static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
  336. {
  337. sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
  338. }
  339. CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
  340. sun8i_r40_rtc_clk_init);
  341. static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
  342. .rc_osc_rate = 32000,
  343. .has_out_clk = 1,
  344. };
  345. static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
  346. {
  347. sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
  348. }
  349. CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
  350. sun8i_v3_rtc_clk_init);
  351. static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
  352. {
  353. struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
  354. irqreturn_t ret = IRQ_NONE;
  355. u32 val;
  356. spin_lock(&chip->lock);
  357. val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
  358. if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
  359. val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
  360. writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
  361. rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
  362. ret = IRQ_HANDLED;
  363. }
  364. spin_unlock(&chip->lock);
  365. return ret;
  366. }
  367. static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
  368. {
  369. u32 alrm_val = 0;
  370. u32 alrm_irq_val = 0;
  371. u32 alrm_wake_val = 0;
  372. unsigned long flags;
  373. if (to) {
  374. alrm_val = SUN6I_ALRM_EN_CNT_EN;
  375. alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
  376. alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
  377. } else {
  378. writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
  379. chip->base + SUN6I_ALRM_IRQ_STA);
  380. }
  381. spin_lock_irqsave(&chip->lock, flags);
  382. writel(alrm_val, chip->base + SUN6I_ALRM_EN);
  383. writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
  384. writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
  385. spin_unlock_irqrestore(&chip->lock, flags);
  386. }
  387. static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  388. {
  389. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  390. u32 date, time;
  391. /*
  392. * read again in case it changes
  393. */
  394. do {
  395. date = readl(chip->base + SUN6I_RTC_YMD);
  396. time = readl(chip->base + SUN6I_RTC_HMS);
  397. } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
  398. (time != readl(chip->base + SUN6I_RTC_HMS)));
  399. rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
  400. rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
  401. rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
  402. rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
  403. rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
  404. rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
  405. rtc_tm->tm_mon -= 1;
  406. /*
  407. * switch from (data_year->min)-relative offset to
  408. * a (1900)-relative one
  409. */
  410. rtc_tm->tm_year += SUN6I_YEAR_OFF;
  411. return 0;
  412. }
  413. static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  414. {
  415. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  416. unsigned long flags;
  417. u32 alrm_st;
  418. u32 alrm_en;
  419. spin_lock_irqsave(&chip->lock, flags);
  420. alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
  421. alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
  422. spin_unlock_irqrestore(&chip->lock, flags);
  423. wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
  424. wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
  425. rtc_time64_to_tm(chip->alarm, &wkalrm->time);
  426. return 0;
  427. }
  428. static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  429. {
  430. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  431. struct rtc_time *alrm_tm = &wkalrm->time;
  432. struct rtc_time tm_now;
  433. unsigned long time_now = 0;
  434. unsigned long time_set = 0;
  435. unsigned long time_gap = 0;
  436. int ret = 0;
  437. ret = sun6i_rtc_gettime(dev, &tm_now);
  438. if (ret < 0) {
  439. dev_err(dev, "Error in getting time\n");
  440. return -EINVAL;
  441. }
  442. time_set = rtc_tm_to_time64(alrm_tm);
  443. time_now = rtc_tm_to_time64(&tm_now);
  444. if (time_set <= time_now) {
  445. dev_err(dev, "Date to set in the past\n");
  446. return -EINVAL;
  447. }
  448. time_gap = time_set - time_now;
  449. if (time_gap > U32_MAX) {
  450. dev_err(dev, "Date too far in the future\n");
  451. return -EINVAL;
  452. }
  453. sun6i_rtc_setaie(0, chip);
  454. writel(0, chip->base + SUN6I_ALRM_COUNTER);
  455. usleep_range(100, 300);
  456. writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
  457. chip->alarm = time_set;
  458. sun6i_rtc_setaie(wkalrm->enabled, chip);
  459. return 0;
  460. }
  461. static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
  462. unsigned int mask, unsigned int ms_timeout)
  463. {
  464. const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
  465. u32 reg;
  466. do {
  467. reg = readl(chip->base + offset);
  468. reg &= mask;
  469. if (!reg)
  470. return 0;
  471. } while (time_before(jiffies, timeout));
  472. return -ETIMEDOUT;
  473. }
  474. static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
  475. {
  476. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  477. u32 date = 0;
  478. u32 time = 0;
  479. rtc_tm->tm_year -= SUN6I_YEAR_OFF;
  480. rtc_tm->tm_mon += 1;
  481. date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
  482. SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
  483. SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
  484. if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
  485. date |= SUN6I_LEAP_SET_VALUE(1);
  486. time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
  487. SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
  488. SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
  489. /* Check whether registers are writable */
  490. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  491. SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
  492. dev_err(dev, "rtc is still busy.\n");
  493. return -EBUSY;
  494. }
  495. writel(time, chip->base + SUN6I_RTC_HMS);
  496. /*
  497. * After writing the RTC HH-MM-SS register, the
  498. * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
  499. * be cleared until the real writing operation is finished
  500. */
  501. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  502. SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
  503. dev_err(dev, "Failed to set rtc time.\n");
  504. return -ETIMEDOUT;
  505. }
  506. writel(date, chip->base + SUN6I_RTC_YMD);
  507. /*
  508. * After writing the RTC YY-MM-DD register, the
  509. * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
  510. * be cleared until the real writing operation is finished
  511. */
  512. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  513. SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
  514. dev_err(dev, "Failed to set rtc time.\n");
  515. return -ETIMEDOUT;
  516. }
  517. return 0;
  518. }
  519. static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  520. {
  521. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  522. if (!enabled)
  523. sun6i_rtc_setaie(enabled, chip);
  524. return 0;
  525. }
  526. static const struct rtc_class_ops sun6i_rtc_ops = {
  527. .read_time = sun6i_rtc_gettime,
  528. .set_time = sun6i_rtc_settime,
  529. .read_alarm = sun6i_rtc_getalarm,
  530. .set_alarm = sun6i_rtc_setalarm,
  531. .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
  532. };
  533. #ifdef CONFIG_PM_SLEEP
  534. /* Enable IRQ wake on suspend, to wake up from RTC. */
  535. static int sun6i_rtc_suspend(struct device *dev)
  536. {
  537. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  538. if (device_may_wakeup(dev))
  539. enable_irq_wake(chip->irq);
  540. return 0;
  541. }
  542. /* Disable IRQ wake on resume. */
  543. static int sun6i_rtc_resume(struct device *dev)
  544. {
  545. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  546. if (device_may_wakeup(dev))
  547. disable_irq_wake(chip->irq);
  548. return 0;
  549. }
  550. #endif
  551. static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
  552. sun6i_rtc_suspend, sun6i_rtc_resume);
  553. static int sun6i_rtc_probe(struct platform_device *pdev)
  554. {
  555. struct sun6i_rtc_dev *chip = sun6i_rtc;
  556. int ret;
  557. if (!chip)
  558. return -ENODEV;
  559. platform_set_drvdata(pdev, chip);
  560. chip->irq = platform_get_irq(pdev, 0);
  561. if (chip->irq < 0)
  562. return chip->irq;
  563. ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
  564. 0, dev_name(&pdev->dev), chip);
  565. if (ret) {
  566. dev_err(&pdev->dev, "Could not request IRQ\n");
  567. return ret;
  568. }
  569. /* clear the alarm counter value */
  570. writel(0, chip->base + SUN6I_ALRM_COUNTER);
  571. /* disable counter alarm */
  572. writel(0, chip->base + SUN6I_ALRM_EN);
  573. /* disable counter alarm interrupt */
  574. writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
  575. /* disable week alarm */
  576. writel(0, chip->base + SUN6I_ALRM1_EN);
  577. /* disable week alarm interrupt */
  578. writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
  579. /* clear counter alarm pending interrupts */
  580. writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
  581. chip->base + SUN6I_ALRM_IRQ_STA);
  582. /* clear week alarm pending interrupts */
  583. writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
  584. chip->base + SUN6I_ALRM1_IRQ_STA);
  585. /* disable alarm wakeup */
  586. writel(0, chip->base + SUN6I_ALARM_CONFIG);
  587. clk_prepare_enable(chip->losc);
  588. device_init_wakeup(&pdev->dev, 1);
  589. chip->rtc = devm_rtc_allocate_device(&pdev->dev);
  590. if (IS_ERR(chip->rtc))
  591. return PTR_ERR(chip->rtc);
  592. chip->rtc->ops = &sun6i_rtc_ops;
  593. chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
  594. ret = rtc_register_device(chip->rtc);
  595. if (ret)
  596. return ret;
  597. dev_info(&pdev->dev, "RTC enabled\n");
  598. return 0;
  599. }
  600. /*
  601. * As far as RTC functionality goes, all models are the same. The
  602. * datasheets claim that different models have different number of
  603. * registers available for non-volatile storage, but experiments show
  604. * that all SoCs have 16 registers available for this purpose.
  605. */
  606. static const struct of_device_id sun6i_rtc_dt_ids[] = {
  607. { .compatible = "allwinner,sun6i-a31-rtc" },
  608. { .compatible = "allwinner,sun8i-a23-rtc" },
  609. { .compatible = "allwinner,sun8i-h3-rtc" },
  610. { .compatible = "allwinner,sun8i-r40-rtc" },
  611. { .compatible = "allwinner,sun8i-v3-rtc" },
  612. { .compatible = "allwinner,sun50i-h5-rtc" },
  613. { .compatible = "allwinner,sun50i-h6-rtc" },
  614. { /* sentinel */ },
  615. };
  616. MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
  617. static struct platform_driver sun6i_rtc_driver = {
  618. .probe = sun6i_rtc_probe,
  619. .driver = {
  620. .name = "sun6i-rtc",
  621. .of_match_table = sun6i_rtc_dt_ids,
  622. .pm = &sun6i_rtc_pm_ops,
  623. },
  624. };
  625. builtin_platform_driver(sun6i_rtc_driver);