rtc-stmp3xxx.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale STMP37XX/STMP378X Real Time Clock driver
  4. *
  5. * Copyright (c) 2007 Sigmatel, Inc.
  6. * Peter Hartley, <peter.hartley@sigmatel.com>
  7. *
  8. * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
  9. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  10. * Copyright 2011 Wolfram Sang, Pengutronix e.K.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/io.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/delay.h>
  19. #include <linux/rtc.h>
  20. #include <linux/slab.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of.h>
  23. #include <linux/stmp_device.h>
  24. #include <linux/stmp3xxx_rtc_wdt.h>
  25. #define STMP3XXX_RTC_CTRL 0x0
  26. #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
  27. #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
  28. #define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
  29. #define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
  30. #define STMP3XXX_RTC_STAT 0x10
  31. #define STMP3XXX_RTC_STAT_STALE_SHIFT 16
  32. #define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
  33. #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
  34. #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
  35. #define STMP3XXX_RTC_SECONDS 0x30
  36. #define STMP3XXX_RTC_ALARM 0x40
  37. #define STMP3XXX_RTC_WATCHDOG 0x50
  38. #define STMP3XXX_RTC_PERSISTENT0 0x60
  39. #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
  40. #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
  41. #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
  42. #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
  43. #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
  44. #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
  45. #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
  46. #define STMP3XXX_RTC_PERSISTENT1 0x70
  47. /* missing bitmask in headers */
  48. #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
  49. struct stmp3xxx_rtc_data {
  50. struct rtc_device *rtc;
  51. void __iomem *io;
  52. int irq_alarm;
  53. };
  54. #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
  55. /**
  56. * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
  57. * @dev: the parent device of the watchdog (= the RTC)
  58. * @timeout: the desired value for the timeout register of the watchdog.
  59. * 0 disables the watchdog
  60. *
  61. * The watchdog needs one register and two bits which are in the RTC domain.
  62. * To handle the resource conflict, the RTC driver will create another
  63. * platform_device for the watchdog driver as a child of the RTC device.
  64. * The watchdog driver is passed the below accessor function via platform_data
  65. * to configure the watchdog. Locking is not needed because accessing SET/CLR
  66. * registers is atomic.
  67. */
  68. static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
  69. {
  70. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  71. if (timeout) {
  72. writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
  73. writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  74. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
  75. writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  76. rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
  77. } else {
  78. writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  79. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  80. writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  81. rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
  82. }
  83. }
  84. static struct stmp3xxx_wdt_pdata wdt_pdata = {
  85. .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
  86. };
  87. static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
  88. {
  89. int rc = -1;
  90. struct platform_device *wdt_pdev =
  91. platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
  92. if (wdt_pdev) {
  93. wdt_pdev->dev.parent = &rtc_pdev->dev;
  94. wdt_pdev->dev.platform_data = &wdt_pdata;
  95. rc = platform_device_add(wdt_pdev);
  96. }
  97. if (rc)
  98. dev_err(&rtc_pdev->dev,
  99. "failed to register stmp3xxx_rtc_wdt\n");
  100. }
  101. #else
  102. static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
  103. {
  104. }
  105. #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
  106. static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
  107. {
  108. int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
  109. /*
  110. * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
  111. * states:
  112. * | The order in which registers are updated is
  113. * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
  114. * | (This list is in bitfield order, from LSB to MSB, as they would
  115. * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
  116. * | register. For example, the Seconds register corresponds to
  117. * | STALE_REGS or NEW_REGS containing 0x80.)
  118. */
  119. do {
  120. if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
  121. (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
  122. return 0;
  123. udelay(1);
  124. } while (--timeout > 0);
  125. return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
  126. (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
  127. }
  128. /* Time read/write */
  129. static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  130. {
  131. int ret;
  132. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  133. ret = stmp3xxx_wait_time(rtc_data);
  134. if (ret)
  135. return ret;
  136. rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
  137. return 0;
  138. }
  139. static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
  140. {
  141. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  142. writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
  143. return stmp3xxx_wait_time(rtc_data);
  144. }
  145. /* interrupt(s) handler */
  146. static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
  147. {
  148. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
  149. u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
  150. if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
  151. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
  152. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  153. rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
  154. return IRQ_HANDLED;
  155. }
  156. return IRQ_NONE;
  157. }
  158. static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
  159. {
  160. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  161. if (enabled) {
  162. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  163. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
  164. rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
  165. STMP_OFFSET_REG_SET);
  166. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  167. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
  168. } else {
  169. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  170. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
  171. rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
  172. STMP_OFFSET_REG_CLR);
  173. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  174. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  175. }
  176. return 0;
  177. }
  178. static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  179. {
  180. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  181. rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
  182. return 0;
  183. }
  184. static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  185. {
  186. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  187. writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
  188. stmp3xxx_alarm_irq_enable(dev, alm->enabled);
  189. return 0;
  190. }
  191. static const struct rtc_class_ops stmp3xxx_rtc_ops = {
  192. .alarm_irq_enable =
  193. stmp3xxx_alarm_irq_enable,
  194. .read_time = stmp3xxx_rtc_gettime,
  195. .set_time = stmp3xxx_rtc_settime,
  196. .read_alarm = stmp3xxx_rtc_read_alarm,
  197. .set_alarm = stmp3xxx_rtc_set_alarm,
  198. };
  199. static int stmp3xxx_rtc_remove(struct platform_device *pdev)
  200. {
  201. struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
  202. if (!rtc_data)
  203. return 0;
  204. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  205. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  206. return 0;
  207. }
  208. static int stmp3xxx_rtc_probe(struct platform_device *pdev)
  209. {
  210. struct stmp3xxx_rtc_data *rtc_data;
  211. struct resource *r;
  212. u32 rtc_stat;
  213. u32 pers0_set, pers0_clr;
  214. u32 crystalfreq = 0;
  215. int err;
  216. rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
  217. if (!rtc_data)
  218. return -ENOMEM;
  219. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  220. if (!r) {
  221. dev_err(&pdev->dev, "failed to get resource\n");
  222. return -ENXIO;
  223. }
  224. rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  225. if (!rtc_data->io) {
  226. dev_err(&pdev->dev, "ioremap failed\n");
  227. return -EIO;
  228. }
  229. rtc_data->irq_alarm = platform_get_irq(pdev, 0);
  230. rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
  231. if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
  232. dev_err(&pdev->dev, "no device onboard\n");
  233. return -ENODEV;
  234. }
  235. platform_set_drvdata(pdev, rtc_data);
  236. /*
  237. * Resetting the rtc stops the watchdog timer that is potentially
  238. * running. So (assuming it is running on purpose) don't reset if the
  239. * watchdog is enabled.
  240. */
  241. if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
  242. STMP3XXX_RTC_CTRL_WATCHDOGEN) {
  243. dev_info(&pdev->dev,
  244. "Watchdog is running, skip resetting rtc\n");
  245. } else {
  246. err = stmp_reset_block(rtc_data->io);
  247. if (err) {
  248. dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
  249. err);
  250. return err;
  251. }
  252. }
  253. /*
  254. * Obviously the rtc needs a clock input to be able to run.
  255. * This clock can be provided by an external 32k crystal. If that one is
  256. * missing XTAL must not be disabled in suspend which consumes a
  257. * lot of power. Normally the presence and exact frequency (supported
  258. * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
  259. * proves these fuses are not blown correctly on all machines, so the
  260. * frequency can be overridden in the device tree.
  261. */
  262. if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
  263. crystalfreq = 32000;
  264. else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
  265. crystalfreq = 32768;
  266. of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
  267. &crystalfreq);
  268. switch (crystalfreq) {
  269. case 32000:
  270. /* keep 32kHz crystal running in low-power mode */
  271. pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
  272. STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
  273. STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
  274. pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
  275. break;
  276. case 32768:
  277. /* keep 32.768kHz crystal running in low-power mode */
  278. pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
  279. STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
  280. pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
  281. STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
  282. break;
  283. default:
  284. dev_warn(&pdev->dev,
  285. "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
  286. fallthrough;
  287. case 0:
  288. /* keep XTAL on in low-power mode */
  289. pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
  290. pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
  291. STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
  292. }
  293. writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
  294. STMP_OFFSET_REG_SET);
  295. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  296. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
  297. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
  298. rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
  299. writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
  300. STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  301. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  302. rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
  303. if (IS_ERR(rtc_data->rtc))
  304. return PTR_ERR(rtc_data->rtc);
  305. err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
  306. stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
  307. if (err) {
  308. dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
  309. rtc_data->irq_alarm);
  310. return err;
  311. }
  312. rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
  313. rtc_data->rtc->range_max = U32_MAX;
  314. err = rtc_register_device(rtc_data->rtc);
  315. if (err)
  316. return err;
  317. stmp3xxx_wdt_register(pdev);
  318. return 0;
  319. }
  320. #ifdef CONFIG_PM_SLEEP
  321. static int stmp3xxx_rtc_suspend(struct device *dev)
  322. {
  323. return 0;
  324. }
  325. static int stmp3xxx_rtc_resume(struct device *dev)
  326. {
  327. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  328. stmp_reset_block(rtc_data->io);
  329. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  330. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
  331. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
  332. rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
  333. return 0;
  334. }
  335. #endif
  336. static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
  337. stmp3xxx_rtc_resume);
  338. static const struct of_device_id rtc_dt_ids[] = {
  339. { .compatible = "fsl,stmp3xxx-rtc", },
  340. { /* sentinel */ }
  341. };
  342. MODULE_DEVICE_TABLE(of, rtc_dt_ids);
  343. static struct platform_driver stmp3xxx_rtcdrv = {
  344. .probe = stmp3xxx_rtc_probe,
  345. .remove = stmp3xxx_rtc_remove,
  346. .driver = {
  347. .name = "stmp3xxx-rtc",
  348. .pm = &stmp3xxx_rtc_pm_ops,
  349. .of_match_table = rtc_dt_ids,
  350. },
  351. };
  352. module_platform_driver(stmp3xxx_rtcdrv);
  353. MODULE_DESCRIPTION("STMP3xxx RTC Driver");
  354. MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
  355. "Wolfram Sang <kernel@pengutronix.de>");
  356. MODULE_LICENSE("GPL");