rtc-s5m.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
  4. // http://www.samsung.com
  5. //
  6. // Copyright (C) 2013 Google, Inc
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/module.h>
  9. #include <linux/i2c.h>
  10. #include <linux/bcd.h>
  11. #include <linux/regmap.h>
  12. #include <linux/rtc.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/mfd/samsung/core.h>
  15. #include <linux/mfd/samsung/irq.h>
  16. #include <linux/mfd/samsung/rtc.h>
  17. #include <linux/mfd/samsung/s2mps14.h>
  18. /*
  19. * Maximum number of retries for checking changes in UDR field
  20. * of S5M_RTC_UDR_CON register (to limit possible endless loop).
  21. *
  22. * After writing to RTC registers (setting time or alarm) read the UDR field
  23. * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
  24. * been transferred.
  25. */
  26. #define UDR_READ_RETRY_CNT 5
  27. enum {
  28. RTC_SEC = 0,
  29. RTC_MIN,
  30. RTC_HOUR,
  31. RTC_WEEKDAY,
  32. RTC_DATE,
  33. RTC_MONTH,
  34. RTC_YEAR1,
  35. RTC_YEAR2,
  36. /* Make sure this is always the last enum name. */
  37. RTC_MAX_NUM_TIME_REGS
  38. };
  39. /*
  40. * Registers used by the driver which are different between chipsets.
  41. *
  42. * Operations like read time and write alarm/time require updating
  43. * specific fields in UDR register. These fields usually are auto-cleared
  44. * (with some exceptions).
  45. *
  46. * Table of operations per device:
  47. *
  48. * Device | Write time | Read time | Write alarm
  49. * =================================================
  50. * S5M8767 | UDR + TIME | | UDR
  51. * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
  52. * S2MPS13 | WUDR | RUDR | WUDR + AUDR
  53. * S2MPS15 | WUDR | RUDR | AUDR
  54. */
  55. struct s5m_rtc_reg_config {
  56. /* Number of registers used for setting time/alarm0/alarm1 */
  57. unsigned int regs_count;
  58. /* First register for time, seconds */
  59. unsigned int time;
  60. /* RTC control register */
  61. unsigned int ctrl;
  62. /* First register for alarm 0, seconds */
  63. unsigned int alarm0;
  64. /* First register for alarm 1, seconds */
  65. unsigned int alarm1;
  66. /*
  67. * Register for update flag (UDR). Typically setting UDR field to 1
  68. * will enable update of time or alarm register. Then it will be
  69. * auto-cleared after successful update.
  70. */
  71. unsigned int udr_update;
  72. /* Auto-cleared mask in UDR field for writing time and alarm */
  73. unsigned int autoclear_udr_mask;
  74. /*
  75. * Masks in UDR field for time and alarm operations.
  76. * The read time mask can be 0. Rest should not.
  77. */
  78. unsigned int read_time_udr_mask;
  79. unsigned int write_time_udr_mask;
  80. unsigned int write_alarm_udr_mask;
  81. };
  82. /* Register map for S5M8763 and S5M8767 */
  83. static const struct s5m_rtc_reg_config s5m_rtc_regs = {
  84. .regs_count = 8,
  85. .time = S5M_RTC_SEC,
  86. .ctrl = S5M_ALARM1_CONF,
  87. .alarm0 = S5M_ALARM0_SEC,
  88. .alarm1 = S5M_ALARM1_SEC,
  89. .udr_update = S5M_RTC_UDR_CON,
  90. .autoclear_udr_mask = S5M_RTC_UDR_MASK,
  91. .read_time_udr_mask = 0, /* Not needed */
  92. .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
  93. .write_alarm_udr_mask = S5M_RTC_UDR_MASK,
  94. };
  95. /* Register map for S2MPS13 */
  96. static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
  97. .regs_count = 7,
  98. .time = S2MPS_RTC_SEC,
  99. .ctrl = S2MPS_RTC_CTRL,
  100. .alarm0 = S2MPS_ALARM0_SEC,
  101. .alarm1 = S2MPS_ALARM1_SEC,
  102. .udr_update = S2MPS_RTC_UDR_CON,
  103. .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
  104. .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
  105. .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
  106. .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
  107. };
  108. /* Register map for S2MPS11/14 */
  109. static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
  110. .regs_count = 7,
  111. .time = S2MPS_RTC_SEC,
  112. .ctrl = S2MPS_RTC_CTRL,
  113. .alarm0 = S2MPS_ALARM0_SEC,
  114. .alarm1 = S2MPS_ALARM1_SEC,
  115. .udr_update = S2MPS_RTC_UDR_CON,
  116. .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
  117. .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
  118. .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
  119. .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
  120. };
  121. /*
  122. * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
  123. * are swapped.
  124. */
  125. static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
  126. .regs_count = 7,
  127. .time = S2MPS_RTC_SEC,
  128. .ctrl = S2MPS_RTC_CTRL,
  129. .alarm0 = S2MPS_ALARM0_SEC,
  130. .alarm1 = S2MPS_ALARM1_SEC,
  131. .udr_update = S2MPS_RTC_UDR_CON,
  132. .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
  133. .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
  134. .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
  135. .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
  136. };
  137. struct s5m_rtc_info {
  138. struct device *dev;
  139. struct i2c_client *i2c;
  140. struct sec_pmic_dev *s5m87xx;
  141. struct regmap *regmap;
  142. struct rtc_device *rtc_dev;
  143. int irq;
  144. enum sec_device_type device_type;
  145. int rtc_24hr_mode;
  146. const struct s5m_rtc_reg_config *regs;
  147. };
  148. static const struct regmap_config s5m_rtc_regmap_config = {
  149. .reg_bits = 8,
  150. .val_bits = 8,
  151. .max_register = S5M_RTC_REG_MAX,
  152. };
  153. static const struct regmap_config s2mps14_rtc_regmap_config = {
  154. .reg_bits = 8,
  155. .val_bits = 8,
  156. .max_register = S2MPS_RTC_REG_MAX,
  157. };
  158. static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
  159. int rtc_24hr_mode)
  160. {
  161. tm->tm_sec = data[RTC_SEC] & 0x7f;
  162. tm->tm_min = data[RTC_MIN] & 0x7f;
  163. if (rtc_24hr_mode) {
  164. tm->tm_hour = data[RTC_HOUR] & 0x1f;
  165. } else {
  166. tm->tm_hour = data[RTC_HOUR] & 0x0f;
  167. if (data[RTC_HOUR] & HOUR_PM_MASK)
  168. tm->tm_hour += 12;
  169. }
  170. tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
  171. tm->tm_mday = data[RTC_DATE] & 0x1f;
  172. tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
  173. tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
  174. tm->tm_yday = 0;
  175. tm->tm_isdst = 0;
  176. }
  177. static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
  178. {
  179. data[RTC_SEC] = tm->tm_sec;
  180. data[RTC_MIN] = tm->tm_min;
  181. if (tm->tm_hour >= 12)
  182. data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
  183. else
  184. data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
  185. data[RTC_WEEKDAY] = 1 << tm->tm_wday;
  186. data[RTC_DATE] = tm->tm_mday;
  187. data[RTC_MONTH] = tm->tm_mon + 1;
  188. data[RTC_YEAR1] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
  189. if (tm->tm_year < 100) {
  190. pr_err("RTC cannot handle the year %d\n",
  191. 1900 + tm->tm_year);
  192. return -EINVAL;
  193. } else {
  194. return 0;
  195. }
  196. }
  197. /*
  198. * Read RTC_UDR_CON register and wait till UDR field is cleared.
  199. * This indicates that time/alarm update ended.
  200. */
  201. static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
  202. {
  203. int ret, retry = UDR_READ_RETRY_CNT;
  204. unsigned int data;
  205. do {
  206. ret = regmap_read(info->regmap, info->regs->udr_update, &data);
  207. } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
  208. if (!retry)
  209. dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
  210. return ret;
  211. }
  212. static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info,
  213. struct rtc_wkalrm *alarm)
  214. {
  215. int ret;
  216. unsigned int val;
  217. switch (info->device_type) {
  218. case S5M8767X:
  219. case S5M8763X:
  220. ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
  221. val &= S5M_ALARM0_STATUS;
  222. break;
  223. case S2MPS15X:
  224. case S2MPS14X:
  225. case S2MPS13X:
  226. ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
  227. &val);
  228. val &= S2MPS_ALARM0_STATUS;
  229. break;
  230. default:
  231. return -EINVAL;
  232. }
  233. if (ret < 0)
  234. return ret;
  235. if (val)
  236. alarm->pending = 1;
  237. else
  238. alarm->pending = 0;
  239. return 0;
  240. }
  241. static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
  242. {
  243. int ret;
  244. unsigned int data;
  245. ret = regmap_read(info->regmap, info->regs->udr_update, &data);
  246. if (ret < 0) {
  247. dev_err(info->dev, "failed to read update reg(%d)\n", ret);
  248. return ret;
  249. }
  250. data |= info->regs->write_time_udr_mask;
  251. ret = regmap_write(info->regmap, info->regs->udr_update, data);
  252. if (ret < 0) {
  253. dev_err(info->dev, "failed to write update reg(%d)\n", ret);
  254. return ret;
  255. }
  256. ret = s5m8767_wait_for_udr_update(info);
  257. return ret;
  258. }
  259. static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
  260. {
  261. int ret;
  262. unsigned int data;
  263. ret = regmap_read(info->regmap, info->regs->udr_update, &data);
  264. if (ret < 0) {
  265. dev_err(info->dev, "%s: fail to read update reg(%d)\n",
  266. __func__, ret);
  267. return ret;
  268. }
  269. data |= info->regs->write_alarm_udr_mask;
  270. switch (info->device_type) {
  271. case S5M8763X:
  272. case S5M8767X:
  273. data &= ~S5M_RTC_TIME_EN_MASK;
  274. break;
  275. case S2MPS15X:
  276. case S2MPS14X:
  277. case S2MPS13X:
  278. /* No exceptions needed */
  279. break;
  280. default:
  281. return -EINVAL;
  282. }
  283. ret = regmap_write(info->regmap, info->regs->udr_update, data);
  284. if (ret < 0) {
  285. dev_err(info->dev, "%s: fail to write update reg(%d)\n",
  286. __func__, ret);
  287. return ret;
  288. }
  289. ret = s5m8767_wait_for_udr_update(info);
  290. /* On S2MPS13 the AUDR is not auto-cleared */
  291. if (info->device_type == S2MPS13X)
  292. regmap_update_bits(info->regmap, info->regs->udr_update,
  293. S2MPS13_RTC_AUDR_MASK, 0);
  294. return ret;
  295. }
  296. static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm)
  297. {
  298. tm->tm_sec = bcd2bin(data[RTC_SEC]);
  299. tm->tm_min = bcd2bin(data[RTC_MIN]);
  300. if (data[RTC_HOUR] & HOUR_12) {
  301. tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f);
  302. if (data[RTC_HOUR] & HOUR_PM)
  303. tm->tm_hour += 12;
  304. } else {
  305. tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
  306. }
  307. tm->tm_wday = data[RTC_WEEKDAY] & 0x07;
  308. tm->tm_mday = bcd2bin(data[RTC_DATE]);
  309. tm->tm_mon = bcd2bin(data[RTC_MONTH]);
  310. tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100;
  311. tm->tm_year -= 1900;
  312. }
  313. static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data)
  314. {
  315. data[RTC_SEC] = bin2bcd(tm->tm_sec);
  316. data[RTC_MIN] = bin2bcd(tm->tm_min);
  317. data[RTC_HOUR] = bin2bcd(tm->tm_hour);
  318. data[RTC_WEEKDAY] = tm->tm_wday;
  319. data[RTC_DATE] = bin2bcd(tm->tm_mday);
  320. data[RTC_MONTH] = bin2bcd(tm->tm_mon);
  321. data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100);
  322. data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100);
  323. }
  324. static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
  325. {
  326. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  327. u8 data[RTC_MAX_NUM_TIME_REGS];
  328. int ret;
  329. if (info->regs->read_time_udr_mask) {
  330. ret = regmap_update_bits(info->regmap,
  331. info->regs->udr_update,
  332. info->regs->read_time_udr_mask,
  333. info->regs->read_time_udr_mask);
  334. if (ret) {
  335. dev_err(dev,
  336. "Failed to prepare registers for time reading: %d\n",
  337. ret);
  338. return ret;
  339. }
  340. }
  341. ret = regmap_bulk_read(info->regmap, info->regs->time, data,
  342. info->regs->regs_count);
  343. if (ret < 0)
  344. return ret;
  345. switch (info->device_type) {
  346. case S5M8763X:
  347. s5m8763_data_to_tm(data, tm);
  348. break;
  349. case S5M8767X:
  350. case S2MPS15X:
  351. case S2MPS14X:
  352. case S2MPS13X:
  353. s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
  354. break;
  355. default:
  356. return -EINVAL;
  357. }
  358. dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
  359. return 0;
  360. }
  361. static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
  362. {
  363. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  364. u8 data[RTC_MAX_NUM_TIME_REGS];
  365. int ret = 0;
  366. switch (info->device_type) {
  367. case S5M8763X:
  368. s5m8763_tm_to_data(tm, data);
  369. break;
  370. case S5M8767X:
  371. case S2MPS15X:
  372. case S2MPS14X:
  373. case S2MPS13X:
  374. ret = s5m8767_tm_to_data(tm, data);
  375. break;
  376. default:
  377. return -EINVAL;
  378. }
  379. if (ret < 0)
  380. return ret;
  381. dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
  382. ret = regmap_raw_write(info->regmap, info->regs->time, data,
  383. info->regs->regs_count);
  384. if (ret < 0)
  385. return ret;
  386. ret = s5m8767_rtc_set_time_reg(info);
  387. return ret;
  388. }
  389. static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  390. {
  391. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  392. u8 data[RTC_MAX_NUM_TIME_REGS];
  393. unsigned int val;
  394. int ret, i;
  395. ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
  396. info->regs->regs_count);
  397. if (ret < 0)
  398. return ret;
  399. switch (info->device_type) {
  400. case S5M8763X:
  401. s5m8763_data_to_tm(data, &alrm->time);
  402. ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val);
  403. if (ret < 0)
  404. return ret;
  405. alrm->enabled = !!val;
  406. break;
  407. case S5M8767X:
  408. case S2MPS15X:
  409. case S2MPS14X:
  410. case S2MPS13X:
  411. s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
  412. alrm->enabled = 0;
  413. for (i = 0; i < info->regs->regs_count; i++) {
  414. if (data[i] & ALARM_ENABLE_MASK) {
  415. alrm->enabled = 1;
  416. break;
  417. }
  418. }
  419. break;
  420. default:
  421. return -EINVAL;
  422. }
  423. dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
  424. ret = s5m_check_peding_alarm_interrupt(info, alrm);
  425. return 0;
  426. }
  427. static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
  428. {
  429. u8 data[RTC_MAX_NUM_TIME_REGS];
  430. int ret, i;
  431. struct rtc_time tm;
  432. ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
  433. info->regs->regs_count);
  434. if (ret < 0)
  435. return ret;
  436. s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
  437. dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
  438. switch (info->device_type) {
  439. case S5M8763X:
  440. ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0);
  441. break;
  442. case S5M8767X:
  443. case S2MPS15X:
  444. case S2MPS14X:
  445. case S2MPS13X:
  446. for (i = 0; i < info->regs->regs_count; i++)
  447. data[i] &= ~ALARM_ENABLE_MASK;
  448. ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
  449. info->regs->regs_count);
  450. if (ret < 0)
  451. return ret;
  452. ret = s5m8767_rtc_set_alarm_reg(info);
  453. break;
  454. default:
  455. return -EINVAL;
  456. }
  457. return ret;
  458. }
  459. static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
  460. {
  461. int ret;
  462. u8 data[RTC_MAX_NUM_TIME_REGS];
  463. u8 alarm0_conf;
  464. struct rtc_time tm;
  465. ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
  466. info->regs->regs_count);
  467. if (ret < 0)
  468. return ret;
  469. s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
  470. dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
  471. switch (info->device_type) {
  472. case S5M8763X:
  473. alarm0_conf = 0x77;
  474. ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf);
  475. break;
  476. case S5M8767X:
  477. case S2MPS15X:
  478. case S2MPS14X:
  479. case S2MPS13X:
  480. data[RTC_SEC] |= ALARM_ENABLE_MASK;
  481. data[RTC_MIN] |= ALARM_ENABLE_MASK;
  482. data[RTC_HOUR] |= ALARM_ENABLE_MASK;
  483. data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
  484. if (data[RTC_DATE] & 0x1f)
  485. data[RTC_DATE] |= ALARM_ENABLE_MASK;
  486. if (data[RTC_MONTH] & 0xf)
  487. data[RTC_MONTH] |= ALARM_ENABLE_MASK;
  488. if (data[RTC_YEAR1] & 0x7f)
  489. data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
  490. ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
  491. info->regs->regs_count);
  492. if (ret < 0)
  493. return ret;
  494. ret = s5m8767_rtc_set_alarm_reg(info);
  495. break;
  496. default:
  497. return -EINVAL;
  498. }
  499. return ret;
  500. }
  501. static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  502. {
  503. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  504. u8 data[RTC_MAX_NUM_TIME_REGS];
  505. int ret;
  506. switch (info->device_type) {
  507. case S5M8763X:
  508. s5m8763_tm_to_data(&alrm->time, data);
  509. break;
  510. case S5M8767X:
  511. case S2MPS15X:
  512. case S2MPS14X:
  513. case S2MPS13X:
  514. s5m8767_tm_to_data(&alrm->time, data);
  515. break;
  516. default:
  517. return -EINVAL;
  518. }
  519. dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
  520. ret = s5m_rtc_stop_alarm(info);
  521. if (ret < 0)
  522. return ret;
  523. ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
  524. info->regs->regs_count);
  525. if (ret < 0)
  526. return ret;
  527. ret = s5m8767_rtc_set_alarm_reg(info);
  528. if (ret < 0)
  529. return ret;
  530. if (alrm->enabled)
  531. ret = s5m_rtc_start_alarm(info);
  532. return ret;
  533. }
  534. static int s5m_rtc_alarm_irq_enable(struct device *dev,
  535. unsigned int enabled)
  536. {
  537. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  538. if (enabled)
  539. return s5m_rtc_start_alarm(info);
  540. else
  541. return s5m_rtc_stop_alarm(info);
  542. }
  543. static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
  544. {
  545. struct s5m_rtc_info *info = data;
  546. rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
  547. return IRQ_HANDLED;
  548. }
  549. static const struct rtc_class_ops s5m_rtc_ops = {
  550. .read_time = s5m_rtc_read_time,
  551. .set_time = s5m_rtc_set_time,
  552. .read_alarm = s5m_rtc_read_alarm,
  553. .set_alarm = s5m_rtc_set_alarm,
  554. .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
  555. };
  556. static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
  557. {
  558. u8 data[2];
  559. int ret;
  560. switch (info->device_type) {
  561. case S5M8763X:
  562. case S5M8767X:
  563. /* UDR update time. Default of 7.32 ms is too long. */
  564. ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
  565. S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
  566. if (ret < 0)
  567. dev_err(info->dev, "%s: fail to change UDR time: %d\n",
  568. __func__, ret);
  569. /* Set RTC control register : Binary mode, 24hour mode */
  570. data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  571. data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  572. ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
  573. break;
  574. case S2MPS15X:
  575. case S2MPS14X:
  576. case S2MPS13X:
  577. data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  578. ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
  579. if (ret < 0)
  580. break;
  581. /*
  582. * Should set WUDR & (RUDR or AUDR) bits to high after writing
  583. * RTC_CTRL register like writing Alarm registers. We can't find
  584. * the description from datasheet but vendor code does that
  585. * really.
  586. */
  587. ret = s5m8767_rtc_set_alarm_reg(info);
  588. break;
  589. default:
  590. return -EINVAL;
  591. }
  592. info->rtc_24hr_mode = 1;
  593. if (ret < 0) {
  594. dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
  595. __func__, ret);
  596. return ret;
  597. }
  598. return ret;
  599. }
  600. static int s5m_rtc_probe(struct platform_device *pdev)
  601. {
  602. struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
  603. struct sec_platform_data *pdata = s5m87xx->pdata;
  604. struct s5m_rtc_info *info;
  605. const struct regmap_config *regmap_cfg;
  606. int ret, alarm_irq;
  607. if (!pdata) {
  608. dev_err(pdev->dev.parent, "Platform data not supplied\n");
  609. return -ENODEV;
  610. }
  611. info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
  612. if (!info)
  613. return -ENOMEM;
  614. switch (platform_get_device_id(pdev)->driver_data) {
  615. case S2MPS15X:
  616. regmap_cfg = &s2mps14_rtc_regmap_config;
  617. info->regs = &s2mps15_rtc_regs;
  618. alarm_irq = S2MPS14_IRQ_RTCA0;
  619. break;
  620. case S2MPS14X:
  621. regmap_cfg = &s2mps14_rtc_regmap_config;
  622. info->regs = &s2mps14_rtc_regs;
  623. alarm_irq = S2MPS14_IRQ_RTCA0;
  624. break;
  625. case S2MPS13X:
  626. regmap_cfg = &s2mps14_rtc_regmap_config;
  627. info->regs = &s2mps13_rtc_regs;
  628. alarm_irq = S2MPS14_IRQ_RTCA0;
  629. break;
  630. case S5M8763X:
  631. regmap_cfg = &s5m_rtc_regmap_config;
  632. info->regs = &s5m_rtc_regs;
  633. alarm_irq = S5M8763_IRQ_ALARM0;
  634. break;
  635. case S5M8767X:
  636. regmap_cfg = &s5m_rtc_regmap_config;
  637. info->regs = &s5m_rtc_regs;
  638. alarm_irq = S5M8767_IRQ_RTCA1;
  639. break;
  640. default:
  641. dev_err(&pdev->dev,
  642. "Device type %lu is not supported by RTC driver\n",
  643. platform_get_device_id(pdev)->driver_data);
  644. return -ENODEV;
  645. }
  646. info->i2c = i2c_new_dummy_device(s5m87xx->i2c->adapter, RTC_I2C_ADDR);
  647. if (IS_ERR(info->i2c)) {
  648. dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n");
  649. return PTR_ERR(info->i2c);
  650. }
  651. info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg);
  652. if (IS_ERR(info->regmap)) {
  653. ret = PTR_ERR(info->regmap);
  654. dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n",
  655. ret);
  656. goto err;
  657. }
  658. info->dev = &pdev->dev;
  659. info->s5m87xx = s5m87xx;
  660. info->device_type = platform_get_device_id(pdev)->driver_data;
  661. if (s5m87xx->irq_data) {
  662. info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
  663. if (info->irq <= 0) {
  664. ret = -EINVAL;
  665. dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n",
  666. alarm_irq);
  667. goto err;
  668. }
  669. }
  670. platform_set_drvdata(pdev, info);
  671. ret = s5m8767_rtc_init_reg(info);
  672. device_init_wakeup(&pdev->dev, 1);
  673. info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc",
  674. &s5m_rtc_ops, THIS_MODULE);
  675. if (IS_ERR(info->rtc_dev)) {
  676. ret = PTR_ERR(info->rtc_dev);
  677. goto err;
  678. }
  679. if (!info->irq) {
  680. dev_info(&pdev->dev, "Alarm IRQ not available\n");
  681. return 0;
  682. }
  683. ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
  684. s5m_rtc_alarm_irq, 0, "rtc-alarm0",
  685. info);
  686. if (ret < 0) {
  687. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  688. info->irq, ret);
  689. goto err;
  690. }
  691. return 0;
  692. err:
  693. i2c_unregister_device(info->i2c);
  694. return ret;
  695. }
  696. static int s5m_rtc_remove(struct platform_device *pdev)
  697. {
  698. struct s5m_rtc_info *info = platform_get_drvdata(pdev);
  699. i2c_unregister_device(info->i2c);
  700. return 0;
  701. }
  702. #ifdef CONFIG_PM_SLEEP
  703. static int s5m_rtc_resume(struct device *dev)
  704. {
  705. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  706. int ret = 0;
  707. if (info->irq && device_may_wakeup(dev))
  708. ret = disable_irq_wake(info->irq);
  709. return ret;
  710. }
  711. static int s5m_rtc_suspend(struct device *dev)
  712. {
  713. struct s5m_rtc_info *info = dev_get_drvdata(dev);
  714. int ret = 0;
  715. if (info->irq && device_may_wakeup(dev))
  716. ret = enable_irq_wake(info->irq);
  717. return ret;
  718. }
  719. #endif /* CONFIG_PM_SLEEP */
  720. static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
  721. static const struct platform_device_id s5m_rtc_id[] = {
  722. { "s5m-rtc", S5M8767X },
  723. { "s2mps13-rtc", S2MPS13X },
  724. { "s2mps14-rtc", S2MPS14X },
  725. { "s2mps15-rtc", S2MPS15X },
  726. { },
  727. };
  728. MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
  729. static struct platform_driver s5m_rtc_driver = {
  730. .driver = {
  731. .name = "s5m-rtc",
  732. .pm = &s5m_rtc_pm_ops,
  733. },
  734. .probe = s5m_rtc_probe,
  735. .remove = s5m_rtc_remove,
  736. .id_table = s5m_rtc_id,
  737. };
  738. module_platform_driver(s5m_rtc_driver);
  739. /* Module information */
  740. MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
  741. MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
  742. MODULE_LICENSE("GPL");
  743. MODULE_ALIAS("platform:s5m-rtc");