rtc-rs5c313.c 10 KB

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  1. /*
  2. * Ricoh RS5C313 RTC device/driver
  3. * Copyright (C) 2007 Nobuhiro Iwamatsu
  4. *
  5. * 2005-09-19 modifed by kogiidena
  6. *
  7. * Based on the old drivers/char/rs5c313_rtc.c by:
  8. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  9. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  10. *
  11. * Based on code written by Paul Gortmaker.
  12. * Copyright (C) 1996 Paul Gortmaker
  13. *
  14. * This file is subject to the terms and conditions of the GNU General Public
  15. * License. See the file "COPYING" in the main directory of this archive
  16. * for more details.
  17. *
  18. * Based on other minimal char device drivers, like Alan's
  19. * watchdog, Ted's random, etc. etc.
  20. *
  21. * 1.07 Paul Gortmaker.
  22. * 1.08 Miquel van Smoorenburg: disallow certain things on the
  23. * DEC Alpha as the CMOS clock is also used for other things.
  24. * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
  25. * 1.09a Pete Zaitcev: Sun SPARC
  26. * 1.09b Jeff Garzik: Modularize, init cleanup
  27. * 1.09c Jeff Garzik: SMP cleanup
  28. * 1.10 Paul Barton-Davis: add support for async I/O
  29. * 1.10a Andrea Arcangeli: Alpha updates
  30. * 1.10b Andrew Morton: SMP lock fix
  31. * 1.10c Cesar Barros: SMP locking fixes and cleanup
  32. * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
  33. * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness.
  34. * 1.11 Takashi Iwai: Kernel access functions
  35. * rtc_register/rtc_unregister/rtc_control
  36. * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
  37. * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
  38. * CONFIG_HPET_EMULATE_RTC
  39. * 1.13 Nobuhiro Iwamatsu: Updata driver.
  40. */
  41. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42. #include <linux/module.h>
  43. #include <linux/err.h>
  44. #include <linux/rtc.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/bcd.h>
  47. #include <linux/delay.h>
  48. #include <linux/io.h>
  49. #define DRV_NAME "rs5c313"
  50. #ifdef CONFIG_SH_LANDISK
  51. /*****************************************************/
  52. /* LANDISK dependence part of RS5C313 */
  53. /*****************************************************/
  54. #define SCSMR1 0xFFE00000
  55. #define SCSCR1 0xFFE00008
  56. #define SCSMR1_CA 0x80
  57. #define SCSCR1_CKE 0x03
  58. #define SCSPTR1 0xFFE0001C
  59. #define SCSPTR1_EIO 0x80
  60. #define SCSPTR1_SPB1IO 0x08
  61. #define SCSPTR1_SPB1DT 0x04
  62. #define SCSPTR1_SPB0IO 0x02
  63. #define SCSPTR1_SPB0DT 0x01
  64. #define SDA_OEN SCSPTR1_SPB1IO
  65. #define SDA SCSPTR1_SPB1DT
  66. #define SCL_OEN SCSPTR1_SPB0IO
  67. #define SCL SCSPTR1_SPB0DT
  68. /* RICOH RS5C313 CE port */
  69. #define RS5C313_CE 0xB0000003
  70. /* RICOH RS5C313 CE port bit */
  71. #define RS5C313_CE_RTCCE 0x02
  72. /* SCSPTR1 data */
  73. unsigned char scsptr1_data;
  74. #define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
  75. #define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
  76. #define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
  77. static void rs5c313_init_port(void)
  78. {
  79. /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
  80. __raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
  81. __raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
  82. /* And Initialize SCL for RS5C313 clock */
  83. scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
  84. __raw_writeb(scsptr1_data, SCSPTR1);
  85. scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */
  86. __raw_writeb(scsptr1_data, SCSPTR1);
  87. RS5C313_CEDISABLE; /* CE:L */
  88. }
  89. static void rs5c313_write_data(unsigned char data)
  90. {
  91. int i;
  92. for (i = 0; i < 8; i++) {
  93. /* SDA:Write Data */
  94. scsptr1_data = (scsptr1_data & ~SDA) |
  95. ((((0x80 >> i) & data) >> (7 - i)) << 2);
  96. __raw_writeb(scsptr1_data, SCSPTR1);
  97. if (i == 0) {
  98. scsptr1_data |= SDA_OEN; /* SDA:output enable */
  99. __raw_writeb(scsptr1_data, SCSPTR1);
  100. }
  101. ndelay(700);
  102. scsptr1_data &= ~SCL; /* SCL:L */
  103. __raw_writeb(scsptr1_data, SCSPTR1);
  104. ndelay(700);
  105. scsptr1_data |= SCL; /* SCL:H */
  106. __raw_writeb(scsptr1_data, SCSPTR1);
  107. }
  108. scsptr1_data &= ~SDA_OEN; /* SDA:output disable */
  109. __raw_writeb(scsptr1_data, SCSPTR1);
  110. }
  111. static unsigned char rs5c313_read_data(void)
  112. {
  113. int i;
  114. unsigned char data = 0;
  115. for (i = 0; i < 8; i++) {
  116. ndelay(700);
  117. /* SDA:Read Data */
  118. data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
  119. scsptr1_data &= ~SCL; /* SCL:L */
  120. __raw_writeb(scsptr1_data, SCSPTR1);
  121. ndelay(700);
  122. scsptr1_data |= SCL; /* SCL:H */
  123. __raw_writeb(scsptr1_data, SCSPTR1);
  124. }
  125. return data & 0x0F;
  126. }
  127. #endif /* CONFIG_SH_LANDISK */
  128. /*****************************************************/
  129. /* machine independence part of RS5C313 */
  130. /*****************************************************/
  131. /* RICOH RS5C313 address */
  132. #define RS5C313_ADDR_SEC 0x00
  133. #define RS5C313_ADDR_SEC10 0x01
  134. #define RS5C313_ADDR_MIN 0x02
  135. #define RS5C313_ADDR_MIN10 0x03
  136. #define RS5C313_ADDR_HOUR 0x04
  137. #define RS5C313_ADDR_HOUR10 0x05
  138. #define RS5C313_ADDR_WEEK 0x06
  139. #define RS5C313_ADDR_INTINTVREG 0x07
  140. #define RS5C313_ADDR_DAY 0x08
  141. #define RS5C313_ADDR_DAY10 0x09
  142. #define RS5C313_ADDR_MON 0x0A
  143. #define RS5C313_ADDR_MON10 0x0B
  144. #define RS5C313_ADDR_YEAR 0x0C
  145. #define RS5C313_ADDR_YEAR10 0x0D
  146. #define RS5C313_ADDR_CNTREG 0x0E
  147. #define RS5C313_ADDR_TESTREG 0x0F
  148. /* RICOH RS5C313 control register */
  149. #define RS5C313_CNTREG_ADJ_BSY 0x01
  150. #define RS5C313_CNTREG_WTEN_XSTP 0x02
  151. #define RS5C313_CNTREG_12_24 0x04
  152. #define RS5C313_CNTREG_CTFG 0x08
  153. /* RICOH RS5C313 test register */
  154. #define RS5C313_TESTREG_TEST 0x01
  155. /* RICOH RS5C313 control bit */
  156. #define RS5C313_CNTBIT_READ 0x40
  157. #define RS5C313_CNTBIT_AD 0x20
  158. #define RS5C313_CNTBIT_DT 0x10
  159. static unsigned char rs5c313_read_reg(unsigned char addr)
  160. {
  161. rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD);
  162. return rs5c313_read_data();
  163. }
  164. static void rs5c313_write_reg(unsigned char addr, unsigned char data)
  165. {
  166. data &= 0x0f;
  167. rs5c313_write_data(addr | RS5C313_CNTBIT_AD);
  168. rs5c313_write_data(data | RS5C313_CNTBIT_DT);
  169. return;
  170. }
  171. static inline unsigned char rs5c313_read_cntreg(void)
  172. {
  173. return rs5c313_read_reg(RS5C313_ADDR_CNTREG);
  174. }
  175. static inline void rs5c313_write_cntreg(unsigned char data)
  176. {
  177. rs5c313_write_reg(RS5C313_ADDR_CNTREG, data);
  178. }
  179. static inline void rs5c313_write_intintvreg(unsigned char data)
  180. {
  181. rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data);
  182. }
  183. static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm)
  184. {
  185. int data;
  186. int cnt;
  187. cnt = 0;
  188. while (1) {
  189. RS5C313_CEENABLE; /* CE:H */
  190. /* Initialize control reg. 24 hour */
  191. rs5c313_write_cntreg(0x04);
  192. if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
  193. break;
  194. RS5C313_CEDISABLE;
  195. ndelay(700); /* CE:L */
  196. if (cnt++ > 100) {
  197. dev_err(dev, "%s: timeout error\n", __func__);
  198. return -EIO;
  199. }
  200. }
  201. data = rs5c313_read_reg(RS5C313_ADDR_SEC);
  202. data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4);
  203. tm->tm_sec = bcd2bin(data);
  204. data = rs5c313_read_reg(RS5C313_ADDR_MIN);
  205. data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4);
  206. tm->tm_min = bcd2bin(data);
  207. data = rs5c313_read_reg(RS5C313_ADDR_HOUR);
  208. data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4);
  209. tm->tm_hour = bcd2bin(data);
  210. data = rs5c313_read_reg(RS5C313_ADDR_DAY);
  211. data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4);
  212. tm->tm_mday = bcd2bin(data);
  213. data = rs5c313_read_reg(RS5C313_ADDR_MON);
  214. data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4);
  215. tm->tm_mon = bcd2bin(data) - 1;
  216. data = rs5c313_read_reg(RS5C313_ADDR_YEAR);
  217. data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4);
  218. tm->tm_year = bcd2bin(data);
  219. if (tm->tm_year < 70)
  220. tm->tm_year += 100;
  221. data = rs5c313_read_reg(RS5C313_ADDR_WEEK);
  222. tm->tm_wday = bcd2bin(data);
  223. RS5C313_CEDISABLE;
  224. ndelay(700); /* CE:L */
  225. return 0;
  226. }
  227. static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm)
  228. {
  229. int data;
  230. int cnt;
  231. cnt = 0;
  232. /* busy check. */
  233. while (1) {
  234. RS5C313_CEENABLE; /* CE:H */
  235. /* Initiatlize control reg. 24 hour */
  236. rs5c313_write_cntreg(0x04);
  237. if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
  238. break;
  239. RS5C313_MISCOP;
  240. RS5C313_CEDISABLE;
  241. ndelay(700); /* CE:L */
  242. if (cnt++ > 100) {
  243. dev_err(dev, "%s: timeout error\n", __func__);
  244. return -EIO;
  245. }
  246. }
  247. data = bin2bcd(tm->tm_sec);
  248. rs5c313_write_reg(RS5C313_ADDR_SEC, data);
  249. rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4));
  250. data = bin2bcd(tm->tm_min);
  251. rs5c313_write_reg(RS5C313_ADDR_MIN, data);
  252. rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4));
  253. data = bin2bcd(tm->tm_hour);
  254. rs5c313_write_reg(RS5C313_ADDR_HOUR, data);
  255. rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4));
  256. data = bin2bcd(tm->tm_mday);
  257. rs5c313_write_reg(RS5C313_ADDR_DAY, data);
  258. rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4));
  259. data = bin2bcd(tm->tm_mon + 1);
  260. rs5c313_write_reg(RS5C313_ADDR_MON, data);
  261. rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4));
  262. data = bin2bcd(tm->tm_year % 100);
  263. rs5c313_write_reg(RS5C313_ADDR_YEAR, data);
  264. rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4));
  265. data = bin2bcd(tm->tm_wday);
  266. rs5c313_write_reg(RS5C313_ADDR_WEEK, data);
  267. RS5C313_CEDISABLE; /* CE:H */
  268. ndelay(700);
  269. return 0;
  270. }
  271. static void rs5c313_check_xstp_bit(void)
  272. {
  273. struct rtc_time tm;
  274. int cnt;
  275. RS5C313_CEENABLE; /* CE:H */
  276. if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) {
  277. /* INT interval reg. OFF */
  278. rs5c313_write_intintvreg(0x00);
  279. /* Initialize control reg. 24 hour & adjust */
  280. rs5c313_write_cntreg(0x07);
  281. /* busy check. */
  282. for (cnt = 0; cnt < 100; cnt++) {
  283. if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
  284. break;
  285. RS5C313_MISCOP;
  286. }
  287. memset(&tm, 0, sizeof(struct rtc_time));
  288. tm.tm_mday = 1;
  289. tm.tm_mon = 1 - 1;
  290. tm.tm_year = 2000 - 1900;
  291. rs5c313_rtc_set_time(NULL, &tm);
  292. pr_err("invalid value, resetting to 1 Jan 2000\n");
  293. }
  294. RS5C313_CEDISABLE;
  295. ndelay(700); /* CE:L */
  296. }
  297. static const struct rtc_class_ops rs5c313_rtc_ops = {
  298. .read_time = rs5c313_rtc_read_time,
  299. .set_time = rs5c313_rtc_set_time,
  300. };
  301. static int rs5c313_rtc_probe(struct platform_device *pdev)
  302. {
  303. struct rtc_device *rtc;
  304. rs5c313_init_port();
  305. rs5c313_check_xstp_bit();
  306. rtc = devm_rtc_device_register(&pdev->dev, "rs5c313", &rs5c313_rtc_ops,
  307. THIS_MODULE);
  308. return PTR_ERR_OR_ZERO(rtc);
  309. }
  310. static struct platform_driver rs5c313_rtc_platform_driver = {
  311. .driver = {
  312. .name = DRV_NAME,
  313. },
  314. .probe = rs5c313_rtc_probe,
  315. };
  316. module_platform_driver(rs5c313_rtc_platform_driver);
  317. MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwamatsu@nigauri.org>");
  318. MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
  319. MODULE_LICENSE("GPL");
  320. MODULE_ALIAS("platform:" DRV_NAME);