rtc-pxa.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Real Time Clock interface for XScale PXA27x and PXA3xx
  4. *
  5. * Copyright (C) 2008 Robert Jarzmik
  6. */
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/rtc.h>
  11. #include <linux/seq_file.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/slab.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <mach/hardware.h>
  18. #include "rtc-sa1100.h"
  19. #define RTC_DEF_DIVIDER (32768 - 1)
  20. #define RTC_DEF_TRIM 0
  21. #define MAXFREQ_PERIODIC 1000
  22. /*
  23. * PXA Registers and bits definitions
  24. */
  25. #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
  26. #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
  27. #define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
  28. #define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
  29. #define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
  30. #define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
  31. #define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
  32. #define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
  33. #define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
  34. #define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
  35. #define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
  36. #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
  37. #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
  38. #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
  39. #define RTSR_AL (1 << 0) /* RTC alarm detected */
  40. #define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
  41. | RTSR_SWAL1 | RTSR_SWAL2)
  42. #define RYxR_YEAR_S 9
  43. #define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
  44. #define RYxR_MONTH_S 5
  45. #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
  46. #define RYxR_DAY_MASK 0x1f
  47. #define RDxR_WOM_S 20
  48. #define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
  49. #define RDxR_DOW_S 17
  50. #define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
  51. #define RDxR_HOUR_S 12
  52. #define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
  53. #define RDxR_MIN_S 6
  54. #define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
  55. #define RDxR_SEC_MASK 0x3f
  56. #define RTSR 0x08
  57. #define RTTR 0x0c
  58. #define RDCR 0x10
  59. #define RYCR 0x14
  60. #define RDAR1 0x18
  61. #define RYAR1 0x1c
  62. #define RTCPICR 0x34
  63. #define PIAR 0x38
  64. #define rtc_readl(pxa_rtc, reg) \
  65. __raw_readl((pxa_rtc)->base + (reg))
  66. #define rtc_writel(pxa_rtc, reg, value) \
  67. __raw_writel((value), (pxa_rtc)->base + (reg))
  68. struct pxa_rtc {
  69. struct sa1100_rtc sa1100_rtc;
  70. struct resource *ress;
  71. void __iomem *base;
  72. struct rtc_device *rtc;
  73. spinlock_t lock; /* Protects this structure */
  74. };
  75. static u32 ryxr_calc(struct rtc_time *tm)
  76. {
  77. return ((tm->tm_year + 1900) << RYxR_YEAR_S)
  78. | ((tm->tm_mon + 1) << RYxR_MONTH_S)
  79. | tm->tm_mday;
  80. }
  81. static u32 rdxr_calc(struct rtc_time *tm)
  82. {
  83. return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
  84. | (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
  85. | (tm->tm_hour << RDxR_HOUR_S)
  86. | (tm->tm_min << RDxR_MIN_S)
  87. | tm->tm_sec;
  88. }
  89. static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
  90. {
  91. tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
  92. tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
  93. tm->tm_mday = (rycr & RYxR_DAY_MASK);
  94. tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
  95. tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
  96. tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
  97. tm->tm_sec = rdcr & RDxR_SEC_MASK;
  98. }
  99. static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
  100. {
  101. u32 rtsr;
  102. rtsr = rtc_readl(pxa_rtc, RTSR);
  103. rtsr &= ~RTSR_TRIG_MASK;
  104. rtsr &= ~mask;
  105. rtc_writel(pxa_rtc, RTSR, rtsr);
  106. }
  107. static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
  108. {
  109. u32 rtsr;
  110. rtsr = rtc_readl(pxa_rtc, RTSR);
  111. rtsr &= ~RTSR_TRIG_MASK;
  112. rtsr |= mask;
  113. rtc_writel(pxa_rtc, RTSR, rtsr);
  114. }
  115. static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
  116. {
  117. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
  118. u32 rtsr;
  119. unsigned long events = 0;
  120. spin_lock(&pxa_rtc->lock);
  121. /* clear interrupt sources */
  122. rtsr = rtc_readl(pxa_rtc, RTSR);
  123. rtc_writel(pxa_rtc, RTSR, rtsr);
  124. /* temporary disable rtc interrupts */
  125. rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
  126. /* clear alarm interrupt if it has occurred */
  127. if (rtsr & RTSR_RDAL1)
  128. rtsr &= ~RTSR_RDALE1;
  129. /* update irq data & counter */
  130. if (rtsr & RTSR_RDAL1)
  131. events |= RTC_AF | RTC_IRQF;
  132. if (rtsr & RTSR_HZ)
  133. events |= RTC_UF | RTC_IRQF;
  134. if (rtsr & RTSR_PIAL)
  135. events |= RTC_PF | RTC_IRQF;
  136. rtc_update_irq(pxa_rtc->rtc, 1, events);
  137. /* enable back rtc interrupts */
  138. rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
  139. spin_unlock(&pxa_rtc->lock);
  140. return IRQ_HANDLED;
  141. }
  142. static int pxa_rtc_open(struct device *dev)
  143. {
  144. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  145. int ret;
  146. ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
  147. "rtc 1Hz", dev);
  148. if (ret < 0) {
  149. dev_err(dev, "can't get irq %i, err %d\n",
  150. pxa_rtc->sa1100_rtc.irq_1hz, ret);
  151. goto err_irq_1Hz;
  152. }
  153. ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
  154. "rtc Alrm", dev);
  155. if (ret < 0) {
  156. dev_err(dev, "can't get irq %i, err %d\n",
  157. pxa_rtc->sa1100_rtc.irq_alarm, ret);
  158. goto err_irq_Alrm;
  159. }
  160. return 0;
  161. err_irq_Alrm:
  162. free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
  163. err_irq_1Hz:
  164. return ret;
  165. }
  166. static void pxa_rtc_release(struct device *dev)
  167. {
  168. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  169. spin_lock_irq(&pxa_rtc->lock);
  170. rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
  171. spin_unlock_irq(&pxa_rtc->lock);
  172. free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
  173. free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
  174. }
  175. static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
  176. {
  177. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  178. spin_lock_irq(&pxa_rtc->lock);
  179. if (enabled)
  180. rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
  181. else
  182. rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
  183. spin_unlock_irq(&pxa_rtc->lock);
  184. return 0;
  185. }
  186. static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
  187. {
  188. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  189. u32 rycr, rdcr;
  190. rycr = rtc_readl(pxa_rtc, RYCR);
  191. rdcr = rtc_readl(pxa_rtc, RDCR);
  192. tm_calc(rycr, rdcr, tm);
  193. return 0;
  194. }
  195. static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
  196. {
  197. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  198. rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
  199. rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
  200. return 0;
  201. }
  202. static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  203. {
  204. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  205. u32 rtsr, ryar, rdar;
  206. ryar = rtc_readl(pxa_rtc, RYAR1);
  207. rdar = rtc_readl(pxa_rtc, RDAR1);
  208. tm_calc(ryar, rdar, &alrm->time);
  209. rtsr = rtc_readl(pxa_rtc, RTSR);
  210. alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
  211. alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
  212. return 0;
  213. }
  214. static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  215. {
  216. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  217. u32 rtsr;
  218. spin_lock_irq(&pxa_rtc->lock);
  219. rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
  220. rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
  221. rtsr = rtc_readl(pxa_rtc, RTSR);
  222. if (alrm->enabled)
  223. rtsr |= RTSR_RDALE1;
  224. else
  225. rtsr &= ~RTSR_RDALE1;
  226. rtc_writel(pxa_rtc, RTSR, rtsr);
  227. spin_unlock_irq(&pxa_rtc->lock);
  228. return 0;
  229. }
  230. static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
  231. {
  232. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  233. seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
  234. seq_printf(seq, "update_IRQ\t: %s\n",
  235. (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
  236. seq_printf(seq, "periodic_IRQ\t: %s\n",
  237. (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
  238. seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
  239. return 0;
  240. }
  241. static const struct rtc_class_ops pxa_rtc_ops = {
  242. .read_time = pxa_rtc_read_time,
  243. .set_time = pxa_rtc_set_time,
  244. .read_alarm = pxa_rtc_read_alarm,
  245. .set_alarm = pxa_rtc_set_alarm,
  246. .alarm_irq_enable = pxa_alarm_irq_enable,
  247. .proc = pxa_rtc_proc,
  248. };
  249. static int __init pxa_rtc_probe(struct platform_device *pdev)
  250. {
  251. struct device *dev = &pdev->dev;
  252. struct pxa_rtc *pxa_rtc;
  253. struct sa1100_rtc *sa1100_rtc;
  254. int ret;
  255. pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
  256. if (!pxa_rtc)
  257. return -ENOMEM;
  258. sa1100_rtc = &pxa_rtc->sa1100_rtc;
  259. spin_lock_init(&pxa_rtc->lock);
  260. platform_set_drvdata(pdev, pxa_rtc);
  261. pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  262. if (!pxa_rtc->ress) {
  263. dev_err(dev, "No I/O memory resource defined\n");
  264. return -ENXIO;
  265. }
  266. sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
  267. if (sa1100_rtc->irq_1hz < 0)
  268. return -ENXIO;
  269. sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
  270. if (sa1100_rtc->irq_alarm < 0)
  271. return -ENXIO;
  272. sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
  273. if (IS_ERR(sa1100_rtc->rtc))
  274. return PTR_ERR(sa1100_rtc->rtc);
  275. pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
  276. resource_size(pxa_rtc->ress));
  277. if (!pxa_rtc->base) {
  278. dev_err(dev, "Unable to map pxa RTC I/O memory\n");
  279. return -ENOMEM;
  280. }
  281. pxa_rtc_open(dev);
  282. sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
  283. sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
  284. sa1100_rtc->rtar = pxa_rtc->base + 0x4;
  285. sa1100_rtc->rttr = pxa_rtc->base + 0xc;
  286. ret = sa1100_rtc_init(pdev, sa1100_rtc);
  287. if (ret) {
  288. dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
  289. return ret;
  290. }
  291. rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
  292. pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
  293. &pxa_rtc_ops, THIS_MODULE);
  294. if (IS_ERR(pxa_rtc->rtc)) {
  295. ret = PTR_ERR(pxa_rtc->rtc);
  296. dev_err(dev, "Failed to register RTC device -> %d\n", ret);
  297. return ret;
  298. }
  299. device_init_wakeup(dev, 1);
  300. return 0;
  301. }
  302. static int __exit pxa_rtc_remove(struct platform_device *pdev)
  303. {
  304. struct device *dev = &pdev->dev;
  305. pxa_rtc_release(dev);
  306. return 0;
  307. }
  308. #ifdef CONFIG_OF
  309. static const struct of_device_id pxa_rtc_dt_ids[] = {
  310. { .compatible = "marvell,pxa-rtc" },
  311. {}
  312. };
  313. MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
  314. #endif
  315. #ifdef CONFIG_PM_SLEEP
  316. static int pxa_rtc_suspend(struct device *dev)
  317. {
  318. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  319. if (device_may_wakeup(dev))
  320. enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
  321. return 0;
  322. }
  323. static int pxa_rtc_resume(struct device *dev)
  324. {
  325. struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
  326. if (device_may_wakeup(dev))
  327. disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
  328. return 0;
  329. }
  330. #endif
  331. static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
  332. static struct platform_driver pxa_rtc_driver = {
  333. .remove = __exit_p(pxa_rtc_remove),
  334. .driver = {
  335. .name = "pxa-rtc",
  336. .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
  337. .pm = &pxa_rtc_pm_ops,
  338. },
  339. };
  340. module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
  341. MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
  342. MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
  343. MODULE_LICENSE("GPL");
  344. MODULE_ALIAS("platform:pxa-rtc");