rtc-pm8xxx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  3. */
  4. #include <linux/of.h>
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/rtc.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm.h>
  10. #include <linux/regmap.h>
  11. #include <linux/slab.h>
  12. #include <linux/spinlock.h>
  13. /* RTC Register offsets from RTC CTRL REG */
  14. #define PM8XXX_ALARM_CTRL_OFFSET 0x01
  15. #define PM8XXX_RTC_WRITE_OFFSET 0x02
  16. #define PM8XXX_RTC_READ_OFFSET 0x06
  17. #define PM8XXX_ALARM_RW_OFFSET 0x0A
  18. /* RTC_CTRL register bit fields */
  19. #define PM8xxx_RTC_ENABLE BIT(7)
  20. #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
  21. #define NUM_8_BIT_RTC_REGS 0x4
  22. /**
  23. * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
  24. * @ctrl: base address of control register
  25. * @write: base address of write register
  26. * @read: base address of read register
  27. * @alarm_ctrl: base address of alarm control register
  28. * @alarm_ctrl2: base address of alarm control2 register
  29. * @alarm_rw: base address of alarm read-write register
  30. * @alarm_en: alarm enable mask
  31. */
  32. struct pm8xxx_rtc_regs {
  33. unsigned int ctrl;
  34. unsigned int write;
  35. unsigned int read;
  36. unsigned int alarm_ctrl;
  37. unsigned int alarm_ctrl2;
  38. unsigned int alarm_rw;
  39. unsigned int alarm_en;
  40. };
  41. /**
  42. * struct pm8xxx_rtc - rtc driver internal structure
  43. * @rtc: rtc device for this driver.
  44. * @regmap: regmap used to access RTC registers
  45. * @allow_set_time: indicates whether writing to the RTC is allowed
  46. * @rtc_alarm_irq: rtc alarm irq number.
  47. * @regs: rtc registers description.
  48. * @rtc_dev: device structure.
  49. * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
  50. */
  51. struct pm8xxx_rtc {
  52. struct rtc_device *rtc;
  53. struct regmap *regmap;
  54. bool allow_set_time;
  55. int rtc_alarm_irq;
  56. const struct pm8xxx_rtc_regs *regs;
  57. struct device *rtc_dev;
  58. spinlock_t ctrl_reg_lock;
  59. };
  60. /*
  61. * Steps to write the RTC registers.
  62. * 1. Disable alarm if enabled.
  63. * 2. Disable rtc if enabled.
  64. * 3. Write 0x00 to LSB.
  65. * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
  66. * 5. Enable rtc if disabled in step 2.
  67. * 6. Enable alarm if disabled in step 1.
  68. */
  69. static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
  70. {
  71. int rc, i;
  72. unsigned long secs, irq_flags;
  73. u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
  74. unsigned int ctrl_reg, rtc_ctrl_reg;
  75. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  76. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  77. if (!rtc_dd->allow_set_time)
  78. return -EACCES;
  79. secs = rtc_tm_to_time64(tm);
  80. dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
  81. for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
  82. value[i] = secs & 0xFF;
  83. secs >>= 8;
  84. }
  85. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  86. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  87. if (rc)
  88. goto rtc_rw_fail;
  89. if (ctrl_reg & regs->alarm_en) {
  90. alarm_enabled = 1;
  91. ctrl_reg &= ~regs->alarm_en;
  92. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  93. if (rc) {
  94. dev_err(dev, "Write to RTC Alarm control register failed\n");
  95. goto rtc_rw_fail;
  96. }
  97. }
  98. /* Disable RTC H/w before writing on RTC register */
  99. rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
  100. if (rc)
  101. goto rtc_rw_fail;
  102. if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
  103. rtc_disabled = 1;
  104. rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
  105. rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
  106. if (rc) {
  107. dev_err(dev, "Write to RTC control register failed\n");
  108. goto rtc_rw_fail;
  109. }
  110. }
  111. /* Write 0 to Byte[0] */
  112. rc = regmap_write(rtc_dd->regmap, regs->write, 0);
  113. if (rc) {
  114. dev_err(dev, "Write to RTC write data register failed\n");
  115. goto rtc_rw_fail;
  116. }
  117. /* Write Byte[1], Byte[2], Byte[3] */
  118. rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
  119. &value[1], sizeof(value) - 1);
  120. if (rc) {
  121. dev_err(dev, "Write to RTC write data register failed\n");
  122. goto rtc_rw_fail;
  123. }
  124. /* Write Byte[0] */
  125. rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
  126. if (rc) {
  127. dev_err(dev, "Write to RTC write data register failed\n");
  128. goto rtc_rw_fail;
  129. }
  130. /* Enable RTC H/w after writing on RTC register */
  131. if (rtc_disabled) {
  132. rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
  133. rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
  134. if (rc) {
  135. dev_err(dev, "Write to RTC control register failed\n");
  136. goto rtc_rw_fail;
  137. }
  138. }
  139. if (alarm_enabled) {
  140. ctrl_reg |= regs->alarm_en;
  141. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  142. if (rc) {
  143. dev_err(dev, "Write to RTC Alarm control register failed\n");
  144. goto rtc_rw_fail;
  145. }
  146. }
  147. rtc_rw_fail:
  148. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  149. return rc;
  150. }
  151. static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
  152. {
  153. int rc;
  154. u8 value[NUM_8_BIT_RTC_REGS];
  155. unsigned long secs;
  156. unsigned int reg;
  157. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  158. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  159. rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
  160. if (rc) {
  161. dev_err(dev, "RTC read data register failed\n");
  162. return rc;
  163. }
  164. /*
  165. * Read the LSB again and check if there has been a carry over.
  166. * If there is, redo the read operation.
  167. */
  168. rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
  169. if (rc < 0) {
  170. dev_err(dev, "RTC read data register failed\n");
  171. return rc;
  172. }
  173. if (unlikely(reg < value[0])) {
  174. rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
  175. value, sizeof(value));
  176. if (rc) {
  177. dev_err(dev, "RTC read data register failed\n");
  178. return rc;
  179. }
  180. }
  181. secs = value[0] | (value[1] << 8) | (value[2] << 16) |
  182. ((unsigned long)value[3] << 24);
  183. rtc_time64_to_tm(secs, tm);
  184. dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
  185. return 0;
  186. }
  187. static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  188. {
  189. int rc, i;
  190. u8 value[NUM_8_BIT_RTC_REGS];
  191. unsigned int ctrl_reg;
  192. unsigned long secs, irq_flags;
  193. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  194. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  195. secs = rtc_tm_to_time64(&alarm->time);
  196. for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
  197. value[i] = secs & 0xFF;
  198. secs >>= 8;
  199. }
  200. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  201. rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
  202. sizeof(value));
  203. if (rc) {
  204. dev_err(dev, "Write to RTC ALARM register failed\n");
  205. goto rtc_rw_fail;
  206. }
  207. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  208. if (rc)
  209. goto rtc_rw_fail;
  210. if (alarm->enabled)
  211. ctrl_reg |= regs->alarm_en;
  212. else
  213. ctrl_reg &= ~regs->alarm_en;
  214. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  215. if (rc) {
  216. dev_err(dev, "Write to RTC alarm control register failed\n");
  217. goto rtc_rw_fail;
  218. }
  219. dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
  220. &alarm->time, &alarm->time);
  221. rtc_rw_fail:
  222. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  223. return rc;
  224. }
  225. static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  226. {
  227. int rc;
  228. u8 value[NUM_8_BIT_RTC_REGS];
  229. unsigned long secs;
  230. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  231. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  232. rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
  233. sizeof(value));
  234. if (rc) {
  235. dev_err(dev, "RTC alarm time read failed\n");
  236. return rc;
  237. }
  238. secs = value[0] | (value[1] << 8) | (value[2] << 16) |
  239. ((unsigned long)value[3] << 24);
  240. rtc_time64_to_tm(secs, &alarm->time);
  241. dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
  242. &alarm->time, &alarm->time);
  243. return 0;
  244. }
  245. static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
  246. {
  247. int rc;
  248. unsigned long irq_flags;
  249. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  250. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  251. unsigned int ctrl_reg;
  252. u8 value[NUM_8_BIT_RTC_REGS] = {0};
  253. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  254. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  255. if (rc)
  256. goto rtc_rw_fail;
  257. if (enable)
  258. ctrl_reg |= regs->alarm_en;
  259. else
  260. ctrl_reg &= ~regs->alarm_en;
  261. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  262. if (rc) {
  263. dev_err(dev, "Write to RTC control register failed\n");
  264. goto rtc_rw_fail;
  265. }
  266. /* Clear Alarm register */
  267. if (!enable) {
  268. rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
  269. sizeof(value));
  270. if (rc) {
  271. dev_err(dev, "Clear RTC ALARM register failed\n");
  272. goto rtc_rw_fail;
  273. }
  274. }
  275. rtc_rw_fail:
  276. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  277. return rc;
  278. }
  279. static const struct rtc_class_ops pm8xxx_rtc_ops = {
  280. .read_time = pm8xxx_rtc_read_time,
  281. .set_time = pm8xxx_rtc_set_time,
  282. .set_alarm = pm8xxx_rtc_set_alarm,
  283. .read_alarm = pm8xxx_rtc_read_alarm,
  284. .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
  285. };
  286. static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
  287. {
  288. struct pm8xxx_rtc *rtc_dd = dev_id;
  289. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  290. unsigned int ctrl_reg;
  291. int rc;
  292. unsigned long irq_flags;
  293. rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
  294. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  295. /* Clear the alarm enable bit */
  296. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  297. if (rc) {
  298. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  299. goto rtc_alarm_handled;
  300. }
  301. ctrl_reg &= ~regs->alarm_en;
  302. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  303. if (rc) {
  304. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  305. dev_err(rtc_dd->rtc_dev,
  306. "Write to alarm control register failed\n");
  307. goto rtc_alarm_handled;
  308. }
  309. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  310. /* Clear RTC alarm register */
  311. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
  312. if (rc) {
  313. dev_err(rtc_dd->rtc_dev,
  314. "RTC Alarm control2 register read failed\n");
  315. goto rtc_alarm_handled;
  316. }
  317. ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
  318. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
  319. if (rc)
  320. dev_err(rtc_dd->rtc_dev,
  321. "Write to RTC Alarm control2 register failed\n");
  322. rtc_alarm_handled:
  323. return IRQ_HANDLED;
  324. }
  325. static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
  326. {
  327. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  328. unsigned int ctrl_reg;
  329. int rc;
  330. /* Check if the RTC is on, else turn it on */
  331. rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
  332. if (rc)
  333. return rc;
  334. if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
  335. ctrl_reg |= PM8xxx_RTC_ENABLE;
  336. rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
  337. if (rc)
  338. return rc;
  339. }
  340. return 0;
  341. }
  342. static const struct pm8xxx_rtc_regs pm8921_regs = {
  343. .ctrl = 0x11d,
  344. .write = 0x11f,
  345. .read = 0x123,
  346. .alarm_rw = 0x127,
  347. .alarm_ctrl = 0x11d,
  348. .alarm_ctrl2 = 0x11e,
  349. .alarm_en = BIT(1),
  350. };
  351. static const struct pm8xxx_rtc_regs pm8058_regs = {
  352. .ctrl = 0x1e8,
  353. .write = 0x1ea,
  354. .read = 0x1ee,
  355. .alarm_rw = 0x1f2,
  356. .alarm_ctrl = 0x1e8,
  357. .alarm_ctrl2 = 0x1e9,
  358. .alarm_en = BIT(1),
  359. };
  360. static const struct pm8xxx_rtc_regs pm8941_regs = {
  361. .ctrl = 0x6046,
  362. .write = 0x6040,
  363. .read = 0x6048,
  364. .alarm_rw = 0x6140,
  365. .alarm_ctrl = 0x6146,
  366. .alarm_ctrl2 = 0x6148,
  367. .alarm_en = BIT(7),
  368. };
  369. /*
  370. * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
  371. */
  372. static const struct of_device_id pm8xxx_id_table[] = {
  373. { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
  374. { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
  375. { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
  376. { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
  377. { },
  378. };
  379. MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
  380. static int pm8xxx_rtc_probe(struct platform_device *pdev)
  381. {
  382. int rc;
  383. struct pm8xxx_rtc *rtc_dd;
  384. const struct of_device_id *match;
  385. match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
  386. if (!match)
  387. return -ENXIO;
  388. rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
  389. if (rtc_dd == NULL)
  390. return -ENOMEM;
  391. /* Initialise spinlock to protect RTC control register */
  392. spin_lock_init(&rtc_dd->ctrl_reg_lock);
  393. rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  394. if (!rtc_dd->regmap) {
  395. dev_err(&pdev->dev, "Parent regmap unavailable.\n");
  396. return -ENXIO;
  397. }
  398. rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
  399. if (rtc_dd->rtc_alarm_irq < 0)
  400. return -ENXIO;
  401. rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
  402. "allow-set-time");
  403. rtc_dd->regs = match->data;
  404. rtc_dd->rtc_dev = &pdev->dev;
  405. rc = pm8xxx_rtc_enable(rtc_dd);
  406. if (rc)
  407. return rc;
  408. platform_set_drvdata(pdev, rtc_dd);
  409. device_init_wakeup(&pdev->dev, 1);
  410. /* Register the RTC device */
  411. rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
  412. if (IS_ERR(rtc_dd->rtc))
  413. return PTR_ERR(rtc_dd->rtc);
  414. rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
  415. rtc_dd->rtc->range_max = U32_MAX;
  416. /* Request the alarm IRQ */
  417. rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
  418. pm8xxx_alarm_trigger,
  419. IRQF_TRIGGER_RISING,
  420. "pm8xxx_rtc_alarm", rtc_dd);
  421. if (rc < 0) {
  422. dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
  423. return rc;
  424. }
  425. return rtc_register_device(rtc_dd->rtc);
  426. }
  427. #ifdef CONFIG_PM_SLEEP
  428. static int pm8xxx_rtc_resume(struct device *dev)
  429. {
  430. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  431. if (device_may_wakeup(dev))
  432. disable_irq_wake(rtc_dd->rtc_alarm_irq);
  433. return 0;
  434. }
  435. static int pm8xxx_rtc_suspend(struct device *dev)
  436. {
  437. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  438. if (device_may_wakeup(dev))
  439. enable_irq_wake(rtc_dd->rtc_alarm_irq);
  440. return 0;
  441. }
  442. #endif
  443. static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
  444. pm8xxx_rtc_suspend,
  445. pm8xxx_rtc_resume);
  446. static struct platform_driver pm8xxx_rtc_driver = {
  447. .probe = pm8xxx_rtc_probe,
  448. .driver = {
  449. .name = "rtc-pm8xxx",
  450. .pm = &pm8xxx_rtc_pm_ops,
  451. .of_match_table = pm8xxx_id_table,
  452. },
  453. };
  454. module_platform_driver(pm8xxx_rtc_driver);
  455. MODULE_ALIAS("platform:rtc-pm8xxx");
  456. MODULE_DESCRIPTION("PMIC8xxx RTC driver");
  457. MODULE_LICENSE("GPL v2");
  458. MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");