rtc-pcf2127.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * An I2C and SPI driver for the NXP PCF2127/29 RTC
  4. * Copyright 2013 Til-Technologies
  5. *
  6. * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
  7. *
  8. * Watchdog and tamper functions
  9. * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
  10. *
  11. * based on the other drivers in this same directory.
  12. *
  13. * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf
  14. */
  15. #include <linux/i2c.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/bcd.h>
  18. #include <linux/rtc.h>
  19. #include <linux/slab.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/regmap.h>
  24. #include <linux/watchdog.h>
  25. /* Control register 1 */
  26. #define PCF2127_REG_CTRL1 0x00
  27. #define PCF2127_BIT_CTRL1_TSF1 BIT(4)
  28. /* Control register 2 */
  29. #define PCF2127_REG_CTRL2 0x01
  30. #define PCF2127_BIT_CTRL2_AIE BIT(1)
  31. #define PCF2127_BIT_CTRL2_TSIE BIT(2)
  32. #define PCF2127_BIT_CTRL2_AF BIT(4)
  33. #define PCF2127_BIT_CTRL2_TSF2 BIT(5)
  34. #define PCF2127_BIT_CTRL2_WDTF BIT(6)
  35. /* Control register 3 */
  36. #define PCF2127_REG_CTRL3 0x02
  37. #define PCF2127_BIT_CTRL3_BLIE BIT(0)
  38. #define PCF2127_BIT_CTRL3_BIE BIT(1)
  39. #define PCF2127_BIT_CTRL3_BLF BIT(2)
  40. #define PCF2127_BIT_CTRL3_BF BIT(3)
  41. #define PCF2127_BIT_CTRL3_BTSE BIT(4)
  42. /* Time and date registers */
  43. #define PCF2127_REG_SC 0x03
  44. #define PCF2127_BIT_SC_OSF BIT(7)
  45. #define PCF2127_REG_MN 0x04
  46. #define PCF2127_REG_HR 0x05
  47. #define PCF2127_REG_DM 0x06
  48. #define PCF2127_REG_DW 0x07
  49. #define PCF2127_REG_MO 0x08
  50. #define PCF2127_REG_YR 0x09
  51. /* Alarm registers */
  52. #define PCF2127_REG_ALARM_SC 0x0A
  53. #define PCF2127_REG_ALARM_MN 0x0B
  54. #define PCF2127_REG_ALARM_HR 0x0C
  55. #define PCF2127_REG_ALARM_DM 0x0D
  56. #define PCF2127_REG_ALARM_DW 0x0E
  57. #define PCF2127_BIT_ALARM_AE BIT(7)
  58. /* Watchdog registers */
  59. #define PCF2127_REG_WD_CTL 0x10
  60. #define PCF2127_BIT_WD_CTL_TF0 BIT(0)
  61. #define PCF2127_BIT_WD_CTL_TF1 BIT(1)
  62. #define PCF2127_BIT_WD_CTL_CD0 BIT(6)
  63. #define PCF2127_BIT_WD_CTL_CD1 BIT(7)
  64. #define PCF2127_REG_WD_VAL 0x11
  65. /* Tamper timestamp registers */
  66. #define PCF2127_REG_TS_CTRL 0x12
  67. #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
  68. #define PCF2127_BIT_TS_CTRL_TSM BIT(7)
  69. #define PCF2127_REG_TS_SC 0x13
  70. #define PCF2127_REG_TS_MN 0x14
  71. #define PCF2127_REG_TS_HR 0x15
  72. #define PCF2127_REG_TS_DM 0x16
  73. #define PCF2127_REG_TS_MO 0x17
  74. #define PCF2127_REG_TS_YR 0x18
  75. /*
  76. * RAM registers
  77. * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
  78. * battery backed and can survive a power outage.
  79. * PCF2129 doesn't have this feature.
  80. */
  81. #define PCF2127_REG_RAM_ADDR_MSB 0x1A
  82. #define PCF2127_REG_RAM_WRT_CMD 0x1C
  83. #define PCF2127_REG_RAM_RD_CMD 0x1D
  84. /* Watchdog timer value constants */
  85. #define PCF2127_WD_VAL_STOP 0
  86. #define PCF2127_WD_VAL_MIN 2
  87. #define PCF2127_WD_VAL_MAX 255
  88. #define PCF2127_WD_VAL_DEFAULT 60
  89. struct pcf2127 {
  90. struct rtc_device *rtc;
  91. struct watchdog_device wdd;
  92. struct regmap *regmap;
  93. };
  94. /*
  95. * In the routines that deal directly with the pcf2127 hardware, we use
  96. * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
  97. */
  98. static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
  99. {
  100. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  101. unsigned char buf[10];
  102. int ret;
  103. /*
  104. * Avoid reading CTRL2 register as it causes WD_VAL register
  105. * value to reset to 0 which means watchdog is stopped.
  106. */
  107. ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3,
  108. (buf + PCF2127_REG_CTRL3),
  109. ARRAY_SIZE(buf) - PCF2127_REG_CTRL3);
  110. if (ret) {
  111. dev_err(dev, "%s: read error\n", __func__);
  112. return ret;
  113. }
  114. if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF)
  115. dev_info(dev,
  116. "low voltage detected, check/replace RTC battery.\n");
  117. /* Clock integrity is not guaranteed when OSF flag is set. */
  118. if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) {
  119. /*
  120. * no need clear the flag here,
  121. * it will be cleared once the new date is saved
  122. */
  123. dev_warn(dev,
  124. "oscillator stop detected, date/time is not reliable\n");
  125. return -EINVAL;
  126. }
  127. dev_dbg(dev,
  128. "%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, "
  129. "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
  130. __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC],
  131. buf[PCF2127_REG_MN], buf[PCF2127_REG_HR],
  132. buf[PCF2127_REG_DM], buf[PCF2127_REG_DW],
  133. buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]);
  134. tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
  135. tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
  136. tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */
  137. tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
  138. tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
  139. tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
  140. tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]);
  141. tm->tm_year += 100;
  142. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  143. "mday=%d, mon=%d, year=%d, wday=%d\n",
  144. __func__,
  145. tm->tm_sec, tm->tm_min, tm->tm_hour,
  146. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  147. return 0;
  148. }
  149. static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
  150. {
  151. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  152. unsigned char buf[7];
  153. int i = 0, err;
  154. dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
  155. "mday=%d, mon=%d, year=%d, wday=%d\n",
  156. __func__,
  157. tm->tm_sec, tm->tm_min, tm->tm_hour,
  158. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  159. /* hours, minutes and seconds */
  160. buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
  161. buf[i++] = bin2bcd(tm->tm_min);
  162. buf[i++] = bin2bcd(tm->tm_hour);
  163. buf[i++] = bin2bcd(tm->tm_mday);
  164. buf[i++] = tm->tm_wday & 0x07;
  165. /* month, 1 - 12 */
  166. buf[i++] = bin2bcd(tm->tm_mon + 1);
  167. /* year */
  168. buf[i++] = bin2bcd(tm->tm_year - 100);
  169. /* write register's data */
  170. err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i);
  171. if (err) {
  172. dev_err(dev,
  173. "%s: err=%d", __func__, err);
  174. return err;
  175. }
  176. return 0;
  177. }
  178. static int pcf2127_rtc_ioctl(struct device *dev,
  179. unsigned int cmd, unsigned long arg)
  180. {
  181. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  182. int val, touser = 0;
  183. int ret;
  184. switch (cmd) {
  185. case RTC_VL_READ:
  186. ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
  187. if (ret)
  188. return ret;
  189. if (val & PCF2127_BIT_CTRL3_BLF)
  190. touser |= RTC_VL_BACKUP_LOW;
  191. if (val & PCF2127_BIT_CTRL3_BF)
  192. touser |= RTC_VL_BACKUP_SWITCH;
  193. return put_user(touser, (unsigned int __user *)arg);
  194. case RTC_VL_CLR:
  195. return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
  196. PCF2127_BIT_CTRL3_BF, 0);
  197. default:
  198. return -ENOIOCTLCMD;
  199. }
  200. }
  201. static const struct rtc_class_ops pcf2127_rtc_ops = {
  202. .ioctl = pcf2127_rtc_ioctl,
  203. .read_time = pcf2127_rtc_read_time,
  204. .set_time = pcf2127_rtc_set_time,
  205. };
  206. static int pcf2127_nvmem_read(void *priv, unsigned int offset,
  207. void *val, size_t bytes)
  208. {
  209. struct pcf2127 *pcf2127 = priv;
  210. int ret;
  211. unsigned char offsetbuf[] = { offset >> 8, offset };
  212. ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
  213. offsetbuf, 2);
  214. if (ret)
  215. return ret;
  216. return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
  217. val, bytes);
  218. }
  219. static int pcf2127_nvmem_write(void *priv, unsigned int offset,
  220. void *val, size_t bytes)
  221. {
  222. struct pcf2127 *pcf2127 = priv;
  223. int ret;
  224. unsigned char offsetbuf[] = { offset >> 8, offset };
  225. ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
  226. offsetbuf, 2);
  227. if (ret)
  228. return ret;
  229. return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
  230. val, bytes);
  231. }
  232. /* watchdog driver */
  233. static int pcf2127_wdt_ping(struct watchdog_device *wdd)
  234. {
  235. struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
  236. return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
  237. }
  238. /*
  239. * Restart watchdog timer if feature is active.
  240. *
  241. * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
  242. * since register also contain control/status flags for other features.
  243. * Always call this function after reading CTRL2 register.
  244. */
  245. static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
  246. {
  247. int ret = 0;
  248. if (watchdog_active(wdd)) {
  249. ret = pcf2127_wdt_ping(wdd);
  250. if (ret)
  251. dev_err(wdd->parent,
  252. "%s: watchdog restart failed, ret=%d\n",
  253. __func__, ret);
  254. }
  255. return ret;
  256. }
  257. static int pcf2127_wdt_start(struct watchdog_device *wdd)
  258. {
  259. return pcf2127_wdt_ping(wdd);
  260. }
  261. static int pcf2127_wdt_stop(struct watchdog_device *wdd)
  262. {
  263. struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
  264. return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
  265. PCF2127_WD_VAL_STOP);
  266. }
  267. static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
  268. unsigned int new_timeout)
  269. {
  270. dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
  271. new_timeout, wdd->timeout);
  272. wdd->timeout = new_timeout;
  273. return pcf2127_wdt_active_ping(wdd);
  274. }
  275. static const struct watchdog_info pcf2127_wdt_info = {
  276. .identity = "NXP PCF2127/PCF2129 Watchdog",
  277. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
  278. };
  279. static const struct watchdog_ops pcf2127_watchdog_ops = {
  280. .owner = THIS_MODULE,
  281. .start = pcf2127_wdt_start,
  282. .stop = pcf2127_wdt_stop,
  283. .ping = pcf2127_wdt_ping,
  284. .set_timeout = pcf2127_wdt_set_timeout,
  285. };
  286. static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
  287. {
  288. u32 wdd_timeout;
  289. int ret;
  290. if (!IS_ENABLED(CONFIG_WATCHDOG) ||
  291. !device_property_read_bool(dev, "reset-source"))
  292. return 0;
  293. pcf2127->wdd.parent = dev;
  294. pcf2127->wdd.info = &pcf2127_wdt_info;
  295. pcf2127->wdd.ops = &pcf2127_watchdog_ops;
  296. pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN;
  297. pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
  298. pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
  299. pcf2127->wdd.min_hw_heartbeat_ms = 500;
  300. pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
  301. watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
  302. /* Test if watchdog timer is started by bootloader */
  303. ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
  304. if (ret)
  305. return ret;
  306. if (wdd_timeout)
  307. set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
  308. return devm_watchdog_register_device(dev, &pcf2127->wdd);
  309. }
  310. /* Alarm */
  311. static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  312. {
  313. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  314. unsigned int buf[5], ctrl2;
  315. int ret;
  316. ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
  317. if (ret)
  318. return ret;
  319. ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
  320. if (ret)
  321. return ret;
  322. ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
  323. sizeof(buf));
  324. if (ret)
  325. return ret;
  326. alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
  327. alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
  328. alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
  329. alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
  330. alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
  331. alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
  332. return 0;
  333. }
  334. static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
  335. {
  336. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  337. int ret;
  338. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
  339. PCF2127_BIT_CTRL2_AIE,
  340. enable ? PCF2127_BIT_CTRL2_AIE : 0);
  341. if (ret)
  342. return ret;
  343. return pcf2127_wdt_active_ping(&pcf2127->wdd);
  344. }
  345. static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  346. {
  347. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  348. uint8_t buf[5];
  349. int ret;
  350. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
  351. PCF2127_BIT_CTRL2_AF, 0);
  352. if (ret)
  353. return ret;
  354. ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
  355. if (ret)
  356. return ret;
  357. buf[0] = bin2bcd(alrm->time.tm_sec);
  358. buf[1] = bin2bcd(alrm->time.tm_min);
  359. buf[2] = bin2bcd(alrm->time.tm_hour);
  360. buf[3] = bin2bcd(alrm->time.tm_mday);
  361. buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
  362. ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
  363. sizeof(buf));
  364. if (ret)
  365. return ret;
  366. return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
  367. }
  368. static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
  369. {
  370. struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
  371. unsigned int ctrl2 = 0;
  372. int ret = 0;
  373. ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
  374. if (ret)
  375. return IRQ_NONE;
  376. if (!(ctrl2 & PCF2127_BIT_CTRL2_AF))
  377. return IRQ_NONE;
  378. regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
  379. ctrl2 & ~(PCF2127_BIT_CTRL2_AF | PCF2127_BIT_CTRL2_WDTF));
  380. rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
  381. pcf2127_wdt_active_ping(&pcf2127->wdd);
  382. return IRQ_HANDLED;
  383. }
  384. static const struct rtc_class_ops pcf2127_rtc_alrm_ops = {
  385. .ioctl = pcf2127_rtc_ioctl,
  386. .read_time = pcf2127_rtc_read_time,
  387. .set_time = pcf2127_rtc_set_time,
  388. .read_alarm = pcf2127_rtc_read_alarm,
  389. .set_alarm = pcf2127_rtc_set_alarm,
  390. .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
  391. };
  392. /* sysfs interface */
  393. static ssize_t timestamp0_store(struct device *dev,
  394. struct device_attribute *attr,
  395. const char *buf, size_t count)
  396. {
  397. struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
  398. int ret;
  399. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
  400. PCF2127_BIT_CTRL1_TSF1, 0);
  401. if (ret) {
  402. dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
  403. return ret;
  404. }
  405. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
  406. PCF2127_BIT_CTRL2_TSF2, 0);
  407. if (ret) {
  408. dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
  409. return ret;
  410. }
  411. ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
  412. if (ret)
  413. return ret;
  414. return count;
  415. };
  416. static ssize_t timestamp0_show(struct device *dev,
  417. struct device_attribute *attr, char *buf)
  418. {
  419. struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
  420. struct rtc_time tm;
  421. int ret;
  422. unsigned char data[25];
  423. ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data,
  424. sizeof(data));
  425. if (ret) {
  426. dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
  427. return ret;
  428. }
  429. dev_dbg(dev,
  430. "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, "
  431. "ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
  432. __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2],
  433. data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC],
  434. data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR],
  435. data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO],
  436. data[PCF2127_REG_TS_YR]);
  437. ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
  438. if (ret)
  439. return ret;
  440. if (!(data[PCF2127_REG_CTRL1] & PCF2127_BIT_CTRL1_TSF1) &&
  441. !(data[PCF2127_REG_CTRL2] & PCF2127_BIT_CTRL2_TSF2))
  442. return 0;
  443. tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F);
  444. tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F);
  445. tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F);
  446. tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F);
  447. /* TS_MO register (month) value range: 1-12 */
  448. tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1;
  449. tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]);
  450. if (tm.tm_year < 70)
  451. tm.tm_year += 100; /* assume we are in 1970...2069 */
  452. ret = rtc_valid_tm(&tm);
  453. if (ret)
  454. return ret;
  455. return sprintf(buf, "%llu\n",
  456. (unsigned long long)rtc_tm_to_time64(&tm));
  457. };
  458. static DEVICE_ATTR_RW(timestamp0);
  459. static struct attribute *pcf2127_attrs[] = {
  460. &dev_attr_timestamp0.attr,
  461. NULL
  462. };
  463. static const struct attribute_group pcf2127_attr_group = {
  464. .attrs = pcf2127_attrs,
  465. };
  466. static int pcf2127_probe(struct device *dev, struct regmap *regmap,
  467. int alarm_irq, const char *name, bool has_nvmem)
  468. {
  469. struct pcf2127 *pcf2127;
  470. int ret = 0;
  471. dev_dbg(dev, "%s\n", __func__);
  472. pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
  473. if (!pcf2127)
  474. return -ENOMEM;
  475. pcf2127->regmap = regmap;
  476. dev_set_drvdata(dev, pcf2127);
  477. pcf2127->rtc = devm_rtc_allocate_device(dev);
  478. if (IS_ERR(pcf2127->rtc))
  479. return PTR_ERR(pcf2127->rtc);
  480. pcf2127->rtc->ops = &pcf2127_rtc_ops;
  481. pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  482. pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
  483. pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
  484. pcf2127->rtc->uie_unsupported = 1;
  485. if (alarm_irq > 0) {
  486. ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
  487. pcf2127_rtc_irq,
  488. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  489. dev_name(dev), dev);
  490. if (ret) {
  491. dev_err(dev, "failed to request alarm irq\n");
  492. return ret;
  493. }
  494. }
  495. if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
  496. device_init_wakeup(dev, true);
  497. pcf2127->rtc->ops = &pcf2127_rtc_alrm_ops;
  498. }
  499. if (has_nvmem) {
  500. struct nvmem_config nvmem_cfg = {
  501. .priv = pcf2127,
  502. .reg_read = pcf2127_nvmem_read,
  503. .reg_write = pcf2127_nvmem_write,
  504. .size = 512,
  505. };
  506. ret = rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
  507. }
  508. /*
  509. * Watchdog timer enabled and reset pin /RST activated when timed out.
  510. * Select 1Hz clock source for watchdog timer.
  511. * Note: Countdown timer disabled and not available.
  512. */
  513. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
  514. PCF2127_BIT_WD_CTL_CD1 |
  515. PCF2127_BIT_WD_CTL_CD0 |
  516. PCF2127_BIT_WD_CTL_TF1 |
  517. PCF2127_BIT_WD_CTL_TF0,
  518. PCF2127_BIT_WD_CTL_CD1 |
  519. PCF2127_BIT_WD_CTL_CD0 |
  520. PCF2127_BIT_WD_CTL_TF1);
  521. if (ret) {
  522. dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
  523. return ret;
  524. }
  525. pcf2127_watchdog_init(dev, pcf2127);
  526. /*
  527. * Disable battery low/switch-over timestamp and interrupts.
  528. * Clear battery interrupt flags which can block new trigger events.
  529. * Note: This is the default chip behaviour but added to ensure
  530. * correct tamper timestamp and interrupt function.
  531. */
  532. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
  533. PCF2127_BIT_CTRL3_BTSE |
  534. PCF2127_BIT_CTRL3_BIE |
  535. PCF2127_BIT_CTRL3_BLIE, 0);
  536. if (ret) {
  537. dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
  538. __func__);
  539. return ret;
  540. }
  541. /*
  542. * Enable timestamp function and store timestamp of first trigger
  543. * event until TSF1 and TFS2 interrupt flags are cleared.
  544. */
  545. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
  546. PCF2127_BIT_TS_CTRL_TSOFF |
  547. PCF2127_BIT_TS_CTRL_TSM,
  548. PCF2127_BIT_TS_CTRL_TSM);
  549. if (ret) {
  550. dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
  551. __func__);
  552. return ret;
  553. }
  554. /*
  555. * Enable interrupt generation when TSF1 or TSF2 timestamp flags
  556. * are set. Interrupt signal is an open-drain output and can be
  557. * left floating if unused.
  558. */
  559. ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
  560. PCF2127_BIT_CTRL2_TSIE,
  561. PCF2127_BIT_CTRL2_TSIE);
  562. if (ret) {
  563. dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
  564. __func__);
  565. return ret;
  566. }
  567. ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
  568. if (ret) {
  569. dev_err(dev, "%s: tamper sysfs registering failed\n",
  570. __func__);
  571. return ret;
  572. }
  573. return rtc_register_device(pcf2127->rtc);
  574. }
  575. #ifdef CONFIG_OF
  576. static const struct of_device_id pcf2127_of_match[] = {
  577. { .compatible = "nxp,pcf2127" },
  578. { .compatible = "nxp,pcf2129" },
  579. { .compatible = "nxp,pca2129" },
  580. {}
  581. };
  582. MODULE_DEVICE_TABLE(of, pcf2127_of_match);
  583. #endif
  584. #if IS_ENABLED(CONFIG_I2C)
  585. static int pcf2127_i2c_write(void *context, const void *data, size_t count)
  586. {
  587. struct device *dev = context;
  588. struct i2c_client *client = to_i2c_client(dev);
  589. int ret;
  590. ret = i2c_master_send(client, data, count);
  591. if (ret != count)
  592. return ret < 0 ? ret : -EIO;
  593. return 0;
  594. }
  595. static int pcf2127_i2c_gather_write(void *context,
  596. const void *reg, size_t reg_size,
  597. const void *val, size_t val_size)
  598. {
  599. struct device *dev = context;
  600. struct i2c_client *client = to_i2c_client(dev);
  601. int ret;
  602. void *buf;
  603. if (WARN_ON(reg_size != 1))
  604. return -EINVAL;
  605. buf = kmalloc(val_size + 1, GFP_KERNEL);
  606. if (!buf)
  607. return -ENOMEM;
  608. memcpy(buf, reg, 1);
  609. memcpy(buf + 1, val, val_size);
  610. ret = i2c_master_send(client, buf, val_size + 1);
  611. kfree(buf);
  612. if (ret != val_size + 1)
  613. return ret < 0 ? ret : -EIO;
  614. return 0;
  615. }
  616. static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
  617. void *val, size_t val_size)
  618. {
  619. struct device *dev = context;
  620. struct i2c_client *client = to_i2c_client(dev);
  621. int ret;
  622. if (WARN_ON(reg_size != 1))
  623. return -EINVAL;
  624. ret = i2c_master_send(client, reg, 1);
  625. if (ret != 1)
  626. return ret < 0 ? ret : -EIO;
  627. ret = i2c_master_recv(client, val, val_size);
  628. if (ret != val_size)
  629. return ret < 0 ? ret : -EIO;
  630. return 0;
  631. }
  632. /*
  633. * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
  634. * is that the STOP condition is required between set register address and
  635. * read register data when reading from registers.
  636. */
  637. static const struct regmap_bus pcf2127_i2c_regmap = {
  638. .write = pcf2127_i2c_write,
  639. .gather_write = pcf2127_i2c_gather_write,
  640. .read = pcf2127_i2c_read,
  641. };
  642. static struct i2c_driver pcf2127_i2c_driver;
  643. static int pcf2127_i2c_probe(struct i2c_client *client,
  644. const struct i2c_device_id *id)
  645. {
  646. struct regmap *regmap;
  647. static const struct regmap_config config = {
  648. .reg_bits = 8,
  649. .val_bits = 8,
  650. .max_register = 0x1d,
  651. };
  652. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  653. return -ENODEV;
  654. regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
  655. &client->dev, &config);
  656. if (IS_ERR(regmap)) {
  657. dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
  658. __func__, PTR_ERR(regmap));
  659. return PTR_ERR(regmap);
  660. }
  661. return pcf2127_probe(&client->dev, regmap, client->irq,
  662. pcf2127_i2c_driver.driver.name, id->driver_data);
  663. }
  664. static const struct i2c_device_id pcf2127_i2c_id[] = {
  665. { "pcf2127", 1 },
  666. { "pcf2129", 0 },
  667. { "pca2129", 0 },
  668. { }
  669. };
  670. MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
  671. static struct i2c_driver pcf2127_i2c_driver = {
  672. .driver = {
  673. .name = "rtc-pcf2127-i2c",
  674. .of_match_table = of_match_ptr(pcf2127_of_match),
  675. },
  676. .probe = pcf2127_i2c_probe,
  677. .id_table = pcf2127_i2c_id,
  678. };
  679. static int pcf2127_i2c_register_driver(void)
  680. {
  681. return i2c_add_driver(&pcf2127_i2c_driver);
  682. }
  683. static void pcf2127_i2c_unregister_driver(void)
  684. {
  685. i2c_del_driver(&pcf2127_i2c_driver);
  686. }
  687. #else
  688. static int pcf2127_i2c_register_driver(void)
  689. {
  690. return 0;
  691. }
  692. static void pcf2127_i2c_unregister_driver(void)
  693. {
  694. }
  695. #endif
  696. #if IS_ENABLED(CONFIG_SPI_MASTER)
  697. static struct spi_driver pcf2127_spi_driver;
  698. static int pcf2127_spi_probe(struct spi_device *spi)
  699. {
  700. static const struct regmap_config config = {
  701. .reg_bits = 8,
  702. .val_bits = 8,
  703. .read_flag_mask = 0xa0,
  704. .write_flag_mask = 0x20,
  705. .max_register = 0x1d,
  706. };
  707. struct regmap *regmap;
  708. regmap = devm_regmap_init_spi(spi, &config);
  709. if (IS_ERR(regmap)) {
  710. dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
  711. __func__, PTR_ERR(regmap));
  712. return PTR_ERR(regmap);
  713. }
  714. return pcf2127_probe(&spi->dev, regmap, spi->irq,
  715. pcf2127_spi_driver.driver.name,
  716. spi_get_device_id(spi)->driver_data);
  717. }
  718. static const struct spi_device_id pcf2127_spi_id[] = {
  719. { "pcf2127", 1 },
  720. { "pcf2129", 0 },
  721. { "pca2129", 0 },
  722. { }
  723. };
  724. MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
  725. static struct spi_driver pcf2127_spi_driver = {
  726. .driver = {
  727. .name = "rtc-pcf2127-spi",
  728. .of_match_table = of_match_ptr(pcf2127_of_match),
  729. },
  730. .probe = pcf2127_spi_probe,
  731. .id_table = pcf2127_spi_id,
  732. };
  733. static int pcf2127_spi_register_driver(void)
  734. {
  735. return spi_register_driver(&pcf2127_spi_driver);
  736. }
  737. static void pcf2127_spi_unregister_driver(void)
  738. {
  739. spi_unregister_driver(&pcf2127_spi_driver);
  740. }
  741. #else
  742. static int pcf2127_spi_register_driver(void)
  743. {
  744. return 0;
  745. }
  746. static void pcf2127_spi_unregister_driver(void)
  747. {
  748. }
  749. #endif
  750. static int __init pcf2127_init(void)
  751. {
  752. int ret;
  753. ret = pcf2127_i2c_register_driver();
  754. if (ret) {
  755. pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
  756. return ret;
  757. }
  758. ret = pcf2127_spi_register_driver();
  759. if (ret) {
  760. pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
  761. pcf2127_i2c_unregister_driver();
  762. }
  763. return ret;
  764. }
  765. module_init(pcf2127_init)
  766. static void __exit pcf2127_exit(void)
  767. {
  768. pcf2127_spi_unregister_driver();
  769. pcf2127_i2c_unregister_driver();
  770. }
  771. module_exit(pcf2127_exit)
  772. MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
  773. MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
  774. MODULE_LICENSE("GPL v2");