rtc-pcf2123.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * An SPI driver for the Philips PCF2123 RTC
  4. * Copyright 2009 Cyber Switching, Inc.
  5. *
  6. * Author: Chris Verges <chrisv@cyberswitching.com>
  7. * Maintainers: http://www.cyberswitching.com
  8. *
  9. * based on the RS5C348 driver in this same directory.
  10. *
  11. * Thanks to Christian Pellegrin <chripell@fsfe.org> for
  12. * the sysfs contributions to this driver.
  13. *
  14. * Please note that the CS is active high, so platform data
  15. * should look something like:
  16. *
  17. * static struct spi_board_info ek_spi_devices[] = {
  18. * ...
  19. * {
  20. * .modalias = "rtc-pcf2123",
  21. * .chip_select = 1,
  22. * .controller_data = (void *)AT91_PIN_PA10,
  23. * .max_speed_hz = 1000 * 1000,
  24. * .mode = SPI_CS_HIGH,
  25. * .bus_num = 0,
  26. * },
  27. * ...
  28. *};
  29. */
  30. #include <linux/bcd.h>
  31. #include <linux/delay.h>
  32. #include <linux/device.h>
  33. #include <linux/errno.h>
  34. #include <linux/init.h>
  35. #include <linux/kernel.h>
  36. #include <linux/of.h>
  37. #include <linux/string.h>
  38. #include <linux/slab.h>
  39. #include <linux/rtc.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/module.h>
  42. #include <linux/regmap.h>
  43. /* REGISTERS */
  44. #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
  45. #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
  46. #define PCF2123_REG_SC (0x02) /* datetime */
  47. #define PCF2123_REG_MN (0x03)
  48. #define PCF2123_REG_HR (0x04)
  49. #define PCF2123_REG_DM (0x05)
  50. #define PCF2123_REG_DW (0x06)
  51. #define PCF2123_REG_MO (0x07)
  52. #define PCF2123_REG_YR (0x08)
  53. #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
  54. #define PCF2123_REG_ALRM_HR (0x0a)
  55. #define PCF2123_REG_ALRM_DM (0x0b)
  56. #define PCF2123_REG_ALRM_DW (0x0c)
  57. #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
  58. #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
  59. #define PCF2123_REG_CTDWN_TMR (0x0f)
  60. /* PCF2123_REG_CTRL1 BITS */
  61. #define CTRL1_CLEAR (0) /* Clear */
  62. #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
  63. #define CTRL1_12_HOUR BIT(2) /* 12 hour time */
  64. #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
  65. #define CTRL1_STOP BIT(5) /* Stop the clock */
  66. #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
  67. /* PCF2123_REG_CTRL2 BITS */
  68. #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
  69. #define CTRL2_AIE BIT(1) /* Alarm irq enable */
  70. #define CTRL2_TF BIT(2) /* Countdown timer flag */
  71. #define CTRL2_AF BIT(3) /* Alarm flag */
  72. #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
  73. #define CTRL2_MSF BIT(5) /* Minute or second irq flag */
  74. #define CTRL2_SI BIT(6) /* Second irq enable */
  75. #define CTRL2_MI BIT(7) /* Minute irq enable */
  76. /* PCF2123_REG_SC BITS */
  77. #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
  78. /* PCF2123_REG_ALRM_XX BITS */
  79. #define ALRM_DISABLE BIT(7) /* MN, HR, DM, or DW alarm matching */
  80. /* PCF2123_REG_TMR_CLKOUT BITS */
  81. #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
  82. #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
  83. #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
  84. #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
  85. #define CD_TMR_TE BIT(3) /* Countdown timer enable */
  86. /* PCF2123_REG_OFFSET BITS */
  87. #define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
  88. #define OFFSET_COARSE BIT(7) /* Coarse mode offset */
  89. #define OFFSET_STEP (2170) /* Offset step in parts per billion */
  90. #define OFFSET_MASK GENMASK(6, 0) /* Offset value */
  91. /* READ/WRITE ADDRESS BITS */
  92. #define PCF2123_WRITE BIT(4)
  93. #define PCF2123_READ (BIT(4) | BIT(7))
  94. static struct spi_driver pcf2123_driver;
  95. struct pcf2123_data {
  96. struct rtc_device *rtc;
  97. struct regmap *map;
  98. };
  99. static const struct regmap_config pcf2123_regmap_config = {
  100. .reg_bits = 8,
  101. .val_bits = 8,
  102. .read_flag_mask = PCF2123_READ,
  103. .write_flag_mask = PCF2123_WRITE,
  104. .max_register = PCF2123_REG_CTDWN_TMR,
  105. };
  106. static int pcf2123_read_offset(struct device *dev, long *offset)
  107. {
  108. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  109. int ret, val;
  110. unsigned int reg;
  111. ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, &reg);
  112. if (ret)
  113. return ret;
  114. val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
  115. if (reg & OFFSET_COARSE)
  116. val *= 2;
  117. *offset = ((long)val) * OFFSET_STEP;
  118. return 0;
  119. }
  120. /*
  121. * The offset register is a 7 bit signed value with a coarse bit in bit 7.
  122. * The main difference between the two is normal offset adjusts the first
  123. * second of n minutes every other hour, with 61, 62 and 63 being shoved
  124. * into the 60th minute.
  125. * The coarse adjustment does the same, but every hour.
  126. * the two overlap, with every even normal offset value corresponding
  127. * to a coarse offset. Based on this algorithm, it seems that despite the
  128. * name, coarse offset is a better fit for overlapping values.
  129. */
  130. static int pcf2123_set_offset(struct device *dev, long offset)
  131. {
  132. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  133. s8 reg;
  134. if (offset > OFFSET_STEP * 127)
  135. reg = 127;
  136. else if (offset < OFFSET_STEP * -128)
  137. reg = -128;
  138. else
  139. reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
  140. /* choose fine offset only for odd values in the normal range */
  141. if (reg & 1 && reg <= 63 && reg >= -64) {
  142. /* Normal offset. Clear the coarse bit */
  143. reg &= ~OFFSET_COARSE;
  144. } else {
  145. /* Coarse offset. Divide by 2 and set the coarse bit */
  146. reg >>= 1;
  147. reg |= OFFSET_COARSE;
  148. }
  149. return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg);
  150. }
  151. static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
  152. {
  153. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  154. u8 rxbuf[7];
  155. int ret;
  156. ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_SC, rxbuf,
  157. sizeof(rxbuf));
  158. if (ret)
  159. return ret;
  160. if (rxbuf[0] & OSC_HAS_STOPPED) {
  161. dev_info(dev, "clock was stopped. Time is not valid\n");
  162. return -EINVAL;
  163. }
  164. tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
  165. tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
  166. tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
  167. tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
  168. tm->tm_wday = rxbuf[4] & 0x07;
  169. tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
  170. tm->tm_year = bcd2bin(rxbuf[6]) + 100;
  171. dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
  172. return 0;
  173. }
  174. static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
  175. {
  176. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  177. u8 txbuf[7];
  178. int ret;
  179. dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
  180. /* Stop the counter first */
  181. ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
  182. if (ret)
  183. return ret;
  184. /* Set the new time */
  185. txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
  186. txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
  187. txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
  188. txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
  189. txbuf[4] = tm->tm_wday & 0x07;
  190. txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
  191. txbuf[6] = bin2bcd(tm->tm_year - 100);
  192. ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_SC, txbuf,
  193. sizeof(txbuf));
  194. if (ret)
  195. return ret;
  196. /* Start the counter */
  197. ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
  198. if (ret)
  199. return ret;
  200. return 0;
  201. }
  202. static int pcf2123_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
  203. {
  204. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  205. return regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE,
  206. en ? CTRL2_AIE : 0);
  207. }
  208. static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  209. {
  210. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  211. u8 rxbuf[4];
  212. int ret;
  213. unsigned int val = 0;
  214. ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_ALRM_MN, rxbuf,
  215. sizeof(rxbuf));
  216. if (ret)
  217. return ret;
  218. alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
  219. alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
  220. alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
  221. alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
  222. dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
  223. ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
  224. if (ret)
  225. return ret;
  226. alm->enabled = !!(val & CTRL2_AIE);
  227. return 0;
  228. }
  229. static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  230. {
  231. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  232. u8 txbuf[4];
  233. int ret;
  234. dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
  235. /* Disable alarm interrupt */
  236. ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
  237. if (ret)
  238. return ret;
  239. /* Ensure alarm flag is clear */
  240. ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
  241. if (ret)
  242. return ret;
  243. /* Set new alarm */
  244. txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
  245. txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
  246. txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
  247. txbuf[3] = ALRM_DISABLE;
  248. ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_ALRM_MN, txbuf,
  249. sizeof(txbuf));
  250. if (ret)
  251. return ret;
  252. return pcf2123_rtc_alarm_irq_enable(dev, alm->enabled);
  253. }
  254. static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
  255. {
  256. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  257. struct mutex *lock = &pcf2123->rtc->ops_lock;
  258. unsigned int val = 0;
  259. int ret = IRQ_NONE;
  260. mutex_lock(lock);
  261. regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
  262. /* Alarm? */
  263. if (val & CTRL2_AF) {
  264. ret = IRQ_HANDLED;
  265. /* Clear alarm flag */
  266. regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
  267. rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF);
  268. }
  269. mutex_unlock(lock);
  270. return ret;
  271. }
  272. static int pcf2123_reset(struct device *dev)
  273. {
  274. struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
  275. int ret;
  276. unsigned int val = 0;
  277. ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
  278. if (ret)
  279. return ret;
  280. /* Stop the counter */
  281. dev_dbg(dev, "stopping RTC\n");
  282. ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
  283. if (ret)
  284. return ret;
  285. /* See if the counter was actually stopped */
  286. dev_dbg(dev, "checking for presence of RTC\n");
  287. ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val);
  288. if (ret)
  289. return ret;
  290. dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
  291. if (!(val & CTRL1_STOP))
  292. return -ENODEV;
  293. /* Start the counter */
  294. ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
  295. if (ret)
  296. return ret;
  297. return 0;
  298. }
  299. static const struct rtc_class_ops pcf2123_rtc_ops = {
  300. .read_time = pcf2123_rtc_read_time,
  301. .set_time = pcf2123_rtc_set_time,
  302. .read_offset = pcf2123_read_offset,
  303. .set_offset = pcf2123_set_offset,
  304. .read_alarm = pcf2123_rtc_read_alarm,
  305. .set_alarm = pcf2123_rtc_set_alarm,
  306. .alarm_irq_enable = pcf2123_rtc_alarm_irq_enable,
  307. };
  308. static int pcf2123_probe(struct spi_device *spi)
  309. {
  310. struct rtc_device *rtc;
  311. struct rtc_time tm;
  312. struct pcf2123_data *pcf2123;
  313. int ret = 0;
  314. pcf2123 = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_data),
  315. GFP_KERNEL);
  316. if (!pcf2123)
  317. return -ENOMEM;
  318. dev_set_drvdata(&spi->dev, pcf2123);
  319. pcf2123->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
  320. if (IS_ERR(pcf2123->map)) {
  321. dev_err(&spi->dev, "regmap init failed.\n");
  322. return PTR_ERR(pcf2123->map);
  323. }
  324. ret = pcf2123_rtc_read_time(&spi->dev, &tm);
  325. if (ret < 0) {
  326. ret = pcf2123_reset(&spi->dev);
  327. if (ret < 0) {
  328. dev_err(&spi->dev, "chip not found\n");
  329. return ret;
  330. }
  331. }
  332. dev_info(&spi->dev, "spiclk %u KHz.\n",
  333. (spi->max_speed_hz + 500) / 1000);
  334. /* Finalize the initialization */
  335. rtc = devm_rtc_allocate_device(&spi->dev);
  336. if (IS_ERR(rtc))
  337. return PTR_ERR(rtc);
  338. pcf2123->rtc = rtc;
  339. /* Register alarm irq */
  340. if (spi->irq > 0) {
  341. ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
  342. pcf2123_rtc_irq,
  343. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  344. pcf2123_driver.driver.name, &spi->dev);
  345. if (!ret)
  346. device_init_wakeup(&spi->dev, true);
  347. else
  348. dev_err(&spi->dev, "could not request irq.\n");
  349. }
  350. /* The PCF2123's alarm only has minute accuracy. Must add timer
  351. * support to this driver to generate interrupts more than once
  352. * per minute.
  353. */
  354. rtc->uie_unsupported = 1;
  355. rtc->ops = &pcf2123_rtc_ops;
  356. rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  357. rtc->range_max = RTC_TIMESTAMP_END_2099;
  358. rtc->set_start_time = true;
  359. ret = rtc_register_device(rtc);
  360. if (ret)
  361. return ret;
  362. return 0;
  363. }
  364. #ifdef CONFIG_OF
  365. static const struct of_device_id pcf2123_dt_ids[] = {
  366. { .compatible = "nxp,pcf2123", },
  367. { .compatible = "microcrystal,rv2123", },
  368. /* Deprecated, do not use */
  369. { .compatible = "nxp,rtc-pcf2123", },
  370. { /* sentinel */ }
  371. };
  372. MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
  373. #endif
  374. static struct spi_driver pcf2123_driver = {
  375. .driver = {
  376. .name = "rtc-pcf2123",
  377. .of_match_table = of_match_ptr(pcf2123_dt_ids),
  378. },
  379. .probe = pcf2123_probe,
  380. };
  381. module_spi_driver(pcf2123_driver);
  382. MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
  383. MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
  384. MODULE_LICENSE("GPL");