rtc-omap.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI OMAP Real Time Clock interface for Linux
  4. *
  5. * Copyright (C) 2003 MontaVista Software, Inc.
  6. * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  7. *
  8. * Copyright (C) 2006 David Brownell (new RTC framework)
  9. * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
  10. */
  11. #include <linux/bcd.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/ioport.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/pinctrl/pinctrl.h>
  22. #include <linux/pinctrl/pinconf.h>
  23. #include <linux/pinctrl/pinconf-generic.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/rtc.h>
  27. /*
  28. * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
  29. * with century-range alarm matching, driven by the 32kHz clock.
  30. *
  31. * The main user-visible ways it differs from PC RTCs are by omitting
  32. * "don't care" alarm fields and sub-second periodic IRQs, and having
  33. * an autoadjust mechanism to calibrate to the true oscillator rate.
  34. *
  35. * Board-specific wiring options include using split power mode with
  36. * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  37. * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
  38. * low power modes) for OMAP1 boards (OMAP-L138 has this built into
  39. * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  40. */
  41. /* RTC registers */
  42. #define OMAP_RTC_SECONDS_REG 0x00
  43. #define OMAP_RTC_MINUTES_REG 0x04
  44. #define OMAP_RTC_HOURS_REG 0x08
  45. #define OMAP_RTC_DAYS_REG 0x0C
  46. #define OMAP_RTC_MONTHS_REG 0x10
  47. #define OMAP_RTC_YEARS_REG 0x14
  48. #define OMAP_RTC_WEEKS_REG 0x18
  49. #define OMAP_RTC_ALARM_SECONDS_REG 0x20
  50. #define OMAP_RTC_ALARM_MINUTES_REG 0x24
  51. #define OMAP_RTC_ALARM_HOURS_REG 0x28
  52. #define OMAP_RTC_ALARM_DAYS_REG 0x2c
  53. #define OMAP_RTC_ALARM_MONTHS_REG 0x30
  54. #define OMAP_RTC_ALARM_YEARS_REG 0x34
  55. #define OMAP_RTC_CTRL_REG 0x40
  56. #define OMAP_RTC_STATUS_REG 0x44
  57. #define OMAP_RTC_INTERRUPTS_REG 0x48
  58. #define OMAP_RTC_COMP_LSB_REG 0x4c
  59. #define OMAP_RTC_COMP_MSB_REG 0x50
  60. #define OMAP_RTC_OSC_REG 0x54
  61. #define OMAP_RTC_SCRATCH0_REG 0x60
  62. #define OMAP_RTC_SCRATCH1_REG 0x64
  63. #define OMAP_RTC_SCRATCH2_REG 0x68
  64. #define OMAP_RTC_KICK0_REG 0x6c
  65. #define OMAP_RTC_KICK1_REG 0x70
  66. #define OMAP_RTC_IRQWAKEEN 0x7c
  67. #define OMAP_RTC_ALARM2_SECONDS_REG 0x80
  68. #define OMAP_RTC_ALARM2_MINUTES_REG 0x84
  69. #define OMAP_RTC_ALARM2_HOURS_REG 0x88
  70. #define OMAP_RTC_ALARM2_DAYS_REG 0x8c
  71. #define OMAP_RTC_ALARM2_MONTHS_REG 0x90
  72. #define OMAP_RTC_ALARM2_YEARS_REG 0x94
  73. #define OMAP_RTC_PMIC_REG 0x98
  74. /* OMAP_RTC_CTRL_REG bit fields: */
  75. #define OMAP_RTC_CTRL_SPLIT BIT(7)
  76. #define OMAP_RTC_CTRL_DISABLE BIT(6)
  77. #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
  78. #define OMAP_RTC_CTRL_TEST BIT(4)
  79. #define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
  80. #define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
  81. #define OMAP_RTC_CTRL_ROUND_30S BIT(1)
  82. #define OMAP_RTC_CTRL_STOP BIT(0)
  83. /* OMAP_RTC_STATUS_REG bit fields: */
  84. #define OMAP_RTC_STATUS_POWER_UP BIT(7)
  85. #define OMAP_RTC_STATUS_ALARM2 BIT(7)
  86. #define OMAP_RTC_STATUS_ALARM BIT(6)
  87. #define OMAP_RTC_STATUS_1D_EVENT BIT(5)
  88. #define OMAP_RTC_STATUS_1H_EVENT BIT(4)
  89. #define OMAP_RTC_STATUS_1M_EVENT BIT(3)
  90. #define OMAP_RTC_STATUS_1S_EVENT BIT(2)
  91. #define OMAP_RTC_STATUS_RUN BIT(1)
  92. #define OMAP_RTC_STATUS_BUSY BIT(0)
  93. /* OMAP_RTC_INTERRUPTS_REG bit fields: */
  94. #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
  95. #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
  96. #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
  97. /* OMAP_RTC_OSC_REG bit fields: */
  98. #define OMAP_RTC_OSC_32KCLK_EN BIT(6)
  99. #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
  100. #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
  101. /* OMAP_RTC_IRQWAKEEN bit fields: */
  102. #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
  103. /* OMAP_RTC_PMIC bit fields: */
  104. #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
  105. #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
  106. #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
  107. /* OMAP_RTC_KICKER values */
  108. #define KICK0_VALUE 0x83e70b13
  109. #define KICK1_VALUE 0x95a4f1e0
  110. struct omap_rtc;
  111. struct omap_rtc_device_type {
  112. bool has_32kclk_en;
  113. bool has_irqwakeen;
  114. bool has_pmic_mode;
  115. bool has_power_up_reset;
  116. void (*lock)(struct omap_rtc *rtc);
  117. void (*unlock)(struct omap_rtc *rtc);
  118. };
  119. struct omap_rtc {
  120. struct rtc_device *rtc;
  121. void __iomem *base;
  122. struct clk *clk;
  123. int irq_alarm;
  124. int irq_timer;
  125. u8 interrupts_reg;
  126. bool is_pmic_controller;
  127. bool has_ext_clk;
  128. bool is_suspending;
  129. const struct omap_rtc_device_type *type;
  130. struct pinctrl_dev *pctldev;
  131. };
  132. static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
  133. {
  134. return readb(rtc->base + reg);
  135. }
  136. static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
  137. {
  138. return readl(rtc->base + reg);
  139. }
  140. static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
  141. {
  142. writeb(val, rtc->base + reg);
  143. }
  144. static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
  145. {
  146. writel(val, rtc->base + reg);
  147. }
  148. static void am3352_rtc_unlock(struct omap_rtc *rtc)
  149. {
  150. rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
  151. rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
  152. }
  153. static void am3352_rtc_lock(struct omap_rtc *rtc)
  154. {
  155. rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
  156. rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
  157. }
  158. static void default_rtc_unlock(struct omap_rtc *rtc)
  159. {
  160. }
  161. static void default_rtc_lock(struct omap_rtc *rtc)
  162. {
  163. }
  164. /*
  165. * We rely on the rtc framework to handle locking (rtc->ops_lock),
  166. * so the only other requirement is that register accesses which
  167. * require BUSY to be clear are made with IRQs locally disabled
  168. */
  169. static void rtc_wait_not_busy(struct omap_rtc *rtc)
  170. {
  171. int count;
  172. u8 status;
  173. /* BUSY may stay active for 1/32768 second (~30 usec) */
  174. for (count = 0; count < 50; count++) {
  175. status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
  176. if (!(status & OMAP_RTC_STATUS_BUSY))
  177. break;
  178. udelay(1);
  179. }
  180. /* now we have ~15 usec to read/write various registers */
  181. }
  182. static irqreturn_t rtc_irq(int irq, void *dev_id)
  183. {
  184. struct omap_rtc *rtc = dev_id;
  185. unsigned long events = 0;
  186. u8 irq_data;
  187. irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
  188. /* alarm irq? */
  189. if (irq_data & OMAP_RTC_STATUS_ALARM) {
  190. rtc->type->unlock(rtc);
  191. rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
  192. rtc->type->lock(rtc);
  193. events |= RTC_IRQF | RTC_AF;
  194. }
  195. /* 1/sec periodic/update irq? */
  196. if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
  197. events |= RTC_IRQF | RTC_UF;
  198. rtc_update_irq(rtc->rtc, 1, events);
  199. return IRQ_HANDLED;
  200. }
  201. static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  202. {
  203. struct omap_rtc *rtc = dev_get_drvdata(dev);
  204. u8 reg, irqwake_reg = 0;
  205. local_irq_disable();
  206. rtc_wait_not_busy(rtc);
  207. reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  208. if (rtc->type->has_irqwakeen)
  209. irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
  210. if (enabled) {
  211. reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
  212. irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
  213. } else {
  214. reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
  215. irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
  216. }
  217. rtc_wait_not_busy(rtc);
  218. rtc->type->unlock(rtc);
  219. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
  220. if (rtc->type->has_irqwakeen)
  221. rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
  222. rtc->type->lock(rtc);
  223. local_irq_enable();
  224. return 0;
  225. }
  226. /* this hardware doesn't support "don't care" alarm fields */
  227. static void tm2bcd(struct rtc_time *tm)
  228. {
  229. tm->tm_sec = bin2bcd(tm->tm_sec);
  230. tm->tm_min = bin2bcd(tm->tm_min);
  231. tm->tm_hour = bin2bcd(tm->tm_hour);
  232. tm->tm_mday = bin2bcd(tm->tm_mday);
  233. tm->tm_mon = bin2bcd(tm->tm_mon + 1);
  234. tm->tm_year = bin2bcd(tm->tm_year - 100);
  235. }
  236. static void bcd2tm(struct rtc_time *tm)
  237. {
  238. tm->tm_sec = bcd2bin(tm->tm_sec);
  239. tm->tm_min = bcd2bin(tm->tm_min);
  240. tm->tm_hour = bcd2bin(tm->tm_hour);
  241. tm->tm_mday = bcd2bin(tm->tm_mday);
  242. tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
  243. /* epoch == 1900 */
  244. tm->tm_year = bcd2bin(tm->tm_year) + 100;
  245. }
  246. static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
  247. {
  248. tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
  249. tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
  250. tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
  251. tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
  252. tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
  253. tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
  254. }
  255. static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
  256. {
  257. struct omap_rtc *rtc = dev_get_drvdata(dev);
  258. /* we don't report wday/yday/isdst ... */
  259. local_irq_disable();
  260. rtc_wait_not_busy(rtc);
  261. omap_rtc_read_time_raw(rtc, tm);
  262. local_irq_enable();
  263. bcd2tm(tm);
  264. return 0;
  265. }
  266. static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
  267. {
  268. struct omap_rtc *rtc = dev_get_drvdata(dev);
  269. tm2bcd(tm);
  270. local_irq_disable();
  271. rtc_wait_not_busy(rtc);
  272. rtc->type->unlock(rtc);
  273. rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
  274. rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
  275. rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
  276. rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
  277. rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
  278. rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
  279. rtc->type->lock(rtc);
  280. local_irq_enable();
  281. return 0;
  282. }
  283. static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  284. {
  285. struct omap_rtc *rtc = dev_get_drvdata(dev);
  286. u8 interrupts;
  287. local_irq_disable();
  288. rtc_wait_not_busy(rtc);
  289. alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
  290. alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
  291. alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
  292. alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
  293. alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
  294. alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
  295. local_irq_enable();
  296. bcd2tm(&alm->time);
  297. interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  298. alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
  299. return 0;
  300. }
  301. static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  302. {
  303. struct omap_rtc *rtc = dev_get_drvdata(dev);
  304. u8 reg, irqwake_reg = 0;
  305. tm2bcd(&alm->time);
  306. local_irq_disable();
  307. rtc_wait_not_busy(rtc);
  308. rtc->type->unlock(rtc);
  309. rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
  310. rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
  311. rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
  312. rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
  313. rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
  314. rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
  315. reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  316. if (rtc->type->has_irqwakeen)
  317. irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
  318. if (alm->enabled) {
  319. reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
  320. irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
  321. } else {
  322. reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
  323. irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
  324. }
  325. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
  326. if (rtc->type->has_irqwakeen)
  327. rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
  328. rtc->type->lock(rtc);
  329. local_irq_enable();
  330. return 0;
  331. }
  332. static struct omap_rtc *omap_rtc_power_off_rtc;
  333. /**
  334. * omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
  335. * generates pmic_pwr_enable control, which can be used to control an external
  336. * PMIC.
  337. */
  338. int omap_rtc_power_off_program(struct device *dev)
  339. {
  340. struct omap_rtc *rtc = omap_rtc_power_off_rtc;
  341. struct rtc_time tm;
  342. unsigned long now;
  343. int seconds;
  344. u32 val;
  345. rtc->type->unlock(rtc);
  346. /* enable pmic_power_en control */
  347. val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
  348. rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
  349. again:
  350. /* Clear any existing ALARM2 event */
  351. rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
  352. /* set alarm one second from now */
  353. omap_rtc_read_time_raw(rtc, &tm);
  354. seconds = tm.tm_sec;
  355. bcd2tm(&tm);
  356. now = rtc_tm_to_time64(&tm);
  357. rtc_time64_to_tm(now + 1, &tm);
  358. tm2bcd(&tm);
  359. rtc_wait_not_busy(rtc);
  360. rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
  361. rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
  362. rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
  363. rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
  364. rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
  365. rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
  366. /*
  367. * enable ALARM2 interrupt
  368. *
  369. * NOTE: this fails on AM3352 if rtc_write (writeb) is used
  370. */
  371. val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  372. rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
  373. val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
  374. /* Retry in case roll over happened before alarm was armed. */
  375. if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
  376. val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
  377. if (!(val & OMAP_RTC_STATUS_ALARM2))
  378. goto again;
  379. }
  380. rtc->type->lock(rtc);
  381. return 0;
  382. }
  383. EXPORT_SYMBOL(omap_rtc_power_off_program);
  384. /*
  385. * omap_rtc_poweroff: RTC-controlled power off
  386. *
  387. * The RTC can be used to control an external PMIC via the pmic_power_en pin,
  388. * which can be configured to transition to OFF on ALARM2 events.
  389. *
  390. * Notes:
  391. * The one-second alarm offset is the shortest offset possible as the alarm
  392. * registers must be set before the next timer update and the offset
  393. * calculation is too heavy for everything to be done within a single access
  394. * period (~15 us).
  395. *
  396. * Called with local interrupts disabled.
  397. */
  398. static void omap_rtc_power_off(void)
  399. {
  400. struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
  401. u32 val;
  402. omap_rtc_power_off_program(rtc->dev.parent);
  403. /* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
  404. omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
  405. val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
  406. val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) |
  407. OMAP_RTC_PMIC_EXT_WKUP_EN(0);
  408. rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
  409. omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
  410. /*
  411. * Wait for alarm to trigger (within one second) and external PMIC to
  412. * power off the system. Add a 500 ms margin for external latencies
  413. * (e.g. debounce circuits).
  414. */
  415. mdelay(1500);
  416. }
  417. static const struct rtc_class_ops omap_rtc_ops = {
  418. .read_time = omap_rtc_read_time,
  419. .set_time = omap_rtc_set_time,
  420. .read_alarm = omap_rtc_read_alarm,
  421. .set_alarm = omap_rtc_set_alarm,
  422. .alarm_irq_enable = omap_rtc_alarm_irq_enable,
  423. };
  424. static const struct omap_rtc_device_type omap_rtc_default_type = {
  425. .has_power_up_reset = true,
  426. .lock = default_rtc_lock,
  427. .unlock = default_rtc_unlock,
  428. };
  429. static const struct omap_rtc_device_type omap_rtc_am3352_type = {
  430. .has_32kclk_en = true,
  431. .has_irqwakeen = true,
  432. .has_pmic_mode = true,
  433. .lock = am3352_rtc_lock,
  434. .unlock = am3352_rtc_unlock,
  435. };
  436. static const struct omap_rtc_device_type omap_rtc_da830_type = {
  437. .lock = am3352_rtc_lock,
  438. .unlock = am3352_rtc_unlock,
  439. };
  440. static const struct platform_device_id omap_rtc_id_table[] = {
  441. {
  442. .name = "omap_rtc",
  443. .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
  444. }, {
  445. .name = "am3352-rtc",
  446. .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
  447. }, {
  448. .name = "da830-rtc",
  449. .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
  450. }, {
  451. /* sentinel */
  452. }
  453. };
  454. MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
  455. static const struct of_device_id omap_rtc_of_match[] = {
  456. {
  457. .compatible = "ti,am3352-rtc",
  458. .data = &omap_rtc_am3352_type,
  459. }, {
  460. .compatible = "ti,da830-rtc",
  461. .data = &omap_rtc_da830_type,
  462. }, {
  463. /* sentinel */
  464. }
  465. };
  466. MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
  467. static const struct pinctrl_pin_desc rtc_pins_desc[] = {
  468. PINCTRL_PIN(0, "ext_wakeup0"),
  469. PINCTRL_PIN(1, "ext_wakeup1"),
  470. PINCTRL_PIN(2, "ext_wakeup2"),
  471. PINCTRL_PIN(3, "ext_wakeup3"),
  472. };
  473. static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  474. {
  475. return 0;
  476. }
  477. static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  478. unsigned int group)
  479. {
  480. return NULL;
  481. }
  482. static const struct pinctrl_ops rtc_pinctrl_ops = {
  483. .get_groups_count = rtc_pinctrl_get_groups_count,
  484. .get_group_name = rtc_pinctrl_get_group_name,
  485. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  486. .dt_free_map = pinconf_generic_dt_free_map,
  487. };
  488. #define PIN_CONFIG_ACTIVE_HIGH (PIN_CONFIG_END + 1)
  489. static const struct pinconf_generic_params rtc_params[] = {
  490. {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
  491. };
  492. #ifdef CONFIG_DEBUG_FS
  493. static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
  494. PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
  495. };
  496. #endif
  497. static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
  498. unsigned int pin, unsigned long *config)
  499. {
  500. struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
  501. unsigned int param = pinconf_to_config_param(*config);
  502. u32 val;
  503. u16 arg = 0;
  504. val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
  505. switch (param) {
  506. case PIN_CONFIG_INPUT_ENABLE:
  507. if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
  508. return -EINVAL;
  509. break;
  510. case PIN_CONFIG_ACTIVE_HIGH:
  511. if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
  512. return -EINVAL;
  513. break;
  514. default:
  515. return -ENOTSUPP;
  516. }
  517. *config = pinconf_to_config_packed(param, arg);
  518. return 0;
  519. }
  520. static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
  521. unsigned int pin, unsigned long *configs,
  522. unsigned int num_configs)
  523. {
  524. struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
  525. u32 val;
  526. unsigned int param;
  527. u32 param_val;
  528. int i;
  529. val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
  530. /* active low by default */
  531. val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
  532. for (i = 0; i < num_configs; i++) {
  533. param = pinconf_to_config_param(configs[i]);
  534. param_val = pinconf_to_config_argument(configs[i]);
  535. switch (param) {
  536. case PIN_CONFIG_INPUT_ENABLE:
  537. if (param_val)
  538. val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
  539. else
  540. val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
  541. break;
  542. case PIN_CONFIG_ACTIVE_HIGH:
  543. val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
  544. break;
  545. default:
  546. dev_err(&rtc->rtc->dev, "Property %u not supported\n",
  547. param);
  548. return -ENOTSUPP;
  549. }
  550. }
  551. rtc->type->unlock(rtc);
  552. rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
  553. rtc->type->lock(rtc);
  554. return 0;
  555. }
  556. static const struct pinconf_ops rtc_pinconf_ops = {
  557. .is_generic = true,
  558. .pin_config_get = rtc_pinconf_get,
  559. .pin_config_set = rtc_pinconf_set,
  560. };
  561. static struct pinctrl_desc rtc_pinctrl_desc = {
  562. .pins = rtc_pins_desc,
  563. .npins = ARRAY_SIZE(rtc_pins_desc),
  564. .pctlops = &rtc_pinctrl_ops,
  565. .confops = &rtc_pinconf_ops,
  566. .custom_params = rtc_params,
  567. .num_custom_params = ARRAY_SIZE(rtc_params),
  568. #ifdef CONFIG_DEBUG_FS
  569. .custom_conf_items = rtc_conf_items,
  570. #endif
  571. .owner = THIS_MODULE,
  572. };
  573. static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
  574. size_t bytes)
  575. {
  576. struct omap_rtc *rtc = priv;
  577. u32 *val = _val;
  578. int i;
  579. for (i = 0; i < bytes / 4; i++)
  580. val[i] = rtc_readl(rtc,
  581. OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
  582. return 0;
  583. }
  584. static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
  585. size_t bytes)
  586. {
  587. struct omap_rtc *rtc = priv;
  588. u32 *val = _val;
  589. int i;
  590. rtc->type->unlock(rtc);
  591. for (i = 0; i < bytes / 4; i++)
  592. rtc_writel(rtc,
  593. OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
  594. rtc->type->lock(rtc);
  595. return 0;
  596. }
  597. static struct nvmem_config omap_rtc_nvmem_config = {
  598. .name = "omap_rtc_scratch",
  599. .word_size = 4,
  600. .stride = 4,
  601. .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
  602. .reg_read = omap_rtc_scratch_read,
  603. .reg_write = omap_rtc_scratch_write,
  604. };
  605. static int omap_rtc_probe(struct platform_device *pdev)
  606. {
  607. struct omap_rtc *rtc;
  608. u8 reg, mask, new_ctrl;
  609. const struct platform_device_id *id_entry;
  610. const struct of_device_id *of_id;
  611. int ret;
  612. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  613. if (!rtc)
  614. return -ENOMEM;
  615. of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
  616. if (of_id) {
  617. rtc->type = of_id->data;
  618. rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
  619. of_device_is_system_power_controller(pdev->dev.of_node);
  620. } else {
  621. id_entry = platform_get_device_id(pdev);
  622. rtc->type = (void *)id_entry->driver_data;
  623. }
  624. rtc->irq_timer = platform_get_irq(pdev, 0);
  625. if (rtc->irq_timer <= 0)
  626. return -ENOENT;
  627. rtc->irq_alarm = platform_get_irq(pdev, 1);
  628. if (rtc->irq_alarm <= 0)
  629. return -ENOENT;
  630. rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
  631. if (!IS_ERR(rtc->clk))
  632. rtc->has_ext_clk = true;
  633. else
  634. rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
  635. if (!IS_ERR(rtc->clk))
  636. clk_prepare_enable(rtc->clk);
  637. rtc->base = devm_platform_ioremap_resource(pdev, 0);
  638. if (IS_ERR(rtc->base)) {
  639. clk_disable_unprepare(rtc->clk);
  640. return PTR_ERR(rtc->base);
  641. }
  642. platform_set_drvdata(pdev, rtc);
  643. /* Enable the clock/module so that we can access the registers */
  644. pm_runtime_enable(&pdev->dev);
  645. pm_runtime_get_sync(&pdev->dev);
  646. rtc->type->unlock(rtc);
  647. /*
  648. * disable interrupts
  649. *
  650. * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
  651. */
  652. rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
  653. /* enable RTC functional clock */
  654. if (rtc->type->has_32kclk_en) {
  655. reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
  656. rtc_writel(rtc, OMAP_RTC_OSC_REG,
  657. reg | OMAP_RTC_OSC_32KCLK_EN);
  658. }
  659. /* clear old status */
  660. reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
  661. mask = OMAP_RTC_STATUS_ALARM;
  662. if (rtc->type->has_pmic_mode)
  663. mask |= OMAP_RTC_STATUS_ALARM2;
  664. if (rtc->type->has_power_up_reset) {
  665. mask |= OMAP_RTC_STATUS_POWER_UP;
  666. if (reg & OMAP_RTC_STATUS_POWER_UP)
  667. dev_info(&pdev->dev, "RTC power up reset detected\n");
  668. }
  669. if (reg & mask)
  670. rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
  671. /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
  672. reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
  673. if (reg & OMAP_RTC_CTRL_STOP)
  674. dev_info(&pdev->dev, "already running\n");
  675. /* force to 24 hour mode */
  676. new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
  677. new_ctrl |= OMAP_RTC_CTRL_STOP;
  678. /*
  679. * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
  680. *
  681. * - Device wake-up capability setting should come through chip
  682. * init logic. OMAP1 boards should initialize the "wakeup capable"
  683. * flag in the platform device if the board is wired right for
  684. * being woken up by RTC alarm. For OMAP-L138, this capability
  685. * is built into the SoC by the "Deep Sleep" capability.
  686. *
  687. * - Boards wired so RTC_ON_nOFF is used as the reset signal,
  688. * rather than nPWRON_RESET, should forcibly enable split
  689. * power mode. (Some chip errata report that RTC_CTRL_SPLIT
  690. * is write-only, and always reads as zero...)
  691. */
  692. if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
  693. dev_info(&pdev->dev, "split power mode\n");
  694. if (reg != new_ctrl)
  695. rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
  696. /*
  697. * If we have the external clock then switch to it so we can keep
  698. * ticking across suspend.
  699. */
  700. if (rtc->has_ext_clk) {
  701. reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
  702. reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
  703. reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
  704. rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
  705. }
  706. rtc->type->lock(rtc);
  707. device_init_wakeup(&pdev->dev, true);
  708. rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
  709. if (IS_ERR(rtc->rtc)) {
  710. ret = PTR_ERR(rtc->rtc);
  711. goto err;
  712. }
  713. rtc->rtc->ops = &omap_rtc_ops;
  714. rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  715. rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
  716. omap_rtc_nvmem_config.priv = rtc;
  717. /* handle periodic and alarm irqs */
  718. ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
  719. dev_name(&rtc->rtc->dev), rtc);
  720. if (ret)
  721. goto err;
  722. if (rtc->irq_timer != rtc->irq_alarm) {
  723. ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
  724. dev_name(&rtc->rtc->dev), rtc);
  725. if (ret)
  726. goto err;
  727. }
  728. /* Support ext_wakeup pinconf */
  729. rtc_pinctrl_desc.name = dev_name(&pdev->dev);
  730. rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
  731. if (IS_ERR(rtc->pctldev)) {
  732. dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
  733. ret = PTR_ERR(rtc->pctldev);
  734. goto err;
  735. }
  736. ret = rtc_register_device(rtc->rtc);
  737. if (ret)
  738. goto err_deregister_pinctrl;
  739. rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
  740. if (rtc->is_pmic_controller) {
  741. if (!pm_power_off) {
  742. omap_rtc_power_off_rtc = rtc;
  743. pm_power_off = omap_rtc_power_off;
  744. }
  745. }
  746. return 0;
  747. err_deregister_pinctrl:
  748. pinctrl_unregister(rtc->pctldev);
  749. err:
  750. clk_disable_unprepare(rtc->clk);
  751. device_init_wakeup(&pdev->dev, false);
  752. rtc->type->lock(rtc);
  753. pm_runtime_put_sync(&pdev->dev);
  754. pm_runtime_disable(&pdev->dev);
  755. return ret;
  756. }
  757. static int omap_rtc_remove(struct platform_device *pdev)
  758. {
  759. struct omap_rtc *rtc = platform_get_drvdata(pdev);
  760. u8 reg;
  761. if (pm_power_off == omap_rtc_power_off &&
  762. omap_rtc_power_off_rtc == rtc) {
  763. pm_power_off = NULL;
  764. omap_rtc_power_off_rtc = NULL;
  765. }
  766. device_init_wakeup(&pdev->dev, 0);
  767. if (!IS_ERR(rtc->clk))
  768. clk_disable_unprepare(rtc->clk);
  769. rtc->type->unlock(rtc);
  770. /* leave rtc running, but disable irqs */
  771. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
  772. if (rtc->has_ext_clk) {
  773. reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
  774. reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
  775. rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
  776. }
  777. rtc->type->lock(rtc);
  778. /* Disable the clock/module */
  779. pm_runtime_put_sync(&pdev->dev);
  780. pm_runtime_disable(&pdev->dev);
  781. /* Remove ext_wakeup pinconf */
  782. pinctrl_unregister(rtc->pctldev);
  783. return 0;
  784. }
  785. static int __maybe_unused omap_rtc_suspend(struct device *dev)
  786. {
  787. struct omap_rtc *rtc = dev_get_drvdata(dev);
  788. rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  789. rtc->type->unlock(rtc);
  790. /*
  791. * FIXME: the RTC alarm is not currently acting as a wakeup event
  792. * source on some platforms, and in fact this enable() call is just
  793. * saving a flag that's never used...
  794. */
  795. if (device_may_wakeup(dev))
  796. enable_irq_wake(rtc->irq_alarm);
  797. else
  798. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
  799. rtc->type->lock(rtc);
  800. rtc->is_suspending = true;
  801. return 0;
  802. }
  803. static int __maybe_unused omap_rtc_resume(struct device *dev)
  804. {
  805. struct omap_rtc *rtc = dev_get_drvdata(dev);
  806. rtc->type->unlock(rtc);
  807. if (device_may_wakeup(dev))
  808. disable_irq_wake(rtc->irq_alarm);
  809. else
  810. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
  811. rtc->type->lock(rtc);
  812. rtc->is_suspending = false;
  813. return 0;
  814. }
  815. static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
  816. {
  817. struct omap_rtc *rtc = dev_get_drvdata(dev);
  818. if (rtc->is_suspending && !rtc->has_ext_clk)
  819. return -EBUSY;
  820. return 0;
  821. }
  822. static const struct dev_pm_ops omap_rtc_pm_ops = {
  823. SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
  824. SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
  825. };
  826. static void omap_rtc_shutdown(struct platform_device *pdev)
  827. {
  828. struct omap_rtc *rtc = platform_get_drvdata(pdev);
  829. u8 mask;
  830. /*
  831. * Keep the ALARM interrupt enabled to allow the system to power up on
  832. * alarm events.
  833. */
  834. rtc->type->unlock(rtc);
  835. mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
  836. mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
  837. rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
  838. rtc->type->lock(rtc);
  839. }
  840. static struct platform_driver omap_rtc_driver = {
  841. .probe = omap_rtc_probe,
  842. .remove = omap_rtc_remove,
  843. .shutdown = omap_rtc_shutdown,
  844. .driver = {
  845. .name = "omap_rtc",
  846. .pm = &omap_rtc_pm_ops,
  847. .of_match_table = omap_rtc_of_match,
  848. },
  849. .id_table = omap_rtc_id_table,
  850. };
  851. module_platform_driver(omap_rtc_driver);
  852. MODULE_ALIAS("platform:omap_rtc");
  853. MODULE_AUTHOR("George G. Davis (and others)");
  854. MODULE_LICENSE("GPL");