rtc-mxc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  4. #include <linux/io.h>
  5. #include <linux/rtc.h>
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/pm_wakeirq.h>
  11. #include <linux/clk.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #define RTC_INPUT_CLK_32768HZ (0x00 << 5)
  15. #define RTC_INPUT_CLK_32000HZ (0x01 << 5)
  16. #define RTC_INPUT_CLK_38400HZ (0x02 << 5)
  17. #define RTC_SW_BIT (1 << 0)
  18. #define RTC_ALM_BIT (1 << 2)
  19. #define RTC_1HZ_BIT (1 << 4)
  20. #define RTC_2HZ_BIT (1 << 7)
  21. #define RTC_SAM0_BIT (1 << 8)
  22. #define RTC_SAM1_BIT (1 << 9)
  23. #define RTC_SAM2_BIT (1 << 10)
  24. #define RTC_SAM3_BIT (1 << 11)
  25. #define RTC_SAM4_BIT (1 << 12)
  26. #define RTC_SAM5_BIT (1 << 13)
  27. #define RTC_SAM6_BIT (1 << 14)
  28. #define RTC_SAM7_BIT (1 << 15)
  29. #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
  30. RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
  31. RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
  32. #define RTC_ENABLE_BIT (1 << 7)
  33. #define MAX_PIE_NUM 9
  34. #define MAX_PIE_FREQ 512
  35. #define MXC_RTC_TIME 0
  36. #define MXC_RTC_ALARM 1
  37. #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
  38. #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
  39. #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
  40. #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
  41. #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
  42. #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
  43. #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
  44. #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
  45. #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
  46. #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
  47. #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
  48. #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
  49. #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
  50. enum imx_rtc_type {
  51. IMX1_RTC,
  52. IMX21_RTC,
  53. };
  54. struct rtc_plat_data {
  55. struct rtc_device *rtc;
  56. void __iomem *ioaddr;
  57. int irq;
  58. struct clk *clk_ref;
  59. struct clk *clk_ipg;
  60. struct rtc_time g_rtc_alarm;
  61. enum imx_rtc_type devtype;
  62. };
  63. static const struct platform_device_id imx_rtc_devtype[] = {
  64. {
  65. .name = "imx1-rtc",
  66. .driver_data = IMX1_RTC,
  67. }, {
  68. .name = "imx21-rtc",
  69. .driver_data = IMX21_RTC,
  70. }, {
  71. /* sentinel */
  72. }
  73. };
  74. MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
  75. #ifdef CONFIG_OF
  76. static const struct of_device_id imx_rtc_dt_ids[] = {
  77. { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
  78. { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
  79. {}
  80. };
  81. MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
  82. #endif
  83. static inline int is_imx1_rtc(struct rtc_plat_data *data)
  84. {
  85. return data->devtype == IMX1_RTC;
  86. }
  87. /*
  88. * This function is used to obtain the RTC time or the alarm value in
  89. * second.
  90. */
  91. static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
  92. {
  93. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  94. void __iomem *ioaddr = pdata->ioaddr;
  95. u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
  96. switch (time_alarm) {
  97. case MXC_RTC_TIME:
  98. day = readw(ioaddr + RTC_DAYR);
  99. hr_min = readw(ioaddr + RTC_HOURMIN);
  100. sec = readw(ioaddr + RTC_SECOND);
  101. break;
  102. case MXC_RTC_ALARM:
  103. day = readw(ioaddr + RTC_DAYALARM);
  104. hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
  105. sec = readw(ioaddr + RTC_ALRM_SEC);
  106. break;
  107. }
  108. hr = hr_min >> 8;
  109. min = hr_min & 0xff;
  110. return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
  111. }
  112. /*
  113. * This function sets the RTC alarm value or the time value.
  114. */
  115. static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
  116. {
  117. u32 tod, day, hr, min, sec, temp;
  118. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  119. void __iomem *ioaddr = pdata->ioaddr;
  120. day = div_s64_rem(time, 86400, &tod);
  121. /* time is within a day now */
  122. hr = tod / 3600;
  123. tod -= hr * 3600;
  124. /* time is within an hour now */
  125. min = tod / 60;
  126. sec = tod - min * 60;
  127. temp = (hr << 8) + min;
  128. switch (time_alarm) {
  129. case MXC_RTC_TIME:
  130. writew(day, ioaddr + RTC_DAYR);
  131. writew(sec, ioaddr + RTC_SECOND);
  132. writew(temp, ioaddr + RTC_HOURMIN);
  133. break;
  134. case MXC_RTC_ALARM:
  135. writew(day, ioaddr + RTC_DAYALARM);
  136. writew(sec, ioaddr + RTC_ALRM_SEC);
  137. writew(temp, ioaddr + RTC_ALRM_HM);
  138. break;
  139. }
  140. }
  141. /*
  142. * This function updates the RTC alarm registers and then clears all the
  143. * interrupt status bits.
  144. */
  145. static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
  146. {
  147. time64_t time;
  148. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  149. void __iomem *ioaddr = pdata->ioaddr;
  150. time = rtc_tm_to_time64(alrm);
  151. /* clear all the interrupt status bits */
  152. writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
  153. set_alarm_or_time(dev, MXC_RTC_ALARM, time);
  154. }
  155. static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
  156. unsigned int enabled)
  157. {
  158. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  159. void __iomem *ioaddr = pdata->ioaddr;
  160. u32 reg;
  161. unsigned long flags;
  162. spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
  163. reg = readw(ioaddr + RTC_RTCIENR);
  164. if (enabled)
  165. reg |= bit;
  166. else
  167. reg &= ~bit;
  168. writew(reg, ioaddr + RTC_RTCIENR);
  169. spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
  170. }
  171. /* This function is the RTC interrupt service routine. */
  172. static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
  173. {
  174. struct platform_device *pdev = dev_id;
  175. struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
  176. void __iomem *ioaddr = pdata->ioaddr;
  177. unsigned long flags;
  178. u32 status;
  179. u32 events = 0;
  180. spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
  181. status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
  182. /* clear interrupt sources */
  183. writew(status, ioaddr + RTC_RTCISR);
  184. /* update irq data & counter */
  185. if (status & RTC_ALM_BIT) {
  186. events |= (RTC_AF | RTC_IRQF);
  187. /* RTC alarm should be one-shot */
  188. mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
  189. }
  190. if (status & PIT_ALL_ON)
  191. events |= (RTC_PF | RTC_IRQF);
  192. rtc_update_irq(pdata->rtc, 1, events);
  193. spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
  194. return IRQ_HANDLED;
  195. }
  196. static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  197. {
  198. mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
  199. return 0;
  200. }
  201. /*
  202. * This function reads the current RTC time into tm in Gregorian date.
  203. */
  204. static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
  205. {
  206. time64_t val;
  207. /* Avoid roll-over from reading the different registers */
  208. do {
  209. val = get_alarm_or_time(dev, MXC_RTC_TIME);
  210. } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
  211. rtc_time64_to_tm(val, tm);
  212. return 0;
  213. }
  214. /*
  215. * This function sets the internal RTC time based on tm in Gregorian date.
  216. */
  217. static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
  218. {
  219. time64_t time = rtc_tm_to_time64(tm);
  220. /* Avoid roll-over from reading the different registers */
  221. do {
  222. set_alarm_or_time(dev, MXC_RTC_TIME, time);
  223. } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
  224. return 0;
  225. }
  226. /*
  227. * This function reads the current alarm value into the passed in 'alrm'
  228. * argument. It updates the alrm's pending field value based on the whether
  229. * an alarm interrupt occurs or not.
  230. */
  231. static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  232. {
  233. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  234. void __iomem *ioaddr = pdata->ioaddr;
  235. rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
  236. alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
  237. return 0;
  238. }
  239. /*
  240. * This function sets the RTC alarm based on passed in alrm.
  241. */
  242. static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  243. {
  244. struct rtc_plat_data *pdata = dev_get_drvdata(dev);
  245. rtc_update_alarm(dev, &alrm->time);
  246. memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
  247. mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
  248. return 0;
  249. }
  250. /* RTC layer */
  251. static const struct rtc_class_ops mxc_rtc_ops = {
  252. .read_time = mxc_rtc_read_time,
  253. .set_time = mxc_rtc_set_time,
  254. .read_alarm = mxc_rtc_read_alarm,
  255. .set_alarm = mxc_rtc_set_alarm,
  256. .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
  257. };
  258. static void mxc_rtc_action(void *p)
  259. {
  260. struct rtc_plat_data *pdata = p;
  261. clk_disable_unprepare(pdata->clk_ref);
  262. clk_disable_unprepare(pdata->clk_ipg);
  263. }
  264. static int mxc_rtc_probe(struct platform_device *pdev)
  265. {
  266. struct rtc_device *rtc;
  267. struct rtc_plat_data *pdata = NULL;
  268. u32 reg;
  269. unsigned long rate;
  270. int ret;
  271. const struct of_device_id *of_id;
  272. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  273. if (!pdata)
  274. return -ENOMEM;
  275. of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
  276. if (of_id)
  277. pdata->devtype = (enum imx_rtc_type)of_id->data;
  278. else
  279. pdata->devtype = pdev->id_entry->driver_data;
  280. pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
  281. if (IS_ERR(pdata->ioaddr))
  282. return PTR_ERR(pdata->ioaddr);
  283. rtc = devm_rtc_allocate_device(&pdev->dev);
  284. if (IS_ERR(rtc))
  285. return PTR_ERR(rtc);
  286. pdata->rtc = rtc;
  287. rtc->ops = &mxc_rtc_ops;
  288. if (is_imx1_rtc(pdata)) {
  289. struct rtc_time tm;
  290. /* 9bit days + hours minutes seconds */
  291. rtc->range_max = (1 << 9) * 86400 - 1;
  292. /*
  293. * Set the start date as beginning of the current year. This can
  294. * be overridden using device tree.
  295. */
  296. rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
  297. rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0);
  298. rtc->set_start_time = true;
  299. } else {
  300. /* 16bit days + hours minutes seconds */
  301. rtc->range_max = (1 << 16) * 86400ULL - 1;
  302. }
  303. pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  304. if (IS_ERR(pdata->clk_ipg)) {
  305. dev_err(&pdev->dev, "unable to get ipg clock!\n");
  306. return PTR_ERR(pdata->clk_ipg);
  307. }
  308. ret = clk_prepare_enable(pdata->clk_ipg);
  309. if (ret)
  310. return ret;
  311. pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
  312. if (IS_ERR(pdata->clk_ref)) {
  313. clk_disable_unprepare(pdata->clk_ipg);
  314. dev_err(&pdev->dev, "unable to get ref clock!\n");
  315. return PTR_ERR(pdata->clk_ref);
  316. }
  317. ret = clk_prepare_enable(pdata->clk_ref);
  318. if (ret) {
  319. clk_disable_unprepare(pdata->clk_ipg);
  320. return ret;
  321. }
  322. ret = devm_add_action_or_reset(&pdev->dev, mxc_rtc_action, pdata);
  323. if (ret)
  324. return ret;
  325. rate = clk_get_rate(pdata->clk_ref);
  326. if (rate == 32768)
  327. reg = RTC_INPUT_CLK_32768HZ;
  328. else if (rate == 32000)
  329. reg = RTC_INPUT_CLK_32000HZ;
  330. else if (rate == 38400)
  331. reg = RTC_INPUT_CLK_38400HZ;
  332. else {
  333. dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
  334. return -EINVAL;
  335. }
  336. reg |= RTC_ENABLE_BIT;
  337. writew(reg, (pdata->ioaddr + RTC_RTCCTL));
  338. if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
  339. dev_err(&pdev->dev, "hardware module can't be enabled!\n");
  340. return -EIO;
  341. }
  342. platform_set_drvdata(pdev, pdata);
  343. /* Configure and enable the RTC */
  344. pdata->irq = platform_get_irq(pdev, 0);
  345. if (pdata->irq >= 0 &&
  346. devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
  347. IRQF_SHARED, pdev->name, pdev) < 0) {
  348. dev_warn(&pdev->dev, "interrupt not available.\n");
  349. pdata->irq = -1;
  350. }
  351. if (pdata->irq >= 0) {
  352. device_init_wakeup(&pdev->dev, 1);
  353. ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
  354. if (ret)
  355. dev_err(&pdev->dev, "failed to enable irq wake\n");
  356. }
  357. ret = rtc_register_device(rtc);
  358. return ret;
  359. }
  360. static struct platform_driver mxc_rtc_driver = {
  361. .driver = {
  362. .name = "mxc_rtc",
  363. .of_match_table = of_match_ptr(imx_rtc_dt_ids),
  364. },
  365. .id_table = imx_rtc_devtype,
  366. .probe = mxc_rtc_probe,
  367. };
  368. module_platform_driver(mxc_rtc_driver)
  369. MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
  370. MODULE_DESCRIPTION("RTC driver for Freescale MXC");
  371. MODULE_LICENSE("GPL");