rtc-mt6397.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2015 MediaTek Inc.
  4. * Author: Tianping.Fang <tianping.fang@mediatek.com>
  5. */
  6. #include <linux/err.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/mfd/mt6397/core.h>
  9. #include <linux/module.h>
  10. #include <linux/mutex.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. #include <linux/rtc.h>
  15. #include <linux/mfd/mt6397/rtc.h>
  16. #include <linux/mod_devicetable.h>
  17. static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
  18. {
  19. int ret;
  20. u32 data;
  21. ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1);
  22. if (ret < 0)
  23. return ret;
  24. ret = regmap_read_poll_timeout(rtc->regmap,
  25. rtc->addr_base + RTC_BBPU, data,
  26. !(data & RTC_BBPU_CBUSY),
  27. MTK_RTC_POLL_DELAY_US,
  28. MTK_RTC_POLL_TIMEOUT);
  29. if (ret < 0)
  30. dev_err(rtc->rtc_dev->dev.parent,
  31. "failed to write WRTGR: %d\n", ret);
  32. return ret;
  33. }
  34. static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
  35. {
  36. struct mt6397_rtc *rtc = data;
  37. u32 irqsta, irqen;
  38. int ret;
  39. ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
  40. if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
  41. rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
  42. irqen = irqsta & ~RTC_IRQ_EN_AL;
  43. mutex_lock(&rtc->lock);
  44. if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
  45. irqen) == 0)
  46. mtk_rtc_write_trigger(rtc);
  47. mutex_unlock(&rtc->lock);
  48. return IRQ_HANDLED;
  49. }
  50. return IRQ_NONE;
  51. }
  52. static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
  53. struct rtc_time *tm, int *sec)
  54. {
  55. int ret;
  56. u16 data[RTC_OFFSET_COUNT];
  57. mutex_lock(&rtc->lock);
  58. ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
  59. data, RTC_OFFSET_COUNT);
  60. if (ret < 0)
  61. goto exit;
  62. tm->tm_sec = data[RTC_OFFSET_SEC];
  63. tm->tm_min = data[RTC_OFFSET_MIN];
  64. tm->tm_hour = data[RTC_OFFSET_HOUR];
  65. tm->tm_mday = data[RTC_OFFSET_DOM];
  66. tm->tm_mon = data[RTC_OFFSET_MTH];
  67. tm->tm_year = data[RTC_OFFSET_YEAR];
  68. ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
  69. exit:
  70. mutex_unlock(&rtc->lock);
  71. return ret;
  72. }
  73. static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
  74. {
  75. time64_t time;
  76. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  77. int days, sec, ret;
  78. do {
  79. ret = __mtk_rtc_read_time(rtc, tm, &sec);
  80. if (ret < 0)
  81. goto exit;
  82. } while (sec < tm->tm_sec);
  83. /* HW register use 7 bits to store year data, minus
  84. * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
  85. * RTC_MIN_YEAR_OFFSET back after read year from register
  86. */
  87. tm->tm_year += RTC_MIN_YEAR_OFFSET;
  88. /* HW register start mon from one, but tm_mon start from zero. */
  89. tm->tm_mon--;
  90. time = rtc_tm_to_time64(tm);
  91. /* rtc_tm_to_time64 covert Gregorian date to seconds since
  92. * 01-01-1970 00:00:00, and this date is Thursday.
  93. */
  94. days = div_s64(time, 86400);
  95. tm->tm_wday = (days + 4) % 7;
  96. exit:
  97. return ret;
  98. }
  99. static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
  100. {
  101. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  102. int ret;
  103. u16 data[RTC_OFFSET_COUNT];
  104. tm->tm_year -= RTC_MIN_YEAR_OFFSET;
  105. tm->tm_mon++;
  106. data[RTC_OFFSET_SEC] = tm->tm_sec;
  107. data[RTC_OFFSET_MIN] = tm->tm_min;
  108. data[RTC_OFFSET_HOUR] = tm->tm_hour;
  109. data[RTC_OFFSET_DOM] = tm->tm_mday;
  110. data[RTC_OFFSET_MTH] = tm->tm_mon;
  111. data[RTC_OFFSET_YEAR] = tm->tm_year;
  112. mutex_lock(&rtc->lock);
  113. ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
  114. data, RTC_OFFSET_COUNT);
  115. if (ret < 0)
  116. goto exit;
  117. /* Time register write to hardware after call trigger function */
  118. ret = mtk_rtc_write_trigger(rtc);
  119. exit:
  120. mutex_unlock(&rtc->lock);
  121. return ret;
  122. }
  123. static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  124. {
  125. struct rtc_time *tm = &alm->time;
  126. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  127. u32 irqen, pdn2;
  128. int ret;
  129. u16 data[RTC_OFFSET_COUNT];
  130. mutex_lock(&rtc->lock);
  131. ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
  132. if (ret < 0)
  133. goto err_exit;
  134. ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
  135. if (ret < 0)
  136. goto err_exit;
  137. ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
  138. data, RTC_OFFSET_COUNT);
  139. if (ret < 0)
  140. goto err_exit;
  141. alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
  142. alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
  143. mutex_unlock(&rtc->lock);
  144. tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
  145. tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
  146. tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
  147. tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
  148. tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
  149. tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
  150. tm->tm_year += RTC_MIN_YEAR_OFFSET;
  151. tm->tm_mon--;
  152. return 0;
  153. err_exit:
  154. mutex_unlock(&rtc->lock);
  155. return ret;
  156. }
  157. static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  158. {
  159. struct rtc_time *tm = &alm->time;
  160. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  161. int ret;
  162. u16 data[RTC_OFFSET_COUNT];
  163. tm->tm_year -= RTC_MIN_YEAR_OFFSET;
  164. tm->tm_mon++;
  165. mutex_lock(&rtc->lock);
  166. ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
  167. data, RTC_OFFSET_COUNT);
  168. if (ret < 0)
  169. goto exit;
  170. data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
  171. (tm->tm_sec & RTC_AL_SEC_MASK));
  172. data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
  173. (tm->tm_min & RTC_AL_MIN_MASK));
  174. data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
  175. (tm->tm_hour & RTC_AL_HOU_MASK));
  176. data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
  177. (tm->tm_mday & RTC_AL_DOM_MASK));
  178. data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
  179. (tm->tm_mon & RTC_AL_MTH_MASK));
  180. data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
  181. (tm->tm_year & RTC_AL_YEA_MASK));
  182. if (alm->enabled) {
  183. ret = regmap_bulk_write(rtc->regmap,
  184. rtc->addr_base + RTC_AL_SEC,
  185. data, RTC_OFFSET_COUNT);
  186. if (ret < 0)
  187. goto exit;
  188. ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
  189. RTC_AL_MASK_DOW);
  190. if (ret < 0)
  191. goto exit;
  192. ret = regmap_update_bits(rtc->regmap,
  193. rtc->addr_base + RTC_IRQ_EN,
  194. RTC_IRQ_EN_ONESHOT_AL,
  195. RTC_IRQ_EN_ONESHOT_AL);
  196. if (ret < 0)
  197. goto exit;
  198. } else {
  199. ret = regmap_update_bits(rtc->regmap,
  200. rtc->addr_base + RTC_IRQ_EN,
  201. RTC_IRQ_EN_ONESHOT_AL, 0);
  202. if (ret < 0)
  203. goto exit;
  204. }
  205. /* All alarm time register write to hardware after calling
  206. * mtk_rtc_write_trigger. This can avoid race condition if alarm
  207. * occur happen during writing alarm time register.
  208. */
  209. ret = mtk_rtc_write_trigger(rtc);
  210. exit:
  211. mutex_unlock(&rtc->lock);
  212. return ret;
  213. }
  214. static const struct rtc_class_ops mtk_rtc_ops = {
  215. .read_time = mtk_rtc_read_time,
  216. .set_time = mtk_rtc_set_time,
  217. .read_alarm = mtk_rtc_read_alarm,
  218. .set_alarm = mtk_rtc_set_alarm,
  219. };
  220. static int mtk_rtc_probe(struct platform_device *pdev)
  221. {
  222. struct resource *res;
  223. struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
  224. struct mt6397_rtc *rtc;
  225. int ret;
  226. rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
  227. if (!rtc)
  228. return -ENOMEM;
  229. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  230. rtc->addr_base = res->start;
  231. rtc->data = of_device_get_match_data(&pdev->dev);
  232. rtc->irq = platform_get_irq(pdev, 0);
  233. if (rtc->irq < 0)
  234. return rtc->irq;
  235. rtc->regmap = mt6397_chip->regmap;
  236. mutex_init(&rtc->lock);
  237. platform_set_drvdata(pdev, rtc);
  238. rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
  239. if (IS_ERR(rtc->rtc_dev))
  240. return PTR_ERR(rtc->rtc_dev);
  241. ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
  242. mtk_rtc_irq_handler_thread,
  243. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  244. "mt6397-rtc", rtc);
  245. if (ret) {
  246. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  247. rtc->irq, ret);
  248. return ret;
  249. }
  250. device_init_wakeup(&pdev->dev, 1);
  251. rtc->rtc_dev->ops = &mtk_rtc_ops;
  252. return rtc_register_device(rtc->rtc_dev);
  253. }
  254. #ifdef CONFIG_PM_SLEEP
  255. static int mt6397_rtc_suspend(struct device *dev)
  256. {
  257. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  258. if (device_may_wakeup(dev))
  259. enable_irq_wake(rtc->irq);
  260. return 0;
  261. }
  262. static int mt6397_rtc_resume(struct device *dev)
  263. {
  264. struct mt6397_rtc *rtc = dev_get_drvdata(dev);
  265. if (device_may_wakeup(dev))
  266. disable_irq_wake(rtc->irq);
  267. return 0;
  268. }
  269. #endif
  270. static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
  271. mt6397_rtc_resume);
  272. static const struct mtk_rtc_data mt6358_rtc_data = {
  273. .wrtgr = RTC_WRTGR_MT6358,
  274. };
  275. static const struct mtk_rtc_data mt6397_rtc_data = {
  276. .wrtgr = RTC_WRTGR_MT6397,
  277. };
  278. static const struct of_device_id mt6397_rtc_of_match[] = {
  279. { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data },
  280. { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data },
  281. { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data },
  282. { }
  283. };
  284. MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
  285. static struct platform_driver mtk_rtc_driver = {
  286. .driver = {
  287. .name = "mt6397-rtc",
  288. .of_match_table = mt6397_rtc_of_match,
  289. .pm = &mt6397_pm_ops,
  290. },
  291. .probe = mtk_rtc_probe,
  292. };
  293. module_platform_driver(mtk_rtc_driver);
  294. MODULE_LICENSE("GPL v2");
  295. MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
  296. MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");