rtc-meson.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * RTC driver for the interal RTC block in the Amlogic Meson6, Meson8,
  4. * Meson8b and Meson8m2 SoCs.
  5. *
  6. * The RTC is split in to two parts, the AHB front end and a simple serial
  7. * connection to the actual registers. This driver manages both parts.
  8. *
  9. * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  10. * Copyright (c) 2015 Ben Dooks <ben.dooks@codethink.co.uk> for Codethink Ltd
  11. * Based on origin by Carlo Caione <carlo@endlessm.com>
  12. */
  13. #include <linux/bitfield.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/nvmem-provider.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regmap.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/reset.h>
  24. #include <linux/rtc.h>
  25. /* registers accessed from cpu bus */
  26. #define RTC_ADDR0 0x00
  27. #define RTC_ADDR0_LINE_SCLK BIT(0)
  28. #define RTC_ADDR0_LINE_SEN BIT(1)
  29. #define RTC_ADDR0_LINE_SDI BIT(2)
  30. #define RTC_ADDR0_START_SER BIT(17)
  31. #define RTC_ADDR0_WAIT_SER BIT(22)
  32. #define RTC_ADDR0_DATA GENMASK(31, 24)
  33. #define RTC_ADDR1 0x04
  34. #define RTC_ADDR1_SDO BIT(0)
  35. #define RTC_ADDR1_S_READY BIT(1)
  36. #define RTC_ADDR2 0x08
  37. #define RTC_ADDR3 0x0c
  38. #define RTC_REG4 0x10
  39. #define RTC_REG4_STATIC_VALUE GENMASK(7, 0)
  40. /* rtc registers accessed via rtc-serial interface */
  41. #define RTC_COUNTER (0)
  42. #define RTC_SEC_ADJ (2)
  43. #define RTC_REGMEM_0 (4)
  44. #define RTC_REGMEM_1 (5)
  45. #define RTC_REGMEM_2 (6)
  46. #define RTC_REGMEM_3 (7)
  47. #define RTC_ADDR_BITS (3) /* number of address bits to send */
  48. #define RTC_DATA_BITS (32) /* number of data bits to tx/rx */
  49. #define MESON_STATIC_BIAS_CUR (0x5 << 1)
  50. #define MESON_STATIC_VOLTAGE (0x3 << 11)
  51. #define MESON_STATIC_DEFAULT (MESON_STATIC_BIAS_CUR | MESON_STATIC_VOLTAGE)
  52. struct meson_rtc {
  53. struct rtc_device *rtc; /* rtc device we created */
  54. struct device *dev; /* device we bound from */
  55. struct reset_control *reset; /* reset source */
  56. struct regulator *vdd; /* voltage input */
  57. struct regmap *peripheral; /* peripheral registers */
  58. struct regmap *serial; /* serial registers */
  59. };
  60. static const struct regmap_config meson_rtc_peripheral_regmap_config = {
  61. .name = "peripheral-registers",
  62. .reg_bits = 8,
  63. .val_bits = 32,
  64. .reg_stride = 4,
  65. .max_register = RTC_REG4,
  66. .fast_io = true,
  67. };
  68. /* RTC front-end serialiser controls */
  69. static void meson_rtc_sclk_pulse(struct meson_rtc *rtc)
  70. {
  71. udelay(5);
  72. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0);
  73. udelay(5);
  74. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK,
  75. RTC_ADDR0_LINE_SCLK);
  76. }
  77. static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit)
  78. {
  79. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI,
  80. bit ? RTC_ADDR0_LINE_SDI : 0);
  81. meson_rtc_sclk_pulse(rtc);
  82. }
  83. static void meson_rtc_send_bits(struct meson_rtc *rtc, u32 data,
  84. unsigned int nr)
  85. {
  86. u32 bit = 1 << (nr - 1);
  87. while (bit) {
  88. meson_rtc_send_bit(rtc, data & bit);
  89. bit >>= 1;
  90. }
  91. }
  92. static void meson_rtc_set_dir(struct meson_rtc *rtc, u32 mode)
  93. {
  94. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0);
  95. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
  96. meson_rtc_send_bit(rtc, mode);
  97. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
  98. }
  99. static u32 meson_rtc_get_data(struct meson_rtc *rtc)
  100. {
  101. u32 tmp, val = 0;
  102. int bit;
  103. for (bit = 0; bit < RTC_DATA_BITS; bit++) {
  104. meson_rtc_sclk_pulse(rtc);
  105. val <<= 1;
  106. regmap_read(rtc->peripheral, RTC_ADDR1, &tmp);
  107. val |= tmp & RTC_ADDR1_SDO;
  108. }
  109. return val;
  110. }
  111. static int meson_rtc_get_bus(struct meson_rtc *rtc)
  112. {
  113. int ret, retries;
  114. u32 val;
  115. /* prepare bus for transfers, set all lines low */
  116. val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK;
  117. regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0);
  118. for (retries = 0; retries < 3; retries++) {
  119. /* wait for the bus to be ready */
  120. if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val,
  121. val & RTC_ADDR1_S_READY, 10,
  122. 10000))
  123. return 0;
  124. dev_warn(rtc->dev, "failed to get bus, resetting RTC\n");
  125. ret = reset_control_reset(rtc->reset);
  126. if (ret)
  127. return ret;
  128. }
  129. dev_err(rtc->dev, "bus is not ready\n");
  130. return -ETIMEDOUT;
  131. }
  132. static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg,
  133. unsigned int *data)
  134. {
  135. struct meson_rtc *rtc = context;
  136. int ret;
  137. ret = meson_rtc_get_bus(rtc);
  138. if (ret)
  139. return ret;
  140. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
  141. RTC_ADDR0_LINE_SEN);
  142. meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
  143. meson_rtc_set_dir(rtc, 0);
  144. *data = meson_rtc_get_data(rtc);
  145. return 0;
  146. }
  147. static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg,
  148. unsigned int data)
  149. {
  150. struct meson_rtc *rtc = context;
  151. int ret;
  152. ret = meson_rtc_get_bus(rtc);
  153. if (ret)
  154. return ret;
  155. regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
  156. RTC_ADDR0_LINE_SEN);
  157. meson_rtc_send_bits(rtc, data, RTC_DATA_BITS);
  158. meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
  159. meson_rtc_set_dir(rtc, 1);
  160. return 0;
  161. }
  162. static const struct regmap_bus meson_rtc_serial_bus = {
  163. .reg_read = meson_rtc_serial_bus_reg_read,
  164. .reg_write = meson_rtc_serial_bus_reg_write,
  165. };
  166. static const struct regmap_config meson_rtc_serial_regmap_config = {
  167. .name = "serial-registers",
  168. .reg_bits = 4,
  169. .reg_stride = 1,
  170. .val_bits = 32,
  171. .max_register = RTC_REGMEM_3,
  172. .fast_io = false,
  173. };
  174. static int meson_rtc_write_static(struct meson_rtc *rtc, u32 data)
  175. {
  176. u32 tmp;
  177. regmap_write(rtc->peripheral, RTC_REG4,
  178. FIELD_PREP(RTC_REG4_STATIC_VALUE, (data >> 8)));
  179. /* write the static value and start the auto serializer */
  180. tmp = FIELD_PREP(RTC_ADDR0_DATA, (data & 0xff)) | RTC_ADDR0_START_SER;
  181. regmap_update_bits(rtc->peripheral, RTC_ADDR0,
  182. RTC_ADDR0_DATA | RTC_ADDR0_START_SER, tmp);
  183. /* wait for the auto serializer to complete */
  184. return regmap_read_poll_timeout(rtc->peripheral, RTC_REG4, tmp,
  185. !(tmp & RTC_ADDR0_WAIT_SER), 10,
  186. 10000);
  187. }
  188. /* RTC interface layer functions */
  189. static int meson_rtc_gettime(struct device *dev, struct rtc_time *tm)
  190. {
  191. struct meson_rtc *rtc = dev_get_drvdata(dev);
  192. u32 time;
  193. int ret;
  194. ret = regmap_read(rtc->serial, RTC_COUNTER, &time);
  195. if (!ret)
  196. rtc_time64_to_tm(time, tm);
  197. return ret;
  198. }
  199. static int meson_rtc_settime(struct device *dev, struct rtc_time *tm)
  200. {
  201. struct meson_rtc *rtc = dev_get_drvdata(dev);
  202. return regmap_write(rtc->serial, RTC_COUNTER, rtc_tm_to_time64(tm));
  203. }
  204. static const struct rtc_class_ops meson_rtc_ops = {
  205. .read_time = meson_rtc_gettime,
  206. .set_time = meson_rtc_settime,
  207. };
  208. /* NVMEM interface layer functions */
  209. static int meson_rtc_regmem_read(void *context, unsigned int offset,
  210. void *buf, size_t bytes)
  211. {
  212. struct meson_rtc *rtc = context;
  213. unsigned int read_offset, read_size;
  214. read_offset = RTC_REGMEM_0 + (offset / 4);
  215. read_size = bytes / 4;
  216. return regmap_bulk_read(rtc->serial, read_offset, buf, read_size);
  217. }
  218. static int meson_rtc_regmem_write(void *context, unsigned int offset,
  219. void *buf, size_t bytes)
  220. {
  221. struct meson_rtc *rtc = context;
  222. unsigned int write_offset, write_size;
  223. write_offset = RTC_REGMEM_0 + (offset / 4);
  224. write_size = bytes / 4;
  225. return regmap_bulk_write(rtc->serial, write_offset, buf, write_size);
  226. }
  227. static int meson_rtc_probe(struct platform_device *pdev)
  228. {
  229. struct nvmem_config meson_rtc_nvmem_config = {
  230. .name = "meson-rtc-regmem",
  231. .type = NVMEM_TYPE_BATTERY_BACKED,
  232. .word_size = 4,
  233. .stride = 4,
  234. .size = 4 * 4,
  235. .reg_read = meson_rtc_regmem_read,
  236. .reg_write = meson_rtc_regmem_write,
  237. };
  238. struct device *dev = &pdev->dev;
  239. struct meson_rtc *rtc;
  240. void __iomem *base;
  241. int ret;
  242. u32 tm;
  243. rtc = devm_kzalloc(dev, sizeof(struct meson_rtc), GFP_KERNEL);
  244. if (!rtc)
  245. return -ENOMEM;
  246. rtc->rtc = devm_rtc_allocate_device(dev);
  247. if (IS_ERR(rtc->rtc))
  248. return PTR_ERR(rtc->rtc);
  249. platform_set_drvdata(pdev, rtc);
  250. rtc->dev = dev;
  251. rtc->rtc->ops = &meson_rtc_ops;
  252. rtc->rtc->range_max = U32_MAX;
  253. base = devm_platform_ioremap_resource(pdev, 0);
  254. if (IS_ERR(base))
  255. return PTR_ERR(base);
  256. rtc->peripheral = devm_regmap_init_mmio(dev, base,
  257. &meson_rtc_peripheral_regmap_config);
  258. if (IS_ERR(rtc->peripheral)) {
  259. dev_err(dev, "failed to create peripheral regmap\n");
  260. return PTR_ERR(rtc->peripheral);
  261. }
  262. rtc->reset = devm_reset_control_get(dev, NULL);
  263. if (IS_ERR(rtc->reset)) {
  264. dev_err(dev, "missing reset line\n");
  265. return PTR_ERR(rtc->reset);
  266. }
  267. rtc->vdd = devm_regulator_get(dev, "vdd");
  268. if (IS_ERR(rtc->vdd)) {
  269. dev_err(dev, "failed to get the vdd-supply\n");
  270. return PTR_ERR(rtc->vdd);
  271. }
  272. ret = regulator_enable(rtc->vdd);
  273. if (ret) {
  274. dev_err(dev, "failed to enable vdd-supply\n");
  275. return ret;
  276. }
  277. ret = meson_rtc_write_static(rtc, MESON_STATIC_DEFAULT);
  278. if (ret) {
  279. dev_err(dev, "failed to set static values\n");
  280. goto out_disable_vdd;
  281. }
  282. rtc->serial = devm_regmap_init(dev, &meson_rtc_serial_bus, rtc,
  283. &meson_rtc_serial_regmap_config);
  284. if (IS_ERR(rtc->serial)) {
  285. dev_err(dev, "failed to create serial regmap\n");
  286. ret = PTR_ERR(rtc->serial);
  287. goto out_disable_vdd;
  288. }
  289. /*
  290. * check if we can read RTC counter, if not then the RTC is probably
  291. * not functional. If it isn't probably best to not bind.
  292. */
  293. ret = regmap_read(rtc->serial, RTC_COUNTER, &tm);
  294. if (ret) {
  295. dev_err(dev, "cannot read RTC counter, RTC not functional\n");
  296. goto out_disable_vdd;
  297. }
  298. meson_rtc_nvmem_config.priv = rtc;
  299. ret = rtc_nvmem_register(rtc->rtc, &meson_rtc_nvmem_config);
  300. if (ret)
  301. goto out_disable_vdd;
  302. ret = rtc_register_device(rtc->rtc);
  303. if (ret)
  304. goto out_disable_vdd;
  305. return 0;
  306. out_disable_vdd:
  307. regulator_disable(rtc->vdd);
  308. return ret;
  309. }
  310. static const struct of_device_id meson_rtc_dt_match[] = {
  311. { .compatible = "amlogic,meson6-rtc", },
  312. { .compatible = "amlogic,meson8-rtc", },
  313. { .compatible = "amlogic,meson8b-rtc", },
  314. { .compatible = "amlogic,meson8m2-rtc", },
  315. { },
  316. };
  317. MODULE_DEVICE_TABLE(of, meson_rtc_dt_match);
  318. static struct platform_driver meson_rtc_driver = {
  319. .probe = meson_rtc_probe,
  320. .driver = {
  321. .name = "meson-rtc",
  322. .of_match_table = of_match_ptr(meson_rtc_dt_match),
  323. },
  324. };
  325. module_platform_driver(meson_rtc_driver);
  326. MODULE_DESCRIPTION("Amlogic Meson RTC Driver");
  327. MODULE_AUTHOR("Ben Dooks <ben.doosk@codethink.co.uk>");
  328. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  329. MODULE_LICENSE("GPL v2");
  330. MODULE_ALIAS("platform:meson-rtc");