rtc-mcp795.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI Driver for Microchip MCP795 RTC
  4. *
  5. * Copyright (C) Josef Gajdusek <atx@atx.name>
  6. *
  7. * based on other Linux RTC drivers
  8. *
  9. * Device datasheet:
  10. * https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/device.h>
  15. #include <linux/printk.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/rtc.h>
  18. #include <linux/of.h>
  19. #include <linux/bcd.h>
  20. #include <linux/delay.h>
  21. /* MCP795 Instructions, see datasheet table 3-1 */
  22. #define MCP795_EEREAD 0x03
  23. #define MCP795_EEWRITE 0x02
  24. #define MCP795_EEWRDI 0x04
  25. #define MCP795_EEWREN 0x06
  26. #define MCP795_SRREAD 0x05
  27. #define MCP795_SRWRITE 0x01
  28. #define MCP795_READ 0x13
  29. #define MCP795_WRITE 0x12
  30. #define MCP795_UNLOCK 0x14
  31. #define MCP795_IDWRITE 0x32
  32. #define MCP795_IDREAD 0x33
  33. #define MCP795_CLRWDT 0x44
  34. #define MCP795_CLRRAM 0x54
  35. /* MCP795 RTCC registers, see datasheet table 4-1 */
  36. #define MCP795_REG_SECONDS 0x01
  37. #define MCP795_REG_DAY 0x04
  38. #define MCP795_REG_MONTH 0x06
  39. #define MCP795_REG_CONTROL 0x08
  40. #define MCP795_REG_ALM0_SECONDS 0x0C
  41. #define MCP795_REG_ALM0_DAY 0x0F
  42. #define MCP795_ST_BIT BIT(7)
  43. #define MCP795_24_BIT BIT(6)
  44. #define MCP795_LP_BIT BIT(5)
  45. #define MCP795_EXTOSC_BIT BIT(3)
  46. #define MCP795_OSCON_BIT BIT(5)
  47. #define MCP795_ALM0_BIT BIT(4)
  48. #define MCP795_ALM1_BIT BIT(5)
  49. #define MCP795_ALM0IF_BIT BIT(3)
  50. #define MCP795_ALM0C0_BIT BIT(4)
  51. #define MCP795_ALM0C1_BIT BIT(5)
  52. #define MCP795_ALM0C2_BIT BIT(6)
  53. #define SEC_PER_DAY (24 * 60 * 60)
  54. static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
  55. {
  56. struct spi_device *spi = to_spi_device(dev);
  57. int ret;
  58. u8 tx[2];
  59. tx[0] = MCP795_READ;
  60. tx[1] = addr;
  61. ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
  62. if (ret)
  63. dev_err(dev, "Failed reading %d bytes from address %x.\n",
  64. count, addr);
  65. return ret;
  66. }
  67. static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
  68. {
  69. struct spi_device *spi = to_spi_device(dev);
  70. int ret;
  71. u8 tx[257];
  72. tx[0] = MCP795_WRITE;
  73. tx[1] = addr;
  74. memcpy(&tx[2], data, count);
  75. ret = spi_write(spi, tx, 2 + count);
  76. if (ret)
  77. dev_err(dev, "Failed to write %d bytes to address %x.\n",
  78. count, addr);
  79. return ret;
  80. }
  81. static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
  82. {
  83. int ret;
  84. u8 tmp;
  85. ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
  86. if (ret)
  87. return ret;
  88. if ((tmp & mask) != state) {
  89. tmp = (tmp & ~mask) | state;
  90. ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
  91. }
  92. return ret;
  93. }
  94. static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
  95. {
  96. int retries = 5;
  97. int ret;
  98. u8 data;
  99. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
  100. if (ret)
  101. return ret;
  102. ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
  103. if (ret)
  104. return ret;
  105. *extosc = !!(data & MCP795_EXTOSC_BIT);
  106. ret = mcp795_rtcc_set_bits(
  107. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
  108. if (ret)
  109. return ret;
  110. /* wait for the OSCON bit to clear */
  111. do {
  112. usleep_range(700, 800);
  113. ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
  114. if (ret)
  115. break;
  116. if (!(data & MCP795_OSCON_BIT))
  117. break;
  118. } while (--retries);
  119. return !retries ? -EIO : ret;
  120. }
  121. static int mcp795_start_oscillator(struct device *dev, bool *extosc)
  122. {
  123. if (extosc) {
  124. u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
  125. int ret;
  126. ret = mcp795_rtcc_set_bits(
  127. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
  128. if (ret)
  129. return ret;
  130. }
  131. return mcp795_rtcc_set_bits(
  132. dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
  133. }
  134. /* Enable or disable Alarm 0 in RTC */
  135. static int mcp795_update_alarm(struct device *dev, bool enable)
  136. {
  137. int ret;
  138. dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
  139. if (enable) {
  140. /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
  141. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
  142. MCP795_ALM0IF_BIT, 0);
  143. if (ret)
  144. return ret;
  145. /* enable alarm 0 */
  146. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
  147. MCP795_ALM0_BIT, MCP795_ALM0_BIT);
  148. } else {
  149. /* disable alarm 0 and alarm 1 */
  150. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
  151. MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
  152. }
  153. return ret;
  154. }
  155. static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
  156. {
  157. int ret;
  158. u8 data[7];
  159. bool extosc;
  160. /* Stop RTC and store current value of EXTOSC bit */
  161. ret = mcp795_stop_oscillator(dev, &extosc);
  162. if (ret)
  163. return ret;
  164. /* Read first, so we can leave config bits untouched */
  165. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  166. if (ret)
  167. return ret;
  168. data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
  169. data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
  170. data[2] = bin2bcd(tim->tm_hour);
  171. data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
  172. data[4] = bin2bcd(tim->tm_mday);
  173. data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
  174. if (tim->tm_year > 100)
  175. tim->tm_year -= 100;
  176. data[6] = bin2bcd(tim->tm_year);
  177. /* Always write the date and month using a separate Write command.
  178. * This is a workaround for a know silicon issue that some combinations
  179. * of date and month values may result in the date being reset to 1.
  180. */
  181. ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
  182. if (ret)
  183. return ret;
  184. ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
  185. if (ret)
  186. return ret;
  187. /* Start back RTC and restore previous value of EXTOSC bit.
  188. * There is no need to clear EXTOSC bit when the previous value was 0
  189. * because it was already cleared when stopping the RTC oscillator.
  190. */
  191. ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
  192. if (ret)
  193. return ret;
  194. dev_dbg(dev, "Set mcp795: %ptR\n", tim);
  195. return 0;
  196. }
  197. static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
  198. {
  199. int ret;
  200. u8 data[7];
  201. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  202. if (ret)
  203. return ret;
  204. tim->tm_sec = bcd2bin(data[0] & 0x7F);
  205. tim->tm_min = bcd2bin(data[1] & 0x7F);
  206. tim->tm_hour = bcd2bin(data[2] & 0x3F);
  207. tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
  208. tim->tm_mday = bcd2bin(data[4] & 0x3F);
  209. tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
  210. tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
  211. dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
  212. return 0;
  213. }
  214. static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  215. {
  216. struct rtc_time now_tm;
  217. time64_t now;
  218. time64_t later;
  219. u8 tmp[6];
  220. int ret;
  221. /* Read current time from RTC hardware */
  222. ret = mcp795_read_time(dev, &now_tm);
  223. if (ret)
  224. return ret;
  225. /* Get the number of seconds since 1970 */
  226. now = rtc_tm_to_time64(&now_tm);
  227. later = rtc_tm_to_time64(&alm->time);
  228. if (later <= now)
  229. return -EINVAL;
  230. /* make sure alarm fires within the next one year */
  231. if ((later - now) >=
  232. (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
  233. return -EDOM;
  234. /* disable alarm */
  235. ret = mcp795_update_alarm(dev, false);
  236. if (ret)
  237. return ret;
  238. /* Read registers, so we can leave configuration bits untouched */
  239. ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
  240. if (ret)
  241. return ret;
  242. alm->time.tm_year = -1;
  243. alm->time.tm_isdst = -1;
  244. alm->time.tm_yday = -1;
  245. tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
  246. tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
  247. tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
  248. tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
  249. /* set alarm match: seconds, minutes, hour, day, date and month */
  250. tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
  251. tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
  252. tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
  253. ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
  254. if (ret)
  255. return ret;
  256. /* enable alarm if requested */
  257. if (alm->enabled) {
  258. ret = mcp795_update_alarm(dev, true);
  259. if (ret)
  260. return ret;
  261. dev_dbg(dev, "Alarm IRQ armed\n");
  262. }
  263. dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
  264. &alm->time, alm->time.tm_wday, &alm->time);
  265. return 0;
  266. }
  267. static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  268. {
  269. u8 data[6];
  270. int ret;
  271. ret = mcp795_rtcc_read(
  272. dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
  273. if (ret)
  274. return ret;
  275. alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
  276. alm->time.tm_min = bcd2bin(data[1] & 0x7F);
  277. alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
  278. alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
  279. alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
  280. alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
  281. alm->time.tm_year = -1;
  282. alm->time.tm_isdst = -1;
  283. alm->time.tm_yday = -1;
  284. dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
  285. &alm->time, alm->time.tm_wday, &alm->time);
  286. return 0;
  287. }
  288. static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
  289. {
  290. return mcp795_update_alarm(dev, !!enabled);
  291. }
  292. static irqreturn_t mcp795_irq(int irq, void *data)
  293. {
  294. struct spi_device *spi = data;
  295. struct rtc_device *rtc = spi_get_drvdata(spi);
  296. struct mutex *lock = &rtc->ops_lock;
  297. int ret;
  298. mutex_lock(lock);
  299. /* Disable alarm.
  300. * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
  301. * because it is done every time when alarm is enabled.
  302. */
  303. ret = mcp795_update_alarm(&spi->dev, false);
  304. if (ret)
  305. dev_err(&spi->dev,
  306. "Failed to disable alarm in IRQ (ret=%d)\n", ret);
  307. rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
  308. mutex_unlock(lock);
  309. return IRQ_HANDLED;
  310. }
  311. static const struct rtc_class_ops mcp795_rtc_ops = {
  312. .read_time = mcp795_read_time,
  313. .set_time = mcp795_set_time,
  314. .read_alarm = mcp795_read_alarm,
  315. .set_alarm = mcp795_set_alarm,
  316. .alarm_irq_enable = mcp795_alarm_irq_enable
  317. };
  318. static int mcp795_probe(struct spi_device *spi)
  319. {
  320. struct rtc_device *rtc;
  321. int ret;
  322. spi->mode = SPI_MODE_0;
  323. spi->bits_per_word = 8;
  324. ret = spi_setup(spi);
  325. if (ret) {
  326. dev_err(&spi->dev, "Unable to setup SPI\n");
  327. return ret;
  328. }
  329. /* Start the oscillator but don't set the value of EXTOSC bit */
  330. mcp795_start_oscillator(&spi->dev, NULL);
  331. /* Clear the 12 hour mode flag*/
  332. mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
  333. rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
  334. &mcp795_rtc_ops, THIS_MODULE);
  335. if (IS_ERR(rtc))
  336. return PTR_ERR(rtc);
  337. spi_set_drvdata(spi, rtc);
  338. if (spi->irq > 0) {
  339. dev_dbg(&spi->dev, "Alarm support enabled\n");
  340. /* Clear any pending alarm (ALM0IF bit) before requesting
  341. * the interrupt.
  342. */
  343. mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
  344. MCP795_ALM0IF_BIT, 0);
  345. ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
  346. mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  347. dev_name(&rtc->dev), spi);
  348. if (ret)
  349. dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
  350. spi->irq, ret);
  351. else
  352. device_init_wakeup(&spi->dev, true);
  353. }
  354. return 0;
  355. }
  356. #ifdef CONFIG_OF
  357. static const struct of_device_id mcp795_of_match[] = {
  358. { .compatible = "maxim,mcp795" },
  359. { }
  360. };
  361. MODULE_DEVICE_TABLE(of, mcp795_of_match);
  362. #endif
  363. static struct spi_driver mcp795_driver = {
  364. .driver = {
  365. .name = "rtc-mcp795",
  366. .of_match_table = of_match_ptr(mcp795_of_match),
  367. },
  368. .probe = mcp795_probe,
  369. };
  370. module_spi_driver(mcp795_driver);
  371. MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
  372. MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
  373. MODULE_LICENSE("GPL");
  374. MODULE_ALIAS("spi:mcp795");