rtc-max77686.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // RTC driver for Maxim MAX77686 and MAX77802
  4. //
  5. // Copyright (C) 2012 Samsung Electronics Co.Ltd
  6. //
  7. // based on rtc-max8997.c
  8. #include <linux/i2c.h>
  9. #include <linux/slab.h>
  10. #include <linux/rtc.h>
  11. #include <linux/delay.h>
  12. #include <linux/mutex.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/mfd/max77686-private.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/regmap.h>
  18. #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
  19. #define MAX77620_I2C_ADDR_RTC 0x68
  20. #define MAX77686_INVALID_I2C_ADDR (-1)
  21. /* Define non existing register */
  22. #define MAX77686_INVALID_REG (-1)
  23. /* RTC Control Register */
  24. #define BCD_EN_SHIFT 0
  25. #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
  26. #define MODEL24_SHIFT 1
  27. #define MODEL24_MASK BIT(MODEL24_SHIFT)
  28. /* RTC Update Register1 */
  29. #define RTC_UDR_SHIFT 0
  30. #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
  31. #define RTC_RBUDR_SHIFT 4
  32. #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
  33. /* RTC Hour register */
  34. #define HOUR_PM_SHIFT 6
  35. #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT)
  36. /* RTC Alarm Enable */
  37. #define ALARM_ENABLE_SHIFT 7
  38. #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
  39. #define REG_RTC_NONE 0xdeadbeef
  40. /*
  41. * MAX77802 has separate register (RTCAE1) for alarm enable instead
  42. * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
  43. * as in done in MAX77686.
  44. */
  45. #define MAX77802_ALARM_ENABLE_VALUE 0x77
  46. enum {
  47. RTC_SEC = 0,
  48. RTC_MIN,
  49. RTC_HOUR,
  50. RTC_WEEKDAY,
  51. RTC_MONTH,
  52. RTC_YEAR,
  53. RTC_DATE,
  54. RTC_NR_TIME
  55. };
  56. struct max77686_rtc_driver_data {
  57. /* Minimum usecs needed for a RTC update */
  58. unsigned long delay;
  59. /* Mask used to read RTC registers value */
  60. u8 mask;
  61. /* Registers offset to I2C addresses map */
  62. const unsigned int *map;
  63. /* Has a separate alarm enable register? */
  64. bool alarm_enable_reg;
  65. /* I2C address for RTC block */
  66. int rtc_i2c_addr;
  67. /* RTC interrupt via platform resource */
  68. bool rtc_irq_from_platform;
  69. /* Pending alarm status register */
  70. int alarm_pending_status_reg;
  71. /* RTC IRQ CHIP for regmap */
  72. const struct regmap_irq_chip *rtc_irq_chip;
  73. /* regmap configuration for the chip */
  74. const struct regmap_config *regmap_config;
  75. };
  76. struct max77686_rtc_info {
  77. struct device *dev;
  78. struct i2c_client *rtc;
  79. struct rtc_device *rtc_dev;
  80. struct mutex lock;
  81. struct regmap *regmap;
  82. struct regmap *rtc_regmap;
  83. const struct max77686_rtc_driver_data *drv_data;
  84. struct regmap_irq_chip_data *rtc_irq_data;
  85. int rtc_irq;
  86. int virq;
  87. int rtc_24hr_mode;
  88. };
  89. enum MAX77686_RTC_OP {
  90. MAX77686_RTC_WRITE,
  91. MAX77686_RTC_READ,
  92. };
  93. /* These are not registers but just offsets that are mapped to addresses */
  94. enum max77686_rtc_reg_offset {
  95. REG_RTC_CONTROLM = 0,
  96. REG_RTC_CONTROL,
  97. REG_RTC_UPDATE0,
  98. REG_WTSR_SMPL_CNTL,
  99. REG_RTC_SEC,
  100. REG_RTC_MIN,
  101. REG_RTC_HOUR,
  102. REG_RTC_WEEKDAY,
  103. REG_RTC_MONTH,
  104. REG_RTC_YEAR,
  105. REG_RTC_DATE,
  106. REG_ALARM1_SEC,
  107. REG_ALARM1_MIN,
  108. REG_ALARM1_HOUR,
  109. REG_ALARM1_WEEKDAY,
  110. REG_ALARM1_MONTH,
  111. REG_ALARM1_YEAR,
  112. REG_ALARM1_DATE,
  113. REG_ALARM2_SEC,
  114. REG_ALARM2_MIN,
  115. REG_ALARM2_HOUR,
  116. REG_ALARM2_WEEKDAY,
  117. REG_ALARM2_MONTH,
  118. REG_ALARM2_YEAR,
  119. REG_ALARM2_DATE,
  120. REG_RTC_AE1,
  121. REG_RTC_END,
  122. };
  123. /* Maps RTC registers offset to the MAX77686 register addresses */
  124. static const unsigned int max77686_map[REG_RTC_END] = {
  125. [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
  126. [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
  127. [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
  128. [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
  129. [REG_RTC_SEC] = MAX77686_RTC_SEC,
  130. [REG_RTC_MIN] = MAX77686_RTC_MIN,
  131. [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
  132. [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
  133. [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
  134. [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
  135. [REG_RTC_DATE] = MAX77686_RTC_DATE,
  136. [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
  137. [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
  138. [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
  139. [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
  140. [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
  141. [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
  142. [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
  143. [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
  144. [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
  145. [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
  146. [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
  147. [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
  148. [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
  149. [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
  150. [REG_RTC_AE1] = REG_RTC_NONE,
  151. };
  152. static const struct regmap_irq max77686_rtc_irqs[] = {
  153. /* RTC interrupts */
  154. REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
  155. REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
  156. REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
  157. REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
  158. REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
  159. REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
  160. };
  161. static const struct regmap_irq_chip max77686_rtc_irq_chip = {
  162. .name = "max77686-rtc",
  163. .status_base = MAX77686_RTC_INT,
  164. .mask_base = MAX77686_RTC_INTM,
  165. .num_regs = 1,
  166. .irqs = max77686_rtc_irqs,
  167. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  168. };
  169. static const struct regmap_config max77686_rtc_regmap_config = {
  170. .reg_bits = 8,
  171. .val_bits = 8,
  172. };
  173. static const struct max77686_rtc_driver_data max77686_drv_data = {
  174. .delay = 16000,
  175. .mask = 0x7f,
  176. .map = max77686_map,
  177. .alarm_enable_reg = false,
  178. .rtc_irq_from_platform = false,
  179. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  180. .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
  181. .rtc_irq_chip = &max77686_rtc_irq_chip,
  182. .regmap_config = &max77686_rtc_regmap_config,
  183. };
  184. static const struct regmap_config max77620_rtc_regmap_config = {
  185. .reg_bits = 8,
  186. .val_bits = 8,
  187. .use_single_write = true,
  188. };
  189. static const struct max77686_rtc_driver_data max77620_drv_data = {
  190. .delay = 16000,
  191. .mask = 0x7f,
  192. .map = max77686_map,
  193. .alarm_enable_reg = false,
  194. .rtc_irq_from_platform = true,
  195. .alarm_pending_status_reg = MAX77686_INVALID_REG,
  196. .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
  197. .rtc_irq_chip = &max77686_rtc_irq_chip,
  198. .regmap_config = &max77620_rtc_regmap_config,
  199. };
  200. static const unsigned int max77802_map[REG_RTC_END] = {
  201. [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
  202. [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
  203. [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
  204. [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
  205. [REG_RTC_SEC] = MAX77802_RTC_SEC,
  206. [REG_RTC_MIN] = MAX77802_RTC_MIN,
  207. [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
  208. [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
  209. [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
  210. [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
  211. [REG_RTC_DATE] = MAX77802_RTC_DATE,
  212. [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
  213. [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
  214. [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
  215. [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
  216. [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
  217. [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
  218. [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
  219. [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
  220. [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
  221. [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
  222. [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
  223. [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
  224. [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
  225. [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
  226. [REG_RTC_AE1] = MAX77802_RTC_AE1,
  227. };
  228. static const struct regmap_irq_chip max77802_rtc_irq_chip = {
  229. .name = "max77802-rtc",
  230. .status_base = MAX77802_RTC_INT,
  231. .mask_base = MAX77802_RTC_INTM,
  232. .num_regs = 1,
  233. .irqs = max77686_rtc_irqs, /* same masks as 77686 */
  234. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  235. };
  236. static const struct max77686_rtc_driver_data max77802_drv_data = {
  237. .delay = 200,
  238. .mask = 0xff,
  239. .map = max77802_map,
  240. .alarm_enable_reg = true,
  241. .rtc_irq_from_platform = false,
  242. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  243. .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
  244. .rtc_irq_chip = &max77802_rtc_irq_chip,
  245. };
  246. static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
  247. struct max77686_rtc_info *info)
  248. {
  249. u8 mask = info->drv_data->mask;
  250. tm->tm_sec = data[RTC_SEC] & mask;
  251. tm->tm_min = data[RTC_MIN] & mask;
  252. if (info->rtc_24hr_mode) {
  253. tm->tm_hour = data[RTC_HOUR] & 0x1f;
  254. } else {
  255. tm->tm_hour = data[RTC_HOUR] & 0x0f;
  256. if (data[RTC_HOUR] & HOUR_PM_MASK)
  257. tm->tm_hour += 12;
  258. }
  259. /* Only a single bit is set in data[], so fls() would be equivalent */
  260. tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
  261. tm->tm_mday = data[RTC_DATE] & 0x1f;
  262. tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
  263. tm->tm_year = data[RTC_YEAR] & mask;
  264. tm->tm_yday = 0;
  265. tm->tm_isdst = 0;
  266. /*
  267. * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
  268. * year values are just 0..99 so add 100 to support up to 2099.
  269. */
  270. if (!info->drv_data->alarm_enable_reg)
  271. tm->tm_year += 100;
  272. }
  273. static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
  274. struct max77686_rtc_info *info)
  275. {
  276. data[RTC_SEC] = tm->tm_sec;
  277. data[RTC_MIN] = tm->tm_min;
  278. data[RTC_HOUR] = tm->tm_hour;
  279. data[RTC_WEEKDAY] = 1 << tm->tm_wday;
  280. data[RTC_DATE] = tm->tm_mday;
  281. data[RTC_MONTH] = tm->tm_mon + 1;
  282. if (info->drv_data->alarm_enable_reg) {
  283. data[RTC_YEAR] = tm->tm_year;
  284. return 0;
  285. }
  286. data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
  287. if (tm->tm_year < 100) {
  288. dev_err(info->dev, "RTC cannot handle the year %d.\n",
  289. 1900 + tm->tm_year);
  290. return -EINVAL;
  291. }
  292. return 0;
  293. }
  294. static int max77686_rtc_update(struct max77686_rtc_info *info,
  295. enum MAX77686_RTC_OP op)
  296. {
  297. int ret;
  298. unsigned int data;
  299. unsigned long delay = info->drv_data->delay;
  300. if (op == MAX77686_RTC_WRITE)
  301. data = 1 << RTC_UDR_SHIFT;
  302. else
  303. data = 1 << RTC_RBUDR_SHIFT;
  304. ret = regmap_update_bits(info->rtc_regmap,
  305. info->drv_data->map[REG_RTC_UPDATE0],
  306. data, data);
  307. if (ret < 0)
  308. dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
  309. ret, data);
  310. else {
  311. /* Minimum delay required before RTC update. */
  312. usleep_range(delay, delay * 2);
  313. }
  314. return ret;
  315. }
  316. static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
  317. {
  318. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  319. u8 data[RTC_NR_TIME];
  320. int ret;
  321. mutex_lock(&info->lock);
  322. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  323. if (ret < 0)
  324. goto out;
  325. ret = regmap_bulk_read(info->rtc_regmap,
  326. info->drv_data->map[REG_RTC_SEC],
  327. data, ARRAY_SIZE(data));
  328. if (ret < 0) {
  329. dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
  330. goto out;
  331. }
  332. max77686_rtc_data_to_tm(data, tm, info);
  333. out:
  334. mutex_unlock(&info->lock);
  335. return ret;
  336. }
  337. static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
  338. {
  339. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  340. u8 data[RTC_NR_TIME];
  341. int ret;
  342. ret = max77686_rtc_tm_to_data(tm, data, info);
  343. if (ret < 0)
  344. return ret;
  345. mutex_lock(&info->lock);
  346. ret = regmap_bulk_write(info->rtc_regmap,
  347. info->drv_data->map[REG_RTC_SEC],
  348. data, ARRAY_SIZE(data));
  349. if (ret < 0) {
  350. dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
  351. goto out;
  352. }
  353. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  354. out:
  355. mutex_unlock(&info->lock);
  356. return ret;
  357. }
  358. static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  359. {
  360. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  361. u8 data[RTC_NR_TIME];
  362. unsigned int val;
  363. const unsigned int *map = info->drv_data->map;
  364. int i, ret;
  365. mutex_lock(&info->lock);
  366. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  367. if (ret < 0)
  368. goto out;
  369. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  370. data, ARRAY_SIZE(data));
  371. if (ret < 0) {
  372. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  373. goto out;
  374. }
  375. max77686_rtc_data_to_tm(data, &alrm->time, info);
  376. alrm->enabled = 0;
  377. if (info->drv_data->alarm_enable_reg) {
  378. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  379. ret = -EINVAL;
  380. dev_err(info->dev,
  381. "alarm enable register not set(%d)\n", ret);
  382. goto out;
  383. }
  384. ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
  385. if (ret < 0) {
  386. dev_err(info->dev,
  387. "fail to read alarm enable(%d)\n", ret);
  388. goto out;
  389. }
  390. if (val)
  391. alrm->enabled = 1;
  392. } else {
  393. for (i = 0; i < ARRAY_SIZE(data); i++) {
  394. if (data[i] & ALARM_ENABLE_MASK) {
  395. alrm->enabled = 1;
  396. break;
  397. }
  398. }
  399. }
  400. alrm->pending = 0;
  401. if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
  402. goto out;
  403. ret = regmap_read(info->regmap,
  404. info->drv_data->alarm_pending_status_reg, &val);
  405. if (ret < 0) {
  406. dev_err(info->dev,
  407. "Fail to read alarm pending status reg(%d)\n", ret);
  408. goto out;
  409. }
  410. if (val & (1 << 4)) /* RTCA1 */
  411. alrm->pending = 1;
  412. out:
  413. mutex_unlock(&info->lock);
  414. return ret;
  415. }
  416. static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
  417. {
  418. u8 data[RTC_NR_TIME];
  419. int ret, i;
  420. struct rtc_time tm;
  421. const unsigned int *map = info->drv_data->map;
  422. if (!mutex_is_locked(&info->lock))
  423. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  424. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  425. if (ret < 0)
  426. goto out;
  427. if (info->drv_data->alarm_enable_reg) {
  428. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  429. ret = -EINVAL;
  430. dev_err(info->dev,
  431. "alarm enable register not set(%d)\n", ret);
  432. goto out;
  433. }
  434. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
  435. } else {
  436. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  437. data, ARRAY_SIZE(data));
  438. if (ret < 0) {
  439. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  440. goto out;
  441. }
  442. max77686_rtc_data_to_tm(data, &tm, info);
  443. for (i = 0; i < ARRAY_SIZE(data); i++)
  444. data[i] &= ~ALARM_ENABLE_MASK;
  445. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  446. data, ARRAY_SIZE(data));
  447. }
  448. if (ret < 0) {
  449. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  450. goto out;
  451. }
  452. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  453. out:
  454. return ret;
  455. }
  456. static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
  457. {
  458. u8 data[RTC_NR_TIME];
  459. int ret;
  460. struct rtc_time tm;
  461. const unsigned int *map = info->drv_data->map;
  462. if (!mutex_is_locked(&info->lock))
  463. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  464. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  465. if (ret < 0)
  466. goto out;
  467. if (info->drv_data->alarm_enable_reg) {
  468. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
  469. MAX77802_ALARM_ENABLE_VALUE);
  470. } else {
  471. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  472. data, ARRAY_SIZE(data));
  473. if (ret < 0) {
  474. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  475. goto out;
  476. }
  477. max77686_rtc_data_to_tm(data, &tm, info);
  478. data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
  479. data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
  480. data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
  481. data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
  482. if (data[RTC_MONTH] & 0xf)
  483. data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
  484. if (data[RTC_YEAR] & info->drv_data->mask)
  485. data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
  486. if (data[RTC_DATE] & 0x1f)
  487. data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
  488. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  489. data, ARRAY_SIZE(data));
  490. }
  491. if (ret < 0) {
  492. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  493. goto out;
  494. }
  495. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  496. out:
  497. return ret;
  498. }
  499. static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  500. {
  501. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  502. u8 data[RTC_NR_TIME];
  503. int ret;
  504. ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
  505. if (ret < 0)
  506. return ret;
  507. mutex_lock(&info->lock);
  508. ret = max77686_rtc_stop_alarm(info);
  509. if (ret < 0)
  510. goto out;
  511. ret = regmap_bulk_write(info->rtc_regmap,
  512. info->drv_data->map[REG_ALARM1_SEC],
  513. data, ARRAY_SIZE(data));
  514. if (ret < 0) {
  515. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  516. goto out;
  517. }
  518. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  519. if (ret < 0)
  520. goto out;
  521. if (alrm->enabled)
  522. ret = max77686_rtc_start_alarm(info);
  523. out:
  524. mutex_unlock(&info->lock);
  525. return ret;
  526. }
  527. static int max77686_rtc_alarm_irq_enable(struct device *dev,
  528. unsigned int enabled)
  529. {
  530. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  531. int ret;
  532. mutex_lock(&info->lock);
  533. if (enabled)
  534. ret = max77686_rtc_start_alarm(info);
  535. else
  536. ret = max77686_rtc_stop_alarm(info);
  537. mutex_unlock(&info->lock);
  538. return ret;
  539. }
  540. static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
  541. {
  542. struct max77686_rtc_info *info = data;
  543. dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
  544. rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
  545. return IRQ_HANDLED;
  546. }
  547. static const struct rtc_class_ops max77686_rtc_ops = {
  548. .read_time = max77686_rtc_read_time,
  549. .set_time = max77686_rtc_set_time,
  550. .read_alarm = max77686_rtc_read_alarm,
  551. .set_alarm = max77686_rtc_set_alarm,
  552. .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
  553. };
  554. static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
  555. {
  556. u8 data[2];
  557. int ret;
  558. /* Set RTC control register : Binary mode, 24hour mdoe */
  559. data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  560. data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  561. info->rtc_24hr_mode = 1;
  562. ret = regmap_bulk_write(info->rtc_regmap,
  563. info->drv_data->map[REG_RTC_CONTROLM],
  564. data, ARRAY_SIZE(data));
  565. if (ret < 0) {
  566. dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
  567. return ret;
  568. }
  569. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  570. return ret;
  571. }
  572. static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
  573. {
  574. struct device *parent = info->dev->parent;
  575. struct i2c_client *parent_i2c = to_i2c_client(parent);
  576. int ret;
  577. if (info->drv_data->rtc_irq_from_platform) {
  578. struct platform_device *pdev = to_platform_device(info->dev);
  579. info->rtc_irq = platform_get_irq(pdev, 0);
  580. if (info->rtc_irq < 0)
  581. return info->rtc_irq;
  582. } else {
  583. info->rtc_irq = parent_i2c->irq;
  584. }
  585. info->regmap = dev_get_regmap(parent, NULL);
  586. if (!info->regmap) {
  587. dev_err(info->dev, "Failed to get rtc regmap\n");
  588. return -ENODEV;
  589. }
  590. if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
  591. info->rtc_regmap = info->regmap;
  592. goto add_rtc_irq;
  593. }
  594. info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
  595. info->drv_data->rtc_i2c_addr);
  596. if (IS_ERR(info->rtc)) {
  597. dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
  598. return PTR_ERR(info->rtc);
  599. }
  600. info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
  601. info->drv_data->regmap_config);
  602. if (IS_ERR(info->rtc_regmap)) {
  603. ret = PTR_ERR(info->rtc_regmap);
  604. dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
  605. return ret;
  606. }
  607. add_rtc_irq:
  608. ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
  609. IRQF_ONESHOT | IRQF_SHARED,
  610. 0, info->drv_data->rtc_irq_chip,
  611. &info->rtc_irq_data);
  612. if (ret < 0) {
  613. dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
  614. return ret;
  615. }
  616. return 0;
  617. }
  618. static int max77686_rtc_probe(struct platform_device *pdev)
  619. {
  620. struct max77686_rtc_info *info;
  621. const struct platform_device_id *id = platform_get_device_id(pdev);
  622. int ret;
  623. info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
  624. GFP_KERNEL);
  625. if (!info)
  626. return -ENOMEM;
  627. mutex_init(&info->lock);
  628. info->dev = &pdev->dev;
  629. info->drv_data = (const struct max77686_rtc_driver_data *)
  630. id->driver_data;
  631. ret = max77686_init_rtc_regmap(info);
  632. if (ret < 0)
  633. return ret;
  634. platform_set_drvdata(pdev, info);
  635. ret = max77686_rtc_init_reg(info);
  636. if (ret < 0) {
  637. dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
  638. goto err_rtc;
  639. }
  640. device_init_wakeup(&pdev->dev, 1);
  641. info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
  642. &max77686_rtc_ops, THIS_MODULE);
  643. if (IS_ERR(info->rtc_dev)) {
  644. ret = PTR_ERR(info->rtc_dev);
  645. dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
  646. if (ret == 0)
  647. ret = -EINVAL;
  648. goto err_rtc;
  649. }
  650. info->virq = regmap_irq_get_virq(info->rtc_irq_data,
  651. MAX77686_RTCIRQ_RTCA1);
  652. if (info->virq <= 0) {
  653. ret = -ENXIO;
  654. goto err_rtc;
  655. }
  656. ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
  657. "rtc-alarm1", info);
  658. if (ret < 0) {
  659. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  660. info->virq, ret);
  661. goto err_rtc;
  662. }
  663. return 0;
  664. err_rtc:
  665. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  666. return ret;
  667. }
  668. static int max77686_rtc_remove(struct platform_device *pdev)
  669. {
  670. struct max77686_rtc_info *info = platform_get_drvdata(pdev);
  671. free_irq(info->virq, info);
  672. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  673. return 0;
  674. }
  675. #ifdef CONFIG_PM_SLEEP
  676. static int max77686_rtc_suspend(struct device *dev)
  677. {
  678. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  679. int ret = 0;
  680. if (device_may_wakeup(dev)) {
  681. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  682. ret = enable_irq_wake(info->virq);
  683. }
  684. /*
  685. * If the main IRQ (not virtual) is the parent IRQ, then it must be
  686. * disabled during suspend because if it happens while suspended it
  687. * will be handled before resuming I2C.
  688. *
  689. * Since Main IRQ is shared, all its users should disable it to be sure
  690. * it won't fire while one of them is still suspended.
  691. */
  692. if (!info->drv_data->rtc_irq_from_platform)
  693. disable_irq(info->rtc_irq);
  694. return ret;
  695. }
  696. static int max77686_rtc_resume(struct device *dev)
  697. {
  698. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  699. if (!info->drv_data->rtc_irq_from_platform)
  700. enable_irq(info->rtc_irq);
  701. if (device_may_wakeup(dev)) {
  702. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  703. return disable_irq_wake(info->virq);
  704. }
  705. return 0;
  706. }
  707. #endif
  708. static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
  709. max77686_rtc_suspend, max77686_rtc_resume);
  710. static const struct platform_device_id rtc_id[] = {
  711. { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
  712. { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
  713. { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
  714. {},
  715. };
  716. MODULE_DEVICE_TABLE(platform, rtc_id);
  717. static struct platform_driver max77686_rtc_driver = {
  718. .driver = {
  719. .name = "max77686-rtc",
  720. .pm = &max77686_rtc_pm_ops,
  721. },
  722. .probe = max77686_rtc_probe,
  723. .remove = max77686_rtc_remove,
  724. .id_table = rtc_id,
  725. };
  726. module_platform_driver(max77686_rtc_driver);
  727. MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
  728. MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
  729. MODULE_LICENSE("GPL");