rtc-m48t59.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST M48T59 RTC driver
  4. *
  5. * Copyright (c) 2007 Wind River Systems, Inc.
  6. *
  7. * Author: Mark Zhan <rongkai.zhan@windriver.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/rtc.h>
  16. #include <linux/rtc/m48t59.h>
  17. #include <linux/bcd.h>
  18. #include <linux/slab.h>
  19. #ifndef NO_IRQ
  20. #define NO_IRQ (-1)
  21. #endif
  22. #define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
  23. #define M48T59_WRITE(val, reg) \
  24. (pdata->write_byte(dev, pdata->offset + reg, val))
  25. #define M48T59_SET_BITS(mask, reg) \
  26. M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg))
  27. #define M48T59_CLEAR_BITS(mask, reg) \
  28. M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))
  29. struct m48t59_private {
  30. void __iomem *ioaddr;
  31. int irq;
  32. struct rtc_device *rtc;
  33. spinlock_t lock; /* serialize the NVRAM and RTC access */
  34. };
  35. /*
  36. * This is the generic access method when the chip is memory-mapped
  37. */
  38. static void
  39. m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
  40. {
  41. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  42. writeb(val, m48t59->ioaddr+ofs);
  43. }
  44. static u8
  45. m48t59_mem_readb(struct device *dev, u32 ofs)
  46. {
  47. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  48. return readb(m48t59->ioaddr+ofs);
  49. }
  50. /*
  51. * NOTE: M48T59 only uses BCD mode
  52. */
  53. static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
  54. {
  55. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  56. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  57. unsigned long flags;
  58. u8 val;
  59. spin_lock_irqsave(&m48t59->lock, flags);
  60. /* Issue the READ command */
  61. M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
  62. tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
  63. /* tm_mon is 0-11 */
  64. tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
  65. tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY));
  66. val = M48T59_READ(M48T59_WDAY);
  67. if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
  68. (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
  69. dev_dbg(dev, "Century bit is enabled\n");
  70. tm->tm_year += 100; /* one century */
  71. }
  72. #ifdef CONFIG_SPARC
  73. /* Sun SPARC machines count years since 1968 */
  74. tm->tm_year += 68;
  75. #endif
  76. tm->tm_wday = bcd2bin(val & 0x07);
  77. tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
  78. tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
  79. tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);
  80. /* Clear the READ bit */
  81. M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
  82. spin_unlock_irqrestore(&m48t59->lock, flags);
  83. dev_dbg(dev, "RTC read time %ptR\n", tm);
  84. return 0;
  85. }
  86. static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
  87. {
  88. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  89. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  90. unsigned long flags;
  91. u8 val = 0;
  92. int year = tm->tm_year;
  93. #ifdef CONFIG_SPARC
  94. /* Sun SPARC machines count years since 1968 */
  95. year -= 68;
  96. #endif
  97. dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
  98. year + 1900, tm->tm_mon, tm->tm_mday,
  99. tm->tm_hour, tm->tm_min, tm->tm_sec);
  100. if (year < 0)
  101. return -EINVAL;
  102. spin_lock_irqsave(&m48t59->lock, flags);
  103. /* Issue the WRITE command */
  104. M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
  105. M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
  106. M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
  107. M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
  108. M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
  109. /* tm_mon is 0-11 */
  110. M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
  111. M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);
  112. if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
  113. val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
  114. val |= (bin2bcd(tm->tm_wday) & 0x07);
  115. M48T59_WRITE(val, M48T59_WDAY);
  116. /* Clear the WRITE bit */
  117. M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
  118. spin_unlock_irqrestore(&m48t59->lock, flags);
  119. return 0;
  120. }
  121. /*
  122. * Read alarm time and date in RTC
  123. */
  124. static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
  125. {
  126. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  127. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  128. struct rtc_time *tm = &alrm->time;
  129. unsigned long flags;
  130. u8 val;
  131. /* If no irq, we don't support ALARM */
  132. if (m48t59->irq == NO_IRQ)
  133. return -EIO;
  134. spin_lock_irqsave(&m48t59->lock, flags);
  135. /* Issue the READ command */
  136. M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
  137. tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
  138. #ifdef CONFIG_SPARC
  139. /* Sun SPARC machines count years since 1968 */
  140. tm->tm_year += 68;
  141. #endif
  142. /* tm_mon is 0-11 */
  143. tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
  144. val = M48T59_READ(M48T59_WDAY);
  145. if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
  146. tm->tm_year += 100; /* one century */
  147. tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
  148. tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
  149. tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
  150. tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));
  151. /* Clear the READ bit */
  152. M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
  153. spin_unlock_irqrestore(&m48t59->lock, flags);
  154. dev_dbg(dev, "RTC read alarm time %ptR\n", tm);
  155. return rtc_valid_tm(tm);
  156. }
  157. /*
  158. * Set alarm time and date in RTC
  159. */
  160. static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  161. {
  162. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  163. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  164. struct rtc_time *tm = &alrm->time;
  165. u8 mday, hour, min, sec;
  166. unsigned long flags;
  167. int year = tm->tm_year;
  168. #ifdef CONFIG_SPARC
  169. /* Sun SPARC machines count years since 1968 */
  170. year -= 68;
  171. #endif
  172. /* If no irq, we don't support ALARM */
  173. if (m48t59->irq == NO_IRQ)
  174. return -EIO;
  175. if (year < 0)
  176. return -EINVAL;
  177. /*
  178. * 0xff means "always match"
  179. */
  180. mday = tm->tm_mday;
  181. mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
  182. if (mday == 0xff)
  183. mday = M48T59_READ(M48T59_MDAY);
  184. hour = tm->tm_hour;
  185. hour = (hour < 24) ? bin2bcd(hour) : 0x00;
  186. min = tm->tm_min;
  187. min = (min < 60) ? bin2bcd(min) : 0x00;
  188. sec = tm->tm_sec;
  189. sec = (sec < 60) ? bin2bcd(sec) : 0x00;
  190. spin_lock_irqsave(&m48t59->lock, flags);
  191. /* Issue the WRITE command */
  192. M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
  193. M48T59_WRITE(mday, M48T59_ALARM_DATE);
  194. M48T59_WRITE(hour, M48T59_ALARM_HOUR);
  195. M48T59_WRITE(min, M48T59_ALARM_MIN);
  196. M48T59_WRITE(sec, M48T59_ALARM_SEC);
  197. /* Clear the WRITE bit */
  198. M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
  199. spin_unlock_irqrestore(&m48t59->lock, flags);
  200. dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
  201. year + 1900, tm->tm_mon, tm->tm_mday,
  202. tm->tm_hour, tm->tm_min, tm->tm_sec);
  203. return 0;
  204. }
  205. /*
  206. * Handle commands from user-space
  207. */
  208. static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  209. {
  210. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  211. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  212. unsigned long flags;
  213. spin_lock_irqsave(&m48t59->lock, flags);
  214. if (enabled)
  215. M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
  216. else
  217. M48T59_WRITE(0x00, M48T59_INTR);
  218. spin_unlock_irqrestore(&m48t59->lock, flags);
  219. return 0;
  220. }
  221. static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
  222. {
  223. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  224. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  225. unsigned long flags;
  226. u8 val;
  227. spin_lock_irqsave(&m48t59->lock, flags);
  228. val = M48T59_READ(M48T59_FLAGS);
  229. spin_unlock_irqrestore(&m48t59->lock, flags);
  230. seq_printf(seq, "battery\t\t: %s\n",
  231. (val & M48T59_FLAGS_BF) ? "low" : "normal");
  232. return 0;
  233. }
  234. /*
  235. * IRQ handler for the RTC
  236. */
  237. static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
  238. {
  239. struct device *dev = (struct device *)dev_id;
  240. struct m48t59_plat_data *pdata = dev_get_platdata(dev);
  241. struct m48t59_private *m48t59 = dev_get_drvdata(dev);
  242. u8 event;
  243. spin_lock(&m48t59->lock);
  244. event = M48T59_READ(M48T59_FLAGS);
  245. spin_unlock(&m48t59->lock);
  246. if (event & M48T59_FLAGS_AF) {
  247. rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF));
  248. return IRQ_HANDLED;
  249. }
  250. return IRQ_NONE;
  251. }
  252. static const struct rtc_class_ops m48t59_rtc_ops = {
  253. .read_time = m48t59_rtc_read_time,
  254. .set_time = m48t59_rtc_set_time,
  255. .read_alarm = m48t59_rtc_readalarm,
  256. .set_alarm = m48t59_rtc_setalarm,
  257. .proc = m48t59_rtc_proc,
  258. .alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
  259. };
  260. static const struct rtc_class_ops m48t02_rtc_ops = {
  261. .read_time = m48t59_rtc_read_time,
  262. .set_time = m48t59_rtc_set_time,
  263. };
  264. static int m48t59_nvram_read(void *priv, unsigned int offset, void *val,
  265. size_t size)
  266. {
  267. struct platform_device *pdev = priv;
  268. struct device *dev = &pdev->dev;
  269. struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
  270. struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
  271. ssize_t cnt = 0;
  272. unsigned long flags;
  273. u8 *buf = val;
  274. spin_lock_irqsave(&m48t59->lock, flags);
  275. for (; cnt < size; cnt++)
  276. *buf++ = M48T59_READ(cnt);
  277. spin_unlock_irqrestore(&m48t59->lock, flags);
  278. return 0;
  279. }
  280. static int m48t59_nvram_write(void *priv, unsigned int offset, void *val,
  281. size_t size)
  282. {
  283. struct platform_device *pdev = priv;
  284. struct device *dev = &pdev->dev;
  285. struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
  286. struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
  287. ssize_t cnt = 0;
  288. unsigned long flags;
  289. u8 *buf = val;
  290. spin_lock_irqsave(&m48t59->lock, flags);
  291. for (; cnt < size; cnt++)
  292. M48T59_WRITE(*buf++, cnt);
  293. spin_unlock_irqrestore(&m48t59->lock, flags);
  294. return 0;
  295. }
  296. static int m48t59_rtc_probe(struct platform_device *pdev)
  297. {
  298. struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
  299. struct m48t59_private *m48t59 = NULL;
  300. struct resource *res;
  301. int ret = -ENOMEM;
  302. const struct rtc_class_ops *ops;
  303. struct nvmem_config nvmem_cfg = {
  304. .name = "m48t59-",
  305. .word_size = 1,
  306. .stride = 1,
  307. .reg_read = m48t59_nvram_read,
  308. .reg_write = m48t59_nvram_write,
  309. .priv = pdev,
  310. };
  311. /* This chip could be memory-mapped or I/O-mapped */
  312. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  313. if (!res) {
  314. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  315. if (!res)
  316. return -EINVAL;
  317. }
  318. if (res->flags & IORESOURCE_IO) {
  319. /* If we are I/O-mapped, the platform should provide
  320. * the operations accessing chip registers.
  321. */
  322. if (!pdata || !pdata->write_byte || !pdata->read_byte)
  323. return -EINVAL;
  324. } else if (res->flags & IORESOURCE_MEM) {
  325. /* we are memory-mapped */
  326. if (!pdata) {
  327. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
  328. GFP_KERNEL);
  329. if (!pdata)
  330. return -ENOMEM;
  331. /* Ensure we only kmalloc platform data once */
  332. pdev->dev.platform_data = pdata;
  333. }
  334. if (!pdata->type)
  335. pdata->type = M48T59RTC_TYPE_M48T59;
  336. /* Try to use the generic memory read/write ops */
  337. if (!pdata->write_byte)
  338. pdata->write_byte = m48t59_mem_writeb;
  339. if (!pdata->read_byte)
  340. pdata->read_byte = m48t59_mem_readb;
  341. }
  342. m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
  343. if (!m48t59)
  344. return -ENOMEM;
  345. m48t59->ioaddr = pdata->ioaddr;
  346. if (!m48t59->ioaddr) {
  347. /* ioaddr not mapped externally */
  348. m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
  349. resource_size(res));
  350. if (!m48t59->ioaddr)
  351. return ret;
  352. }
  353. /* Try to get irq number. We also can work in
  354. * the mode without IRQ.
  355. */
  356. m48t59->irq = platform_get_irq(pdev, 0);
  357. if (m48t59->irq <= 0)
  358. m48t59->irq = NO_IRQ;
  359. if (m48t59->irq != NO_IRQ) {
  360. ret = devm_request_irq(&pdev->dev, m48t59->irq,
  361. m48t59_rtc_interrupt, IRQF_SHARED,
  362. "rtc-m48t59", &pdev->dev);
  363. if (ret)
  364. return ret;
  365. }
  366. switch (pdata->type) {
  367. case M48T59RTC_TYPE_M48T59:
  368. ops = &m48t59_rtc_ops;
  369. pdata->offset = 0x1ff0;
  370. break;
  371. case M48T59RTC_TYPE_M48T02:
  372. ops = &m48t02_rtc_ops;
  373. pdata->offset = 0x7f0;
  374. break;
  375. case M48T59RTC_TYPE_M48T08:
  376. ops = &m48t02_rtc_ops;
  377. pdata->offset = 0x1ff0;
  378. break;
  379. default:
  380. dev_err(&pdev->dev, "Unknown RTC type\n");
  381. return -ENODEV;
  382. }
  383. spin_lock_init(&m48t59->lock);
  384. platform_set_drvdata(pdev, m48t59);
  385. m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
  386. if (IS_ERR(m48t59->rtc))
  387. return PTR_ERR(m48t59->rtc);
  388. m48t59->rtc->nvram_old_abi = true;
  389. m48t59->rtc->ops = ops;
  390. nvmem_cfg.size = pdata->offset;
  391. ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
  392. if (ret)
  393. return ret;
  394. ret = rtc_register_device(m48t59->rtc);
  395. if (ret)
  396. return ret;
  397. return 0;
  398. }
  399. /* work with hotplug and coldplug */
  400. MODULE_ALIAS("platform:rtc-m48t59");
  401. static struct platform_driver m48t59_rtc_driver = {
  402. .driver = {
  403. .name = "rtc-m48t59",
  404. },
  405. .probe = m48t59_rtc_probe,
  406. };
  407. module_platform_driver(m48t59_rtc_driver);
  408. MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>");
  409. MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
  410. MODULE_LICENSE("GPL");