rtc-lpc32xx.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 NXP Semiconductors
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/rtc.h>
  11. #include <linux/slab.h>
  12. #include <linux/io.h>
  13. #include <linux/of.h>
  14. /*
  15. * Clock and Power control register offsets
  16. */
  17. #define LPC32XX_RTC_UCOUNT 0x00
  18. #define LPC32XX_RTC_DCOUNT 0x04
  19. #define LPC32XX_RTC_MATCH0 0x08
  20. #define LPC32XX_RTC_MATCH1 0x0C
  21. #define LPC32XX_RTC_CTRL 0x10
  22. #define LPC32XX_RTC_INTSTAT 0x14
  23. #define LPC32XX_RTC_KEY 0x18
  24. #define LPC32XX_RTC_SRAM 0x80
  25. #define LPC32XX_RTC_CTRL_MATCH0 (1 << 0)
  26. #define LPC32XX_RTC_CTRL_MATCH1 (1 << 1)
  27. #define LPC32XX_RTC_CTRL_ONSW_MATCH0 (1 << 2)
  28. #define LPC32XX_RTC_CTRL_ONSW_MATCH1 (1 << 3)
  29. #define LPC32XX_RTC_CTRL_SW_RESET (1 << 4)
  30. #define LPC32XX_RTC_CTRL_CNTR_DIS (1 << 6)
  31. #define LPC32XX_RTC_CTRL_ONSW_FORCE_HI (1 << 7)
  32. #define LPC32XX_RTC_INTSTAT_MATCH0 (1 << 0)
  33. #define LPC32XX_RTC_INTSTAT_MATCH1 (1 << 1)
  34. #define LPC32XX_RTC_INTSTAT_ONSW (1 << 2)
  35. #define LPC32XX_RTC_KEY_ONSW_LOADVAL 0xB5C13F27
  36. #define rtc_readl(dev, reg) \
  37. __raw_readl((dev)->rtc_base + (reg))
  38. #define rtc_writel(dev, reg, val) \
  39. __raw_writel((val), (dev)->rtc_base + (reg))
  40. struct lpc32xx_rtc {
  41. void __iomem *rtc_base;
  42. int irq;
  43. unsigned char alarm_enabled;
  44. struct rtc_device *rtc;
  45. spinlock_t lock;
  46. };
  47. static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  48. {
  49. unsigned long elapsed_sec;
  50. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  51. elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
  52. rtc_time64_to_tm(elapsed_sec, time);
  53. return 0;
  54. }
  55. static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
  56. {
  57. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  58. u32 secs = rtc_tm_to_time64(time);
  59. u32 tmp;
  60. spin_lock_irq(&rtc->lock);
  61. /* RTC must be disabled during count update */
  62. tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
  63. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
  64. rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
  65. rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
  66. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
  67. spin_unlock_irq(&rtc->lock);
  68. return 0;
  69. }
  70. static int lpc32xx_rtc_read_alarm(struct device *dev,
  71. struct rtc_wkalrm *wkalrm)
  72. {
  73. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  74. rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
  75. wkalrm->enabled = rtc->alarm_enabled;
  76. wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
  77. LPC32XX_RTC_INTSTAT_MATCH0);
  78. return rtc_valid_tm(&wkalrm->time);
  79. }
  80. static int lpc32xx_rtc_set_alarm(struct device *dev,
  81. struct rtc_wkalrm *wkalrm)
  82. {
  83. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  84. unsigned long alarmsecs;
  85. u32 tmp;
  86. alarmsecs = rtc_tm_to_time64(&wkalrm->time);
  87. spin_lock_irq(&rtc->lock);
  88. /* Disable alarm during update */
  89. tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
  90. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
  91. rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
  92. rtc->alarm_enabled = wkalrm->enabled;
  93. if (wkalrm->enabled) {
  94. rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
  95. LPC32XX_RTC_INTSTAT_MATCH0);
  96. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
  97. LPC32XX_RTC_CTRL_MATCH0);
  98. }
  99. spin_unlock_irq(&rtc->lock);
  100. return 0;
  101. }
  102. static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
  103. unsigned int enabled)
  104. {
  105. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  106. u32 tmp;
  107. spin_lock_irq(&rtc->lock);
  108. tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
  109. if (enabled) {
  110. rtc->alarm_enabled = 1;
  111. tmp |= LPC32XX_RTC_CTRL_MATCH0;
  112. } else {
  113. rtc->alarm_enabled = 0;
  114. tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
  115. }
  116. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
  117. spin_unlock_irq(&rtc->lock);
  118. return 0;
  119. }
  120. static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
  121. {
  122. struct lpc32xx_rtc *rtc = dev;
  123. spin_lock(&rtc->lock);
  124. /* Disable alarm interrupt */
  125. rtc_writel(rtc, LPC32XX_RTC_CTRL,
  126. rtc_readl(rtc, LPC32XX_RTC_CTRL) &
  127. ~LPC32XX_RTC_CTRL_MATCH0);
  128. rtc->alarm_enabled = 0;
  129. /*
  130. * Write a large value to the match value so the RTC won't
  131. * keep firing the match status
  132. */
  133. rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
  134. rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
  135. spin_unlock(&rtc->lock);
  136. rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
  137. return IRQ_HANDLED;
  138. }
  139. static const struct rtc_class_ops lpc32xx_rtc_ops = {
  140. .read_time = lpc32xx_rtc_read_time,
  141. .set_time = lpc32xx_rtc_set_time,
  142. .read_alarm = lpc32xx_rtc_read_alarm,
  143. .set_alarm = lpc32xx_rtc_set_alarm,
  144. .alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
  145. };
  146. static int lpc32xx_rtc_probe(struct platform_device *pdev)
  147. {
  148. struct lpc32xx_rtc *rtc;
  149. int err;
  150. u32 tmp;
  151. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  152. if (unlikely(!rtc))
  153. return -ENOMEM;
  154. rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
  155. if (IS_ERR(rtc->rtc_base))
  156. return PTR_ERR(rtc->rtc_base);
  157. spin_lock_init(&rtc->lock);
  158. /*
  159. * The RTC is on a separate power domain and can keep it's state
  160. * across a chip power cycle. If the RTC has never been previously
  161. * setup, then set it up now for the first time.
  162. */
  163. tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
  164. if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
  165. tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
  166. LPC32XX_RTC_CTRL_CNTR_DIS |
  167. LPC32XX_RTC_CTRL_MATCH0 |
  168. LPC32XX_RTC_CTRL_MATCH1 |
  169. LPC32XX_RTC_CTRL_ONSW_MATCH0 |
  170. LPC32XX_RTC_CTRL_ONSW_MATCH1 |
  171. LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
  172. rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
  173. /* Clear latched interrupt states */
  174. rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
  175. rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
  176. LPC32XX_RTC_INTSTAT_MATCH0 |
  177. LPC32XX_RTC_INTSTAT_MATCH1 |
  178. LPC32XX_RTC_INTSTAT_ONSW);
  179. /* Write key value to RTC so it won't reload on reset */
  180. rtc_writel(rtc, LPC32XX_RTC_KEY,
  181. LPC32XX_RTC_KEY_ONSW_LOADVAL);
  182. } else {
  183. rtc_writel(rtc, LPC32XX_RTC_CTRL,
  184. tmp & ~LPC32XX_RTC_CTRL_MATCH0);
  185. }
  186. platform_set_drvdata(pdev, rtc);
  187. rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
  188. if (IS_ERR(rtc->rtc))
  189. return PTR_ERR(rtc->rtc);
  190. rtc->rtc->ops = &lpc32xx_rtc_ops;
  191. rtc->rtc->range_max = U32_MAX;
  192. err = rtc_register_device(rtc->rtc);
  193. if (err)
  194. return err;
  195. /*
  196. * IRQ is enabled after device registration in case alarm IRQ
  197. * is pending upon suspend exit.
  198. */
  199. rtc->irq = platform_get_irq(pdev, 0);
  200. if (rtc->irq < 0) {
  201. dev_warn(&pdev->dev, "Can't get interrupt resource\n");
  202. } else {
  203. if (devm_request_irq(&pdev->dev, rtc->irq,
  204. lpc32xx_rtc_alarm_interrupt,
  205. 0, pdev->name, rtc) < 0) {
  206. dev_warn(&pdev->dev, "Can't request interrupt.\n");
  207. rtc->irq = -1;
  208. } else {
  209. device_init_wakeup(&pdev->dev, 1);
  210. }
  211. }
  212. return 0;
  213. }
  214. #ifdef CONFIG_PM
  215. static int lpc32xx_rtc_suspend(struct device *dev)
  216. {
  217. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  218. if (rtc->irq >= 0) {
  219. if (device_may_wakeup(dev))
  220. enable_irq_wake(rtc->irq);
  221. else
  222. disable_irq_wake(rtc->irq);
  223. }
  224. return 0;
  225. }
  226. static int lpc32xx_rtc_resume(struct device *dev)
  227. {
  228. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  229. if (rtc->irq >= 0 && device_may_wakeup(dev))
  230. disable_irq_wake(rtc->irq);
  231. return 0;
  232. }
  233. /* Unconditionally disable the alarm */
  234. static int lpc32xx_rtc_freeze(struct device *dev)
  235. {
  236. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  237. spin_lock_irq(&rtc->lock);
  238. rtc_writel(rtc, LPC32XX_RTC_CTRL,
  239. rtc_readl(rtc, LPC32XX_RTC_CTRL) &
  240. ~LPC32XX_RTC_CTRL_MATCH0);
  241. spin_unlock_irq(&rtc->lock);
  242. return 0;
  243. }
  244. static int lpc32xx_rtc_thaw(struct device *dev)
  245. {
  246. struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  247. if (rtc->alarm_enabled) {
  248. spin_lock_irq(&rtc->lock);
  249. rtc_writel(rtc, LPC32XX_RTC_CTRL,
  250. rtc_readl(rtc, LPC32XX_RTC_CTRL) |
  251. LPC32XX_RTC_CTRL_MATCH0);
  252. spin_unlock_irq(&rtc->lock);
  253. }
  254. return 0;
  255. }
  256. static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
  257. .suspend = lpc32xx_rtc_suspend,
  258. .resume = lpc32xx_rtc_resume,
  259. .freeze = lpc32xx_rtc_freeze,
  260. .thaw = lpc32xx_rtc_thaw,
  261. .restore = lpc32xx_rtc_resume
  262. };
  263. #define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
  264. #else
  265. #define LPC32XX_RTC_PM_OPS NULL
  266. #endif
  267. #ifdef CONFIG_OF
  268. static const struct of_device_id lpc32xx_rtc_match[] = {
  269. { .compatible = "nxp,lpc3220-rtc" },
  270. { }
  271. };
  272. MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
  273. #endif
  274. static struct platform_driver lpc32xx_rtc_driver = {
  275. .probe = lpc32xx_rtc_probe,
  276. .driver = {
  277. .name = "rtc-lpc32xx",
  278. .pm = LPC32XX_RTC_PM_OPS,
  279. .of_match_table = of_match_ptr(lpc32xx_rtc_match),
  280. },
  281. };
  282. module_platform_driver(lpc32xx_rtc_driver);
  283. MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
  284. MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
  285. MODULE_LICENSE("GPL");
  286. MODULE_ALIAS("platform:rtc-lpc32xx");