rtc-fsl-ftm-alarm.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale FlexTimer Module (FTM) alarm device driver.
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2019-2020 NXP
  7. *
  8. */
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/module.h>
  19. #include <linux/fsl/ftm.h>
  20. #include <linux/rtc.h>
  21. #include <linux/time.h>
  22. #include <linux/acpi.h>
  23. #include <linux/pm_wakeirq.h>
  24. #define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
  25. /*
  26. * Select Fixed frequency clock (32KHz) as clock source
  27. * of FlexTimer Module
  28. */
  29. #define FTM_SC_CLKS_FIXED_FREQ 0x02
  30. #define FIXED_FREQ_CLK 32000
  31. /* Select 128 (2^7) as divider factor */
  32. #define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)
  33. /* Maximum counter value in FlexTimer's CNT registers */
  34. #define MAX_COUNT_VAL 0xffff
  35. struct ftm_rtc {
  36. struct rtc_device *rtc_dev;
  37. void __iomem *base;
  38. bool big_endian;
  39. u32 alarm_freq;
  40. };
  41. static inline u32 rtc_readl(struct ftm_rtc *dev, u32 reg)
  42. {
  43. if (dev->big_endian)
  44. return ioread32be(dev->base + reg);
  45. else
  46. return ioread32(dev->base + reg);
  47. }
  48. static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val)
  49. {
  50. if (dev->big_endian)
  51. iowrite32be(val, dev->base + reg);
  52. else
  53. iowrite32(val, dev->base + reg);
  54. }
  55. static inline void ftm_counter_enable(struct ftm_rtc *rtc)
  56. {
  57. u32 val;
  58. /* select and enable counter clock source */
  59. val = rtc_readl(rtc, FTM_SC);
  60. val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
  61. val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
  62. rtc_writel(rtc, FTM_SC, val);
  63. }
  64. static inline void ftm_counter_disable(struct ftm_rtc *rtc)
  65. {
  66. u32 val;
  67. /* disable counter clock source */
  68. val = rtc_readl(rtc, FTM_SC);
  69. val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
  70. rtc_writel(rtc, FTM_SC, val);
  71. }
  72. static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)
  73. {
  74. unsigned int timeout = 100;
  75. /*
  76. *Fix errata A-007728 for flextimer
  77. * If the FTM counter reaches the FTM_MOD value between
  78. * the reading of the TOF bit and the writing of 0 to
  79. * the TOF bit, the process of clearing the TOF bit
  80. * does not work as expected when FTMx_CONF[NUMTOF] != 0
  81. * and the current TOF count is less than FTMx_CONF[NUMTOF].
  82. * If the above condition is met, the TOF bit remains set.
  83. * If the TOF interrupt is enabled (FTMx_SC[TOIE] = 1),the
  84. * TOF interrupt also remains asserted.
  85. *
  86. * Above is the errata discription
  87. *
  88. * In one word: software clearing TOF bit not works when
  89. * FTMx_CONF[NUMTOF] was seted as nonzero and FTM counter
  90. * reaches the FTM_MOD value.
  91. *
  92. * The workaround is clearing TOF bit until it works
  93. * (FTM counter doesn't always reache the FTM_MOD anyway),
  94. * which may cost some cycles.
  95. */
  96. while ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--)
  97. rtc_writel(rtc, FTM_SC, rtc_readl(rtc, FTM_SC) & (~FTM_SC_TOF));
  98. }
  99. static inline void ftm_irq_enable(struct ftm_rtc *rtc)
  100. {
  101. u32 val;
  102. val = rtc_readl(rtc, FTM_SC);
  103. val |= FTM_SC_TOIE;
  104. rtc_writel(rtc, FTM_SC, val);
  105. }
  106. static inline void ftm_irq_disable(struct ftm_rtc *rtc)
  107. {
  108. u32 val;
  109. val = rtc_readl(rtc, FTM_SC);
  110. val &= ~FTM_SC_TOIE;
  111. rtc_writel(rtc, FTM_SC, val);
  112. }
  113. static inline void ftm_reset_counter(struct ftm_rtc *rtc)
  114. {
  115. /*
  116. * The CNT register contains the FTM counter value.
  117. * Reset clears the CNT register. Writing any value to COUNT
  118. * updates the counter with its initial value, CNTIN.
  119. */
  120. rtc_writel(rtc, FTM_CNT, 0x00);
  121. }
  122. static void ftm_clean_alarm(struct ftm_rtc *rtc)
  123. {
  124. ftm_counter_disable(rtc);
  125. rtc_writel(rtc, FTM_CNTIN, 0x00);
  126. rtc_writel(rtc, FTM_MOD, ~0U);
  127. ftm_reset_counter(rtc);
  128. }
  129. static irqreturn_t ftm_rtc_alarm_interrupt(int irq, void *dev)
  130. {
  131. struct ftm_rtc *rtc = dev;
  132. rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
  133. ftm_irq_acknowledge(rtc);
  134. ftm_irq_disable(rtc);
  135. ftm_clean_alarm(rtc);
  136. return IRQ_HANDLED;
  137. }
  138. static int ftm_rtc_alarm_irq_enable(struct device *dev,
  139. unsigned int enabled)
  140. {
  141. struct ftm_rtc *rtc = dev_get_drvdata(dev);
  142. if (enabled)
  143. ftm_irq_enable(rtc);
  144. else
  145. ftm_irq_disable(rtc);
  146. return 0;
  147. }
  148. /*
  149. * Note:
  150. * The function is not really getting time from the RTC
  151. * since FlexTimer is not a RTC device, but we need to
  152. * get time to setup alarm, so we are using system time
  153. * for now.
  154. */
  155. static int ftm_rtc_read_time(struct device *dev, struct rtc_time *tm)
  156. {
  157. rtc_time64_to_tm(ktime_get_real_seconds(), tm);
  158. return 0;
  159. }
  160. static int ftm_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  161. {
  162. return 0;
  163. }
  164. /*
  165. * 1. Select fixed frequency clock (32KHz) as clock source;
  166. * 2. Select 128 (2^7) as divider factor;
  167. * So clock is 250 Hz (32KHz/128).
  168. *
  169. * 3. FlexTimer's CNT register is a 32bit register,
  170. * but the register's 16 bit as counter value,it's other 16 bit
  171. * is reserved.So minimum counter value is 0x0,maximum counter
  172. * value is 0xffff.
  173. * So max alarm value is 262 (65536 / 250) seconds
  174. */
  175. static int ftm_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  176. {
  177. time64_t alm_time;
  178. unsigned long long cycle;
  179. struct ftm_rtc *rtc = dev_get_drvdata(dev);
  180. alm_time = rtc_tm_to_time64(&alm->time);
  181. ftm_clean_alarm(rtc);
  182. cycle = (alm_time - ktime_get_real_seconds()) * rtc->alarm_freq;
  183. if (cycle > MAX_COUNT_VAL) {
  184. pr_err("Out of alarm range {0~262} seconds.\n");
  185. return -ERANGE;
  186. }
  187. ftm_irq_disable(rtc);
  188. /*
  189. * The counter increments until the value of MOD is reached,
  190. * at which point the counter is reloaded with the value of CNTIN.
  191. * The TOF (the overflow flag) bit is set when the FTM counter
  192. * changes from MOD to CNTIN. So we should using the cycle - 1.
  193. */
  194. rtc_writel(rtc, FTM_MOD, cycle - 1);
  195. ftm_counter_enable(rtc);
  196. ftm_irq_enable(rtc);
  197. return 0;
  198. }
  199. static const struct rtc_class_ops ftm_rtc_ops = {
  200. .read_time = ftm_rtc_read_time,
  201. .read_alarm = ftm_rtc_read_alarm,
  202. .set_alarm = ftm_rtc_set_alarm,
  203. .alarm_irq_enable = ftm_rtc_alarm_irq_enable,
  204. };
  205. static int ftm_rtc_probe(struct platform_device *pdev)
  206. {
  207. int irq;
  208. int ret;
  209. struct ftm_rtc *rtc;
  210. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  211. if (unlikely(!rtc)) {
  212. dev_err(&pdev->dev, "cannot alloc memory for rtc\n");
  213. return -ENOMEM;
  214. }
  215. platform_set_drvdata(pdev, rtc);
  216. rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
  217. if (IS_ERR(rtc->rtc_dev))
  218. return PTR_ERR(rtc->rtc_dev);
  219. rtc->base = devm_platform_ioremap_resource(pdev, 0);
  220. if (IS_ERR(rtc->base)) {
  221. dev_err(&pdev->dev, "cannot ioremap resource for rtc\n");
  222. return PTR_ERR(rtc->base);
  223. }
  224. irq = platform_get_irq(pdev, 0);
  225. if (irq < 0)
  226. return irq;
  227. ret = devm_request_irq(&pdev->dev, irq, ftm_rtc_alarm_interrupt,
  228. 0, dev_name(&pdev->dev), rtc);
  229. if (ret < 0) {
  230. dev_err(&pdev->dev, "failed to request irq\n");
  231. return ret;
  232. }
  233. rtc->big_endian =
  234. device_property_read_bool(&pdev->dev, "big-endian");
  235. rtc->alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
  236. rtc->rtc_dev->ops = &ftm_rtc_ops;
  237. device_init_wakeup(&pdev->dev, true);
  238. ret = dev_pm_set_wake_irq(&pdev->dev, irq);
  239. if (ret)
  240. dev_err(&pdev->dev, "failed to enable irq wake\n");
  241. ret = rtc_register_device(rtc->rtc_dev);
  242. if (ret) {
  243. dev_err(&pdev->dev, "can't register rtc device\n");
  244. return ret;
  245. }
  246. return 0;
  247. }
  248. static const struct of_device_id ftm_rtc_match[] = {
  249. { .compatible = "fsl,ls1012a-ftm-alarm", },
  250. { .compatible = "fsl,ls1021a-ftm-alarm", },
  251. { .compatible = "fsl,ls1028a-ftm-alarm", },
  252. { .compatible = "fsl,ls1043a-ftm-alarm", },
  253. { .compatible = "fsl,ls1046a-ftm-alarm", },
  254. { .compatible = "fsl,ls1088a-ftm-alarm", },
  255. { .compatible = "fsl,ls208xa-ftm-alarm", },
  256. { .compatible = "fsl,lx2160a-ftm-alarm", },
  257. { },
  258. };
  259. MODULE_DEVICE_TABLE(of, ftm_rtc_match);
  260. static const struct acpi_device_id ftm_imx_acpi_ids[] = {
  261. {"NXP0014",},
  262. { }
  263. };
  264. MODULE_DEVICE_TABLE(acpi, ftm_imx_acpi_ids);
  265. static struct platform_driver ftm_rtc_driver = {
  266. .probe = ftm_rtc_probe,
  267. .driver = {
  268. .name = "ftm-alarm",
  269. .of_match_table = ftm_rtc_match,
  270. .acpi_match_table = ACPI_PTR(ftm_imx_acpi_ids),
  271. },
  272. };
  273. static int __init ftm_alarm_init(void)
  274. {
  275. return platform_driver_register(&ftm_rtc_driver);
  276. }
  277. device_initcall(ftm_alarm_init);
  278. MODULE_DESCRIPTION("NXP/Freescale FlexTimer alarm driver");
  279. MODULE_AUTHOR("Biwen Li <biwen.li@nxp.com>");
  280. MODULE_LICENSE("GPL");