rtc-ds3232.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * RTC client/driver for the Maxim/Dallas DS3232/DS3234 Real-Time Clock
  4. *
  5. * Copyright (C) 2009-2011 Freescale Semiconductor.
  6. * Author: Jack Lan <jack.lan@freescale.com>
  7. * Copyright (C) 2008 MIMOMax Wireless Ltd.
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/rtc.h>
  16. #include <linux/bcd.h>
  17. #include <linux/slab.h>
  18. #include <linux/regmap.h>
  19. #include <linux/hwmon.h>
  20. #define DS3232_REG_SECONDS 0x00
  21. #define DS3232_REG_MINUTES 0x01
  22. #define DS3232_REG_HOURS 0x02
  23. #define DS3232_REG_AMPM 0x02
  24. #define DS3232_REG_DAY 0x03
  25. #define DS3232_REG_DATE 0x04
  26. #define DS3232_REG_MONTH 0x05
  27. #define DS3232_REG_CENTURY 0x05
  28. #define DS3232_REG_YEAR 0x06
  29. #define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
  30. #define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
  31. #define DS3232_REG_CR 0x0E /* Control register */
  32. # define DS3232_REG_CR_nEOSC 0x80
  33. # define DS3232_REG_CR_INTCN 0x04
  34. # define DS3232_REG_CR_A2IE 0x02
  35. # define DS3232_REG_CR_A1IE 0x01
  36. #define DS3232_REG_SR 0x0F /* control/status register */
  37. # define DS3232_REG_SR_OSF 0x80
  38. # define DS3232_REG_SR_BSY 0x04
  39. # define DS3232_REG_SR_A2F 0x02
  40. # define DS3232_REG_SR_A1F 0x01
  41. #define DS3232_REG_TEMPERATURE 0x11
  42. #define DS3232_REG_SRAM_START 0x14
  43. #define DS3232_REG_SRAM_END 0xFF
  44. #define DS3232_REG_SRAM_SIZE 236
  45. struct ds3232 {
  46. struct device *dev;
  47. struct regmap *regmap;
  48. int irq;
  49. struct rtc_device *rtc;
  50. bool suspended;
  51. };
  52. static int ds3232_check_rtc_status(struct device *dev)
  53. {
  54. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  55. int ret = 0;
  56. int control, stat;
  57. ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
  58. if (ret)
  59. return ret;
  60. if (stat & DS3232_REG_SR_OSF)
  61. dev_warn(dev,
  62. "oscillator discontinuity flagged, "
  63. "time unreliable\n");
  64. stat &= ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
  65. ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
  66. if (ret)
  67. return ret;
  68. /* If the alarm is pending, clear it before requesting
  69. * the interrupt, so an interrupt event isn't reported
  70. * before everything is initialized.
  71. */
  72. ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
  73. if (ret)
  74. return ret;
  75. control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
  76. control |= DS3232_REG_CR_INTCN;
  77. return regmap_write(ds3232->regmap, DS3232_REG_CR, control);
  78. }
  79. static int ds3232_read_time(struct device *dev, struct rtc_time *time)
  80. {
  81. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  82. int ret;
  83. u8 buf[7];
  84. unsigned int year, month, day, hour, minute, second;
  85. unsigned int week, twelve_hr, am_pm;
  86. unsigned int century, add_century = 0;
  87. ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
  88. if (ret)
  89. return ret;
  90. second = buf[0];
  91. minute = buf[1];
  92. hour = buf[2];
  93. week = buf[3];
  94. day = buf[4];
  95. month = buf[5];
  96. year = buf[6];
  97. /* Extract additional information for AM/PM and century */
  98. twelve_hr = hour & 0x40;
  99. am_pm = hour & 0x20;
  100. century = month & 0x80;
  101. /* Write to rtc_time structure */
  102. time->tm_sec = bcd2bin(second);
  103. time->tm_min = bcd2bin(minute);
  104. if (twelve_hr) {
  105. /* Convert to 24 hr */
  106. if (am_pm)
  107. time->tm_hour = bcd2bin(hour & 0x1F) + 12;
  108. else
  109. time->tm_hour = bcd2bin(hour & 0x1F);
  110. } else {
  111. time->tm_hour = bcd2bin(hour);
  112. }
  113. /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
  114. time->tm_wday = bcd2bin(week) - 1;
  115. time->tm_mday = bcd2bin(day);
  116. /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
  117. time->tm_mon = bcd2bin(month & 0x7F) - 1;
  118. if (century)
  119. add_century = 100;
  120. time->tm_year = bcd2bin(year) + add_century;
  121. return 0;
  122. }
  123. static int ds3232_set_time(struct device *dev, struct rtc_time *time)
  124. {
  125. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  126. u8 buf[7];
  127. /* Extract time from rtc_time and load into ds3232*/
  128. buf[0] = bin2bcd(time->tm_sec);
  129. buf[1] = bin2bcd(time->tm_min);
  130. buf[2] = bin2bcd(time->tm_hour);
  131. /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
  132. buf[3] = bin2bcd(time->tm_wday + 1);
  133. buf[4] = bin2bcd(time->tm_mday); /* Date */
  134. /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
  135. buf[5] = bin2bcd(time->tm_mon + 1);
  136. if (time->tm_year >= 100) {
  137. buf[5] |= 0x80;
  138. buf[6] = bin2bcd(time->tm_year - 100);
  139. } else {
  140. buf[6] = bin2bcd(time->tm_year);
  141. }
  142. return regmap_bulk_write(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
  143. }
  144. /*
  145. * DS3232 has two alarm, we only use alarm1
  146. * According to linux specification, only support one-shot alarm
  147. * no periodic alarm mode
  148. */
  149. static int ds3232_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  150. {
  151. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  152. int control, stat;
  153. int ret;
  154. u8 buf[4];
  155. ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
  156. if (ret)
  157. goto out;
  158. ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
  159. if (ret)
  160. goto out;
  161. ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
  162. if (ret)
  163. goto out;
  164. alarm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
  165. alarm->time.tm_min = bcd2bin(buf[1] & 0x7F);
  166. alarm->time.tm_hour = bcd2bin(buf[2] & 0x7F);
  167. alarm->time.tm_mday = bcd2bin(buf[3] & 0x7F);
  168. alarm->enabled = !!(control & DS3232_REG_CR_A1IE);
  169. alarm->pending = !!(stat & DS3232_REG_SR_A1F);
  170. ret = 0;
  171. out:
  172. return ret;
  173. }
  174. /*
  175. * linux rtc-module does not support wday alarm
  176. * and only 24h time mode supported indeed
  177. */
  178. static int ds3232_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  179. {
  180. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  181. int control, stat;
  182. int ret;
  183. u8 buf[4];
  184. if (ds3232->irq <= 0)
  185. return -EINVAL;
  186. buf[0] = bin2bcd(alarm->time.tm_sec);
  187. buf[1] = bin2bcd(alarm->time.tm_min);
  188. buf[2] = bin2bcd(alarm->time.tm_hour);
  189. buf[3] = bin2bcd(alarm->time.tm_mday);
  190. /* clear alarm interrupt enable bit */
  191. ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
  192. if (ret)
  193. goto out;
  194. control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
  195. ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
  196. if (ret)
  197. goto out;
  198. /* clear any pending alarm flag */
  199. ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
  200. if (ret)
  201. goto out;
  202. stat &= ~(DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
  203. ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
  204. if (ret)
  205. goto out;
  206. ret = regmap_bulk_write(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
  207. if (ret)
  208. goto out;
  209. if (alarm->enabled) {
  210. control |= DS3232_REG_CR_A1IE;
  211. ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
  212. }
  213. out:
  214. return ret;
  215. }
  216. static int ds3232_update_alarm(struct device *dev, unsigned int enabled)
  217. {
  218. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  219. int control;
  220. int ret;
  221. ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
  222. if (ret)
  223. return ret;
  224. if (enabled)
  225. /* enable alarm1 interrupt */
  226. control |= DS3232_REG_CR_A1IE;
  227. else
  228. /* disable alarm1 interrupt */
  229. control &= ~(DS3232_REG_CR_A1IE);
  230. ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
  231. return ret;
  232. }
  233. /*
  234. * Temperature sensor support for ds3232/ds3234 devices.
  235. * A user-initiated temperature conversion is not started by this function,
  236. * so the temperature is updated once every 64 seconds.
  237. */
  238. static int ds3232_hwmon_read_temp(struct device *dev, long int *mC)
  239. {
  240. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  241. u8 temp_buf[2];
  242. s16 temp;
  243. int ret;
  244. ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_TEMPERATURE, temp_buf,
  245. sizeof(temp_buf));
  246. if (ret < 0)
  247. return ret;
  248. /*
  249. * Temperature is represented as a 10-bit code with a resolution of
  250. * 0.25 degree celsius and encoded in two's complement format.
  251. */
  252. temp = (temp_buf[0] << 8) | temp_buf[1];
  253. temp >>= 6;
  254. *mC = temp * 250;
  255. return 0;
  256. }
  257. static umode_t ds3232_hwmon_is_visible(const void *data,
  258. enum hwmon_sensor_types type,
  259. u32 attr, int channel)
  260. {
  261. if (type != hwmon_temp)
  262. return 0;
  263. switch (attr) {
  264. case hwmon_temp_input:
  265. return 0444;
  266. default:
  267. return 0;
  268. }
  269. }
  270. static int ds3232_hwmon_read(struct device *dev,
  271. enum hwmon_sensor_types type,
  272. u32 attr, int channel, long *temp)
  273. {
  274. int err;
  275. switch (attr) {
  276. case hwmon_temp_input:
  277. err = ds3232_hwmon_read_temp(dev, temp);
  278. break;
  279. default:
  280. err = -EOPNOTSUPP;
  281. break;
  282. }
  283. return err;
  284. }
  285. static u32 ds3232_hwmon_chip_config[] = {
  286. HWMON_C_REGISTER_TZ,
  287. 0
  288. };
  289. static const struct hwmon_channel_info ds3232_hwmon_chip = {
  290. .type = hwmon_chip,
  291. .config = ds3232_hwmon_chip_config,
  292. };
  293. static u32 ds3232_hwmon_temp_config[] = {
  294. HWMON_T_INPUT,
  295. 0
  296. };
  297. static const struct hwmon_channel_info ds3232_hwmon_temp = {
  298. .type = hwmon_temp,
  299. .config = ds3232_hwmon_temp_config,
  300. };
  301. static const struct hwmon_channel_info *ds3232_hwmon_info[] = {
  302. &ds3232_hwmon_chip,
  303. &ds3232_hwmon_temp,
  304. NULL
  305. };
  306. static const struct hwmon_ops ds3232_hwmon_hwmon_ops = {
  307. .is_visible = ds3232_hwmon_is_visible,
  308. .read = ds3232_hwmon_read,
  309. };
  310. static const struct hwmon_chip_info ds3232_hwmon_chip_info = {
  311. .ops = &ds3232_hwmon_hwmon_ops,
  312. .info = ds3232_hwmon_info,
  313. };
  314. static void ds3232_hwmon_register(struct device *dev, const char *name)
  315. {
  316. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  317. struct device *hwmon_dev;
  318. if (!IS_ENABLED(CONFIG_RTC_DRV_DS3232_HWMON))
  319. return;
  320. hwmon_dev = devm_hwmon_device_register_with_info(dev, name, ds3232,
  321. &ds3232_hwmon_chip_info,
  322. NULL);
  323. if (IS_ERR(hwmon_dev)) {
  324. dev_err(dev, "unable to register hwmon device %ld\n",
  325. PTR_ERR(hwmon_dev));
  326. }
  327. }
  328. static int ds3232_alarm_irq_enable(struct device *dev, unsigned int enabled)
  329. {
  330. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  331. if (ds3232->irq <= 0)
  332. return -EINVAL;
  333. return ds3232_update_alarm(dev, enabled);
  334. }
  335. static irqreturn_t ds3232_irq(int irq, void *dev_id)
  336. {
  337. struct device *dev = dev_id;
  338. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  339. struct mutex *lock = &ds3232->rtc->ops_lock;
  340. int ret;
  341. int stat, control;
  342. mutex_lock(lock);
  343. ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
  344. if (ret)
  345. goto unlock;
  346. if (stat & DS3232_REG_SR_A1F) {
  347. ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
  348. if (ret) {
  349. dev_warn(ds3232->dev,
  350. "Read Control Register error %d\n", ret);
  351. } else {
  352. /* disable alarm1 interrupt */
  353. control &= ~(DS3232_REG_CR_A1IE);
  354. ret = regmap_write(ds3232->regmap, DS3232_REG_CR,
  355. control);
  356. if (ret) {
  357. dev_warn(ds3232->dev,
  358. "Write Control Register error %d\n",
  359. ret);
  360. goto unlock;
  361. }
  362. /* clear the alarm pend flag */
  363. stat &= ~DS3232_REG_SR_A1F;
  364. ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
  365. if (ret) {
  366. dev_warn(ds3232->dev,
  367. "Write Status Register error %d\n",
  368. ret);
  369. goto unlock;
  370. }
  371. rtc_update_irq(ds3232->rtc, 1, RTC_AF | RTC_IRQF);
  372. }
  373. }
  374. unlock:
  375. mutex_unlock(lock);
  376. return IRQ_HANDLED;
  377. }
  378. static const struct rtc_class_ops ds3232_rtc_ops = {
  379. .read_time = ds3232_read_time,
  380. .set_time = ds3232_set_time,
  381. .read_alarm = ds3232_read_alarm,
  382. .set_alarm = ds3232_set_alarm,
  383. .alarm_irq_enable = ds3232_alarm_irq_enable,
  384. };
  385. static int ds3232_nvmem_read(void *priv, unsigned int offset, void *val,
  386. size_t bytes)
  387. {
  388. struct regmap *ds3232_regmap = (struct regmap *)priv;
  389. return regmap_bulk_read(ds3232_regmap, DS3232_REG_SRAM_START + offset,
  390. val, bytes);
  391. }
  392. static int ds3232_nvmem_write(void *priv, unsigned int offset, void *val,
  393. size_t bytes)
  394. {
  395. struct regmap *ds3232_regmap = (struct regmap *)priv;
  396. return regmap_bulk_write(ds3232_regmap, DS3232_REG_SRAM_START + offset,
  397. val, bytes);
  398. }
  399. static int ds3232_probe(struct device *dev, struct regmap *regmap, int irq,
  400. const char *name)
  401. {
  402. struct ds3232 *ds3232;
  403. int ret;
  404. struct nvmem_config nvmem_cfg = {
  405. .name = "ds3232_sram",
  406. .stride = 1,
  407. .size = DS3232_REG_SRAM_SIZE,
  408. .word_size = 1,
  409. .reg_read = ds3232_nvmem_read,
  410. .reg_write = ds3232_nvmem_write,
  411. .priv = regmap,
  412. .type = NVMEM_TYPE_BATTERY_BACKED
  413. };
  414. ds3232 = devm_kzalloc(dev, sizeof(*ds3232), GFP_KERNEL);
  415. if (!ds3232)
  416. return -ENOMEM;
  417. ds3232->regmap = regmap;
  418. ds3232->irq = irq;
  419. ds3232->dev = dev;
  420. dev_set_drvdata(dev, ds3232);
  421. ret = ds3232_check_rtc_status(dev);
  422. if (ret)
  423. return ret;
  424. if (ds3232->irq > 0)
  425. device_init_wakeup(dev, 1);
  426. ds3232_hwmon_register(dev, name);
  427. ds3232->rtc = devm_rtc_device_register(dev, name, &ds3232_rtc_ops,
  428. THIS_MODULE);
  429. if (IS_ERR(ds3232->rtc))
  430. return PTR_ERR(ds3232->rtc);
  431. ret = rtc_nvmem_register(ds3232->rtc, &nvmem_cfg);
  432. if(ret)
  433. return ret;
  434. if (ds3232->irq > 0) {
  435. ret = devm_request_threaded_irq(dev, ds3232->irq, NULL,
  436. ds3232_irq,
  437. IRQF_SHARED | IRQF_ONESHOT,
  438. name, dev);
  439. if (ret) {
  440. device_set_wakeup_capable(dev, 0);
  441. ds3232->irq = 0;
  442. dev_err(dev, "unable to request IRQ\n");
  443. }
  444. }
  445. return 0;
  446. }
  447. #ifdef CONFIG_PM_SLEEP
  448. static int ds3232_suspend(struct device *dev)
  449. {
  450. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  451. if (device_may_wakeup(dev)) {
  452. if (enable_irq_wake(ds3232->irq))
  453. dev_warn_once(dev, "Cannot set wakeup source\n");
  454. }
  455. return 0;
  456. }
  457. static int ds3232_resume(struct device *dev)
  458. {
  459. struct ds3232 *ds3232 = dev_get_drvdata(dev);
  460. if (device_may_wakeup(dev))
  461. disable_irq_wake(ds3232->irq);
  462. return 0;
  463. }
  464. #endif
  465. static const struct dev_pm_ops ds3232_pm_ops = {
  466. SET_SYSTEM_SLEEP_PM_OPS(ds3232_suspend, ds3232_resume)
  467. };
  468. #if IS_ENABLED(CONFIG_I2C)
  469. static int ds3232_i2c_probe(struct i2c_client *client,
  470. const struct i2c_device_id *id)
  471. {
  472. struct regmap *regmap;
  473. static const struct regmap_config config = {
  474. .reg_bits = 8,
  475. .val_bits = 8,
  476. .max_register = DS3232_REG_SRAM_END,
  477. };
  478. regmap = devm_regmap_init_i2c(client, &config);
  479. if (IS_ERR(regmap)) {
  480. dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
  481. __func__, PTR_ERR(regmap));
  482. return PTR_ERR(regmap);
  483. }
  484. return ds3232_probe(&client->dev, regmap, client->irq, client->name);
  485. }
  486. static const struct i2c_device_id ds3232_id[] = {
  487. { "ds3232", 0 },
  488. { }
  489. };
  490. MODULE_DEVICE_TABLE(i2c, ds3232_id);
  491. static const struct of_device_id ds3232_of_match[] = {
  492. { .compatible = "dallas,ds3232" },
  493. { }
  494. };
  495. MODULE_DEVICE_TABLE(of, ds3232_of_match);
  496. static struct i2c_driver ds3232_driver = {
  497. .driver = {
  498. .name = "rtc-ds3232",
  499. .of_match_table = of_match_ptr(ds3232_of_match),
  500. .pm = &ds3232_pm_ops,
  501. },
  502. .probe = ds3232_i2c_probe,
  503. .id_table = ds3232_id,
  504. };
  505. static int ds3232_register_driver(void)
  506. {
  507. return i2c_add_driver(&ds3232_driver);
  508. }
  509. static void ds3232_unregister_driver(void)
  510. {
  511. i2c_del_driver(&ds3232_driver);
  512. }
  513. #else
  514. static int ds3232_register_driver(void)
  515. {
  516. return 0;
  517. }
  518. static void ds3232_unregister_driver(void)
  519. {
  520. }
  521. #endif
  522. #if IS_ENABLED(CONFIG_SPI_MASTER)
  523. static int ds3234_probe(struct spi_device *spi)
  524. {
  525. int res;
  526. unsigned int tmp;
  527. static const struct regmap_config config = {
  528. .reg_bits = 8,
  529. .val_bits = 8,
  530. .max_register = DS3232_REG_SRAM_END,
  531. .write_flag_mask = 0x80,
  532. };
  533. struct regmap *regmap;
  534. regmap = devm_regmap_init_spi(spi, &config);
  535. if (IS_ERR(regmap)) {
  536. dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
  537. __func__, PTR_ERR(regmap));
  538. return PTR_ERR(regmap);
  539. }
  540. spi->mode = SPI_MODE_3;
  541. spi->bits_per_word = 8;
  542. spi_setup(spi);
  543. res = regmap_read(regmap, DS3232_REG_SECONDS, &tmp);
  544. if (res)
  545. return res;
  546. /* Control settings
  547. *
  548. * CONTROL_REG
  549. * BIT 7 6 5 4 3 2 1 0
  550. * EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
  551. *
  552. * 0 0 0 1 1 1 0 0
  553. *
  554. * CONTROL_STAT_REG
  555. * BIT 7 6 5 4 3 2 1 0
  556. * OSF BB32kHz CRATE1 CRATE0 EN32kHz BSY A2F A1F
  557. *
  558. * 1 0 0 0 1 0 0 0
  559. */
  560. res = regmap_read(regmap, DS3232_REG_CR, &tmp);
  561. if (res)
  562. return res;
  563. res = regmap_write(regmap, DS3232_REG_CR, tmp & 0x1c);
  564. if (res)
  565. return res;
  566. res = regmap_read(regmap, DS3232_REG_SR, &tmp);
  567. if (res)
  568. return res;
  569. res = regmap_write(regmap, DS3232_REG_SR, tmp & 0x88);
  570. if (res)
  571. return res;
  572. /* Print our settings */
  573. res = regmap_read(regmap, DS3232_REG_CR, &tmp);
  574. if (res)
  575. return res;
  576. dev_info(&spi->dev, "Control Reg: 0x%02x\n", tmp);
  577. res = regmap_read(regmap, DS3232_REG_SR, &tmp);
  578. if (res)
  579. return res;
  580. dev_info(&spi->dev, "Ctrl/Stat Reg: 0x%02x\n", tmp);
  581. return ds3232_probe(&spi->dev, regmap, spi->irq, "ds3234");
  582. }
  583. static struct spi_driver ds3234_driver = {
  584. .driver = {
  585. .name = "ds3234",
  586. },
  587. .probe = ds3234_probe,
  588. };
  589. static int ds3234_register_driver(void)
  590. {
  591. return spi_register_driver(&ds3234_driver);
  592. }
  593. static void ds3234_unregister_driver(void)
  594. {
  595. spi_unregister_driver(&ds3234_driver);
  596. }
  597. #else
  598. static int ds3234_register_driver(void)
  599. {
  600. return 0;
  601. }
  602. static void ds3234_unregister_driver(void)
  603. {
  604. }
  605. #endif
  606. static int __init ds323x_init(void)
  607. {
  608. int ret;
  609. ret = ds3232_register_driver();
  610. if (ret) {
  611. pr_err("Failed to register ds3232 driver: %d\n", ret);
  612. return ret;
  613. }
  614. ret = ds3234_register_driver();
  615. if (ret) {
  616. pr_err("Failed to register ds3234 driver: %d\n", ret);
  617. ds3232_unregister_driver();
  618. }
  619. return ret;
  620. }
  621. module_init(ds323x_init)
  622. static void __exit ds323x_exit(void)
  623. {
  624. ds3234_unregister_driver();
  625. ds3232_unregister_driver();
  626. }
  627. module_exit(ds323x_exit)
  628. MODULE_AUTHOR("Srikanth Srinivasan <srikanth.srinivasan@freescale.com>");
  629. MODULE_AUTHOR("Dennis Aberilla <denzzzhome@yahoo.com>");
  630. MODULE_DESCRIPTION("Maxim/Dallas DS3232/DS3234 RTC Driver");
  631. MODULE_LICENSE("GPL");
  632. MODULE_ALIAS("spi:ds3234");