rtc-ds1343.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* rtc-ds1343.c
  3. *
  4. * Driver for Dallas Semiconductor DS1343 Low Current, SPI Compatible
  5. * Real Time Clock
  6. *
  7. * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>
  8. * Ankur Srivastava <sankurece@gmail.com> : DS1343 Nvram Support
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/device.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/regmap.h>
  16. #include <linux/rtc.h>
  17. #include <linux/bcd.h>
  18. #include <linux/pm.h>
  19. #include <linux/pm_wakeirq.h>
  20. #include <linux/slab.h>
  21. #define DALLAS_MAXIM_DS1343 0
  22. #define DALLAS_MAXIM_DS1344 1
  23. /* RTC DS1343 Registers */
  24. #define DS1343_SECONDS_REG 0x00
  25. #define DS1343_MINUTES_REG 0x01
  26. #define DS1343_HOURS_REG 0x02
  27. #define DS1343_DAY_REG 0x03
  28. #define DS1343_DATE_REG 0x04
  29. #define DS1343_MONTH_REG 0x05
  30. #define DS1343_YEAR_REG 0x06
  31. #define DS1343_ALM0_SEC_REG 0x07
  32. #define DS1343_ALM0_MIN_REG 0x08
  33. #define DS1343_ALM0_HOUR_REG 0x09
  34. #define DS1343_ALM0_DAY_REG 0x0A
  35. #define DS1343_ALM1_SEC_REG 0x0B
  36. #define DS1343_ALM1_MIN_REG 0x0C
  37. #define DS1343_ALM1_HOUR_REG 0x0D
  38. #define DS1343_ALM1_DAY_REG 0x0E
  39. #define DS1343_CONTROL_REG 0x0F
  40. #define DS1343_STATUS_REG 0x10
  41. #define DS1343_TRICKLE_REG 0x11
  42. #define DS1343_NVRAM 0x20
  43. #define DS1343_NVRAM_LEN 96
  44. /* DS1343 Control Registers bits */
  45. #define DS1343_EOSC 0x80
  46. #define DS1343_DOSF 0x20
  47. #define DS1343_EGFIL 0x10
  48. #define DS1343_SQW 0x08
  49. #define DS1343_INTCN 0x04
  50. #define DS1343_A1IE 0x02
  51. #define DS1343_A0IE 0x01
  52. /* DS1343 Status Registers bits */
  53. #define DS1343_OSF 0x80
  54. #define DS1343_IRQF1 0x02
  55. #define DS1343_IRQF0 0x01
  56. /* DS1343 Trickle Charger Registers bits */
  57. #define DS1343_TRICKLE_MAGIC 0xa0
  58. #define DS1343_TRICKLE_DS1 0x08
  59. #define DS1343_TRICKLE_1K 0x01
  60. #define DS1343_TRICKLE_2K 0x02
  61. #define DS1343_TRICKLE_4K 0x03
  62. static const struct spi_device_id ds1343_id[] = {
  63. { "ds1343", DALLAS_MAXIM_DS1343 },
  64. { "ds1344", DALLAS_MAXIM_DS1344 },
  65. { }
  66. };
  67. MODULE_DEVICE_TABLE(spi, ds1343_id);
  68. struct ds1343_priv {
  69. struct rtc_device *rtc;
  70. struct regmap *map;
  71. int irq;
  72. };
  73. static ssize_t ds1343_show_glitchfilter(struct device *dev,
  74. struct device_attribute *attr, char *buf)
  75. {
  76. struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
  77. int glitch_filt_status, data;
  78. int res;
  79. res = regmap_read(priv->map, DS1343_CONTROL_REG, &data);
  80. if (res)
  81. return res;
  82. glitch_filt_status = !!(data & DS1343_EGFIL);
  83. if (glitch_filt_status)
  84. return sprintf(buf, "enabled\n");
  85. else
  86. return sprintf(buf, "disabled\n");
  87. }
  88. static ssize_t ds1343_store_glitchfilter(struct device *dev,
  89. struct device_attribute *attr,
  90. const char *buf, size_t count)
  91. {
  92. struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
  93. int data = 0;
  94. int res;
  95. if (strncmp(buf, "enabled", 7) == 0)
  96. data = DS1343_EGFIL;
  97. else if (strncmp(buf, "disabled", 8))
  98. return -EINVAL;
  99. res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
  100. DS1343_EGFIL, data);
  101. if (res)
  102. return res;
  103. return count;
  104. }
  105. static DEVICE_ATTR(glitch_filter, S_IRUGO | S_IWUSR, ds1343_show_glitchfilter,
  106. ds1343_store_glitchfilter);
  107. static int ds1343_nvram_write(void *priv, unsigned int off, void *val,
  108. size_t bytes)
  109. {
  110. struct ds1343_priv *ds1343 = priv;
  111. return regmap_bulk_write(ds1343->map, DS1343_NVRAM + off, val, bytes);
  112. }
  113. static int ds1343_nvram_read(void *priv, unsigned int off, void *val,
  114. size_t bytes)
  115. {
  116. struct ds1343_priv *ds1343 = priv;
  117. return regmap_bulk_read(ds1343->map, DS1343_NVRAM + off, val, bytes);
  118. }
  119. static ssize_t ds1343_show_tricklecharger(struct device *dev,
  120. struct device_attribute *attr, char *buf)
  121. {
  122. struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
  123. int res, data;
  124. char *diodes = "disabled", *resistors = " ";
  125. res = regmap_read(priv->map, DS1343_TRICKLE_REG, &data);
  126. if (res)
  127. return res;
  128. if ((data & 0xf0) == DS1343_TRICKLE_MAGIC) {
  129. switch (data & 0x0c) {
  130. case DS1343_TRICKLE_DS1:
  131. diodes = "one diode,";
  132. break;
  133. default:
  134. diodes = "no diode,";
  135. break;
  136. }
  137. switch (data & 0x03) {
  138. case DS1343_TRICKLE_1K:
  139. resistors = "1k Ohm";
  140. break;
  141. case DS1343_TRICKLE_2K:
  142. resistors = "2k Ohm";
  143. break;
  144. case DS1343_TRICKLE_4K:
  145. resistors = "4k Ohm";
  146. break;
  147. default:
  148. diodes = "disabled";
  149. break;
  150. }
  151. }
  152. return sprintf(buf, "%s %s\n", diodes, resistors);
  153. }
  154. static DEVICE_ATTR(trickle_charger, S_IRUGO, ds1343_show_tricklecharger, NULL);
  155. static struct attribute *ds1343_attrs[] = {
  156. &dev_attr_glitch_filter.attr,
  157. &dev_attr_trickle_charger.attr,
  158. NULL
  159. };
  160. static const struct attribute_group ds1343_attr_group = {
  161. .attrs = ds1343_attrs,
  162. };
  163. static int ds1343_read_time(struct device *dev, struct rtc_time *dt)
  164. {
  165. struct ds1343_priv *priv = dev_get_drvdata(dev);
  166. unsigned char buf[7];
  167. int res;
  168. res = regmap_bulk_read(priv->map, DS1343_SECONDS_REG, buf, 7);
  169. if (res)
  170. return res;
  171. dt->tm_sec = bcd2bin(buf[0]);
  172. dt->tm_min = bcd2bin(buf[1]);
  173. dt->tm_hour = bcd2bin(buf[2] & 0x3F);
  174. dt->tm_wday = bcd2bin(buf[3]) - 1;
  175. dt->tm_mday = bcd2bin(buf[4]);
  176. dt->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
  177. dt->tm_year = bcd2bin(buf[6]) + 100; /* year offset from 1900 */
  178. return 0;
  179. }
  180. static int ds1343_set_time(struct device *dev, struct rtc_time *dt)
  181. {
  182. struct ds1343_priv *priv = dev_get_drvdata(dev);
  183. u8 buf[7];
  184. buf[0] = bin2bcd(dt->tm_sec);
  185. buf[1] = bin2bcd(dt->tm_min);
  186. buf[2] = bin2bcd(dt->tm_hour) & 0x3F;
  187. buf[3] = bin2bcd(dt->tm_wday + 1);
  188. buf[4] = bin2bcd(dt->tm_mday);
  189. buf[5] = bin2bcd(dt->tm_mon + 1);
  190. buf[6] = bin2bcd(dt->tm_year - 100);
  191. return regmap_bulk_write(priv->map, DS1343_SECONDS_REG,
  192. buf, sizeof(buf));
  193. }
  194. static int ds1343_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  195. {
  196. struct ds1343_priv *priv = dev_get_drvdata(dev);
  197. unsigned char buf[4];
  198. unsigned int val;
  199. int res;
  200. if (priv->irq <= 0)
  201. return -EINVAL;
  202. res = regmap_read(priv->map, DS1343_STATUS_REG, &val);
  203. if (res)
  204. return res;
  205. alarm->pending = !!(val & DS1343_IRQF0);
  206. res = regmap_read(priv->map, DS1343_CONTROL_REG, &val);
  207. if (res)
  208. return res;
  209. alarm->enabled = !!(val & DS1343_A0IE);
  210. res = regmap_bulk_read(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
  211. if (res)
  212. return res;
  213. alarm->time.tm_sec = bcd2bin(buf[0]) & 0x7f;
  214. alarm->time.tm_min = bcd2bin(buf[1]) & 0x7f;
  215. alarm->time.tm_hour = bcd2bin(buf[2]) & 0x3f;
  216. alarm->time.tm_mday = bcd2bin(buf[3]) & 0x3f;
  217. return 0;
  218. }
  219. static int ds1343_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  220. {
  221. struct ds1343_priv *priv = dev_get_drvdata(dev);
  222. unsigned char buf[4];
  223. int res = 0;
  224. if (priv->irq <= 0)
  225. return -EINVAL;
  226. res = regmap_update_bits(priv->map, DS1343_CONTROL_REG, DS1343_A0IE, 0);
  227. if (res)
  228. return res;
  229. buf[0] = bin2bcd(alarm->time.tm_sec);
  230. buf[1] = bin2bcd(alarm->time.tm_min);
  231. buf[2] = bin2bcd(alarm->time.tm_hour);
  232. buf[3] = bin2bcd(alarm->time.tm_mday);
  233. res = regmap_bulk_write(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
  234. if (res)
  235. return res;
  236. if (alarm->enabled)
  237. res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
  238. DS1343_A0IE, DS1343_A0IE);
  239. return res;
  240. }
  241. static int ds1343_alarm_irq_enable(struct device *dev, unsigned int enabled)
  242. {
  243. struct ds1343_priv *priv = dev_get_drvdata(dev);
  244. if (priv->irq <= 0)
  245. return -EINVAL;
  246. return regmap_update_bits(priv->map, DS1343_CONTROL_REG,
  247. DS1343_A0IE, enabled ? DS1343_A0IE : 0);
  248. }
  249. static irqreturn_t ds1343_thread(int irq, void *dev_id)
  250. {
  251. struct ds1343_priv *priv = dev_id;
  252. unsigned int stat;
  253. int res = 0;
  254. rtc_lock(priv->rtc);
  255. res = regmap_read(priv->map, DS1343_STATUS_REG, &stat);
  256. if (res)
  257. goto out;
  258. if (stat & DS1343_IRQF0) {
  259. stat &= ~DS1343_IRQF0;
  260. regmap_write(priv->map, DS1343_STATUS_REG, stat);
  261. rtc_update_irq(priv->rtc, 1, RTC_AF | RTC_IRQF);
  262. regmap_update_bits(priv->map, DS1343_CONTROL_REG,
  263. DS1343_A0IE, 0);
  264. }
  265. out:
  266. rtc_unlock(priv->rtc);
  267. return IRQ_HANDLED;
  268. }
  269. static const struct rtc_class_ops ds1343_rtc_ops = {
  270. .read_time = ds1343_read_time,
  271. .set_time = ds1343_set_time,
  272. .read_alarm = ds1343_read_alarm,
  273. .set_alarm = ds1343_set_alarm,
  274. .alarm_irq_enable = ds1343_alarm_irq_enable,
  275. };
  276. static int ds1343_probe(struct spi_device *spi)
  277. {
  278. struct ds1343_priv *priv;
  279. struct regmap_config config = { .reg_bits = 8, .val_bits = 8,
  280. .write_flag_mask = 0x80, };
  281. unsigned int data;
  282. int res;
  283. struct nvmem_config nvmem_cfg = {
  284. .name = "ds1343-",
  285. .word_size = 1,
  286. .stride = 1,
  287. .size = DS1343_NVRAM_LEN,
  288. .reg_read = ds1343_nvram_read,
  289. .reg_write = ds1343_nvram_write,
  290. };
  291. priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL);
  292. if (!priv)
  293. return -ENOMEM;
  294. /* RTC DS1347 works in spi mode 3 and
  295. * its chip select is active high. Active high should be defined as
  296. * "inverse polarity" as GPIO-based chip selects can be logically
  297. * active high but inverted by the GPIO library.
  298. */
  299. spi->mode |= SPI_MODE_3;
  300. spi->mode ^= SPI_CS_HIGH;
  301. spi->bits_per_word = 8;
  302. res = spi_setup(spi);
  303. if (res)
  304. return res;
  305. spi_set_drvdata(spi, priv);
  306. priv->map = devm_regmap_init_spi(spi, &config);
  307. if (IS_ERR(priv->map)) {
  308. dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n");
  309. return PTR_ERR(priv->map);
  310. }
  311. res = regmap_read(priv->map, DS1343_SECONDS_REG, &data);
  312. if (res)
  313. return res;
  314. regmap_read(priv->map, DS1343_CONTROL_REG, &data);
  315. data |= DS1343_INTCN;
  316. data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE);
  317. regmap_write(priv->map, DS1343_CONTROL_REG, data);
  318. regmap_read(priv->map, DS1343_STATUS_REG, &data);
  319. data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0);
  320. regmap_write(priv->map, DS1343_STATUS_REG, data);
  321. priv->rtc = devm_rtc_allocate_device(&spi->dev);
  322. if (IS_ERR(priv->rtc))
  323. return PTR_ERR(priv->rtc);
  324. priv->rtc->nvram_old_abi = true;
  325. priv->rtc->ops = &ds1343_rtc_ops;
  326. priv->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  327. priv->rtc->range_max = RTC_TIMESTAMP_END_2099;
  328. res = rtc_add_group(priv->rtc, &ds1343_attr_group);
  329. if (res)
  330. dev_err(&spi->dev,
  331. "unable to create sysfs entries for rtc ds1343\n");
  332. res = rtc_register_device(priv->rtc);
  333. if (res)
  334. return res;
  335. nvmem_cfg.priv = priv;
  336. rtc_nvmem_register(priv->rtc, &nvmem_cfg);
  337. priv->irq = spi->irq;
  338. if (priv->irq >= 0) {
  339. res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
  340. ds1343_thread, IRQF_ONESHOT,
  341. "ds1343", priv);
  342. if (res) {
  343. priv->irq = -1;
  344. dev_err(&spi->dev,
  345. "unable to request irq for rtc ds1343\n");
  346. } else {
  347. device_init_wakeup(&spi->dev, true);
  348. dev_pm_set_wake_irq(&spi->dev, spi->irq);
  349. }
  350. }
  351. return 0;
  352. }
  353. static int ds1343_remove(struct spi_device *spi)
  354. {
  355. dev_pm_clear_wake_irq(&spi->dev);
  356. return 0;
  357. }
  358. #ifdef CONFIG_PM_SLEEP
  359. static int ds1343_suspend(struct device *dev)
  360. {
  361. struct spi_device *spi = to_spi_device(dev);
  362. if (spi->irq >= 0 && device_may_wakeup(dev))
  363. enable_irq_wake(spi->irq);
  364. return 0;
  365. }
  366. static int ds1343_resume(struct device *dev)
  367. {
  368. struct spi_device *spi = to_spi_device(dev);
  369. if (spi->irq >= 0 && device_may_wakeup(dev))
  370. disable_irq_wake(spi->irq);
  371. return 0;
  372. }
  373. #endif
  374. static SIMPLE_DEV_PM_OPS(ds1343_pm, ds1343_suspend, ds1343_resume);
  375. static struct spi_driver ds1343_driver = {
  376. .driver = {
  377. .name = "ds1343",
  378. .pm = &ds1343_pm,
  379. },
  380. .probe = ds1343_probe,
  381. .remove = ds1343_remove,
  382. .id_table = ds1343_id,
  383. };
  384. module_spi_driver(ds1343_driver);
  385. MODULE_DESCRIPTION("DS1343 RTC SPI Driver");
  386. MODULE_AUTHOR("Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>,"
  387. "Ankur Srivastava <sankurece@gmail.com>");
  388. MODULE_LICENSE("GPL v2");