rtc-ds1305.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
  4. *
  5. * Copyright (C) 2008 David Brownell
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/bcd.h>
  10. #include <linux/slab.h>
  11. #include <linux/rtc.h>
  12. #include <linux/workqueue.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/ds1305.h>
  15. #include <linux/module.h>
  16. /*
  17. * Registers ... mask DS1305_WRITE into register address to write,
  18. * otherwise you're reading it. All non-bitmask values are BCD.
  19. */
  20. #define DS1305_WRITE 0x80
  21. /* RTC date/time ... the main special cases are that we:
  22. * - Need fancy "hours" encoding in 12hour mode
  23. * - Don't rely on the "day-of-week" field (or tm_wday)
  24. * - Are a 21st-century clock (2000 <= year < 2100)
  25. */
  26. #define DS1305_RTC_LEN 7 /* bytes for RTC regs */
  27. #define DS1305_SEC 0x00 /* register addresses */
  28. #define DS1305_MIN 0x01
  29. #define DS1305_HOUR 0x02
  30. # define DS1305_HR_12 0x40 /* set == 12 hr mode */
  31. # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
  32. #define DS1305_WDAY 0x03
  33. #define DS1305_MDAY 0x04
  34. #define DS1305_MON 0x05
  35. #define DS1305_YEAR 0x06
  36. /* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
  37. * DS1305_ALM_DISABLE disables a match field (some combos are bad).
  38. *
  39. * NOTE that since we don't use WDAY, we limit ourselves to alarms
  40. * only one day into the future (vs potentially up to a week).
  41. *
  42. * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
  43. * don't currently support them. We'd either need to do it only when
  44. * no alarm is pending (not the standard model), or to use the second
  45. * alarm (implying that this is a DS1305 not DS1306, *and* that either
  46. * it's wired up a second IRQ we know, or that INTCN is set)
  47. */
  48. #define DS1305_ALM_LEN 4 /* bytes for ALM regs */
  49. #define DS1305_ALM_DISABLE 0x80
  50. #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
  51. #define DS1305_ALM1(r) (0x0b + (r))
  52. /* three control registers */
  53. #define DS1305_CONTROL_LEN 3 /* bytes of control regs */
  54. #define DS1305_CONTROL 0x0f /* register addresses */
  55. # define DS1305_nEOSC 0x80 /* low enables oscillator */
  56. # define DS1305_WP 0x40 /* write protect */
  57. # define DS1305_INTCN 0x04 /* clear == only int0 used */
  58. # define DS1306_1HZ 0x04 /* enable 1Hz output */
  59. # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
  60. # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
  61. #define DS1305_STATUS 0x10
  62. /* status has just AEIx bits, mirrored as IRQFx */
  63. #define DS1305_TRICKLE 0x11
  64. /* trickle bits are defined in <linux/spi/ds1305.h> */
  65. /* a bunch of NVRAM */
  66. #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
  67. #define DS1305_NVRAM 0x20 /* register addresses */
  68. struct ds1305 {
  69. struct spi_device *spi;
  70. struct rtc_device *rtc;
  71. struct work_struct work;
  72. unsigned long flags;
  73. #define FLAG_EXITING 0
  74. bool hr12;
  75. u8 ctrl[DS1305_CONTROL_LEN];
  76. };
  77. /*----------------------------------------------------------------------*/
  78. /*
  79. * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
  80. * software (like a bootloader) which may require it.
  81. */
  82. static unsigned bcd2hour(u8 bcd)
  83. {
  84. if (bcd & DS1305_HR_12) {
  85. unsigned hour = 0;
  86. bcd &= ~DS1305_HR_12;
  87. if (bcd & DS1305_HR_PM) {
  88. hour = 12;
  89. bcd &= ~DS1305_HR_PM;
  90. }
  91. hour += bcd2bin(bcd);
  92. return hour - 1;
  93. }
  94. return bcd2bin(bcd);
  95. }
  96. static u8 hour2bcd(bool hr12, int hour)
  97. {
  98. if (hr12) {
  99. hour++;
  100. if (hour <= 12)
  101. return DS1305_HR_12 | bin2bcd(hour);
  102. hour -= 12;
  103. return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
  104. }
  105. return bin2bcd(hour);
  106. }
  107. /*----------------------------------------------------------------------*/
  108. /*
  109. * Interface to RTC framework
  110. */
  111. static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
  112. {
  113. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  114. u8 buf[2];
  115. long err = -EINVAL;
  116. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  117. buf[1] = ds1305->ctrl[0];
  118. if (enabled) {
  119. if (ds1305->ctrl[0] & DS1305_AEI0)
  120. goto done;
  121. buf[1] |= DS1305_AEI0;
  122. } else {
  123. if (!(buf[1] & DS1305_AEI0))
  124. goto done;
  125. buf[1] &= ~DS1305_AEI0;
  126. }
  127. err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
  128. if (err >= 0)
  129. ds1305->ctrl[0] = buf[1];
  130. done:
  131. return err;
  132. }
  133. /*
  134. * Get/set of date and time is pretty normal.
  135. */
  136. static int ds1305_get_time(struct device *dev, struct rtc_time *time)
  137. {
  138. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  139. u8 addr = DS1305_SEC;
  140. u8 buf[DS1305_RTC_LEN];
  141. int status;
  142. /* Use write-then-read to get all the date/time registers
  143. * since dma from stack is nonportable
  144. */
  145. status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
  146. buf, sizeof(buf));
  147. if (status < 0)
  148. return status;
  149. dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
  150. /* Decode the registers */
  151. time->tm_sec = bcd2bin(buf[DS1305_SEC]);
  152. time->tm_min = bcd2bin(buf[DS1305_MIN]);
  153. time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
  154. time->tm_wday = buf[DS1305_WDAY] - 1;
  155. time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
  156. time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
  157. time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
  158. dev_vdbg(dev, "%s secs=%d, mins=%d, "
  159. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  160. "read", time->tm_sec, time->tm_min,
  161. time->tm_hour, time->tm_mday,
  162. time->tm_mon, time->tm_year, time->tm_wday);
  163. return 0;
  164. }
  165. static int ds1305_set_time(struct device *dev, struct rtc_time *time)
  166. {
  167. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  168. u8 buf[1 + DS1305_RTC_LEN];
  169. u8 *bp = buf;
  170. dev_vdbg(dev, "%s secs=%d, mins=%d, "
  171. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  172. "write", time->tm_sec, time->tm_min,
  173. time->tm_hour, time->tm_mday,
  174. time->tm_mon, time->tm_year, time->tm_wday);
  175. /* Write registers starting at the first time/date address. */
  176. *bp++ = DS1305_WRITE | DS1305_SEC;
  177. *bp++ = bin2bcd(time->tm_sec);
  178. *bp++ = bin2bcd(time->tm_min);
  179. *bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
  180. *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
  181. *bp++ = bin2bcd(time->tm_mday);
  182. *bp++ = bin2bcd(time->tm_mon + 1);
  183. *bp++ = bin2bcd(time->tm_year - 100);
  184. dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
  185. /* use write-then-read since dma from stack is nonportable */
  186. return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
  187. NULL, 0);
  188. }
  189. /*
  190. * Get/set of alarm is a bit funky:
  191. *
  192. * - First there's the inherent raciness of getting the (partitioned)
  193. * status of an alarm that could trigger while we're reading parts
  194. * of that status.
  195. *
  196. * - Second there's its limited range (we could increase it a bit by
  197. * relying on WDAY), which means it will easily roll over.
  198. *
  199. * - Third there's the choice of two alarms and alarm signals.
  200. * Here we use ALM0 and expect that nINT0 (open drain) is used;
  201. * that's the only real option for DS1306 runtime alarms, and is
  202. * natural on DS1305.
  203. *
  204. * - Fourth, there's also ALM1, and a second interrupt signal:
  205. * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
  206. * + On DS1306 ALM1 only uses INT1 (an active high pulse)
  207. * and it won't work when VCC1 is active.
  208. *
  209. * So to be most general, we should probably set both alarms to the
  210. * same value, letting ALM1 be the wakeup event source on DS1306
  211. * and handling several wiring options on DS1305.
  212. *
  213. * - Fifth, we support the polled mode (as well as possible; why not?)
  214. * even when no interrupt line is wired to an IRQ.
  215. */
  216. /*
  217. * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
  218. */
  219. static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
  220. {
  221. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  222. struct spi_device *spi = ds1305->spi;
  223. u8 addr;
  224. int status;
  225. u8 buf[DS1305_ALM_LEN];
  226. /* Refresh control register cache BEFORE reading ALM0 registers,
  227. * since reading alarm registers acks any pending IRQ. That
  228. * makes returning "pending" status a bit of a lie, but that bit
  229. * of EFI status is at best fragile anyway (given IRQ handlers).
  230. */
  231. addr = DS1305_CONTROL;
  232. status = spi_write_then_read(spi, &addr, sizeof(addr),
  233. ds1305->ctrl, sizeof(ds1305->ctrl));
  234. if (status < 0)
  235. return status;
  236. alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
  237. alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
  238. /* get and check ALM0 registers */
  239. addr = DS1305_ALM0(DS1305_SEC);
  240. status = spi_write_then_read(spi, &addr, sizeof(addr),
  241. buf, sizeof(buf));
  242. if (status < 0)
  243. return status;
  244. dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
  245. "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
  246. buf[DS1305_HOUR], buf[DS1305_WDAY]);
  247. if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
  248. || (DS1305_ALM_DISABLE & buf[DS1305_MIN])
  249. || (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
  250. return -EIO;
  251. /* Stuff these values into alm->time and let RTC framework code
  252. * fill in the rest ... and also handle rollover to tomorrow when
  253. * that's needed.
  254. */
  255. alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
  256. alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
  257. alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
  258. return 0;
  259. }
  260. /*
  261. * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
  262. */
  263. static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  264. {
  265. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  266. struct spi_device *spi = ds1305->spi;
  267. unsigned long now, later;
  268. struct rtc_time tm;
  269. int status;
  270. u8 buf[1 + DS1305_ALM_LEN];
  271. /* convert desired alarm to time_t */
  272. later = rtc_tm_to_time64(&alm->time);
  273. /* Read current time as time_t */
  274. status = ds1305_get_time(dev, &tm);
  275. if (status < 0)
  276. return status;
  277. now = rtc_tm_to_time64(&tm);
  278. /* make sure alarm fires within the next 24 hours */
  279. if (later <= now)
  280. return -EINVAL;
  281. if ((later - now) > 24 * 60 * 60)
  282. return -EDOM;
  283. /* disable alarm if needed */
  284. if (ds1305->ctrl[0] & DS1305_AEI0) {
  285. ds1305->ctrl[0] &= ~DS1305_AEI0;
  286. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  287. buf[1] = ds1305->ctrl[0];
  288. status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
  289. if (status < 0)
  290. return status;
  291. }
  292. /* write alarm */
  293. buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
  294. buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
  295. buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
  296. buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
  297. buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
  298. dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
  299. "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
  300. buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
  301. status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
  302. if (status < 0)
  303. return status;
  304. /* enable alarm if requested */
  305. if (alm->enabled) {
  306. ds1305->ctrl[0] |= DS1305_AEI0;
  307. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  308. buf[1] = ds1305->ctrl[0];
  309. status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
  310. }
  311. return status;
  312. }
  313. #ifdef CONFIG_PROC_FS
  314. static int ds1305_proc(struct device *dev, struct seq_file *seq)
  315. {
  316. struct ds1305 *ds1305 = dev_get_drvdata(dev);
  317. char *diodes = "no";
  318. char *resistors = "";
  319. /* ctrl[2] is treated as read-only; no locking needed */
  320. if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
  321. switch (ds1305->ctrl[2] & 0x0c) {
  322. case DS1305_TRICKLE_DS2:
  323. diodes = "2 diodes, ";
  324. break;
  325. case DS1305_TRICKLE_DS1:
  326. diodes = "1 diode, ";
  327. break;
  328. default:
  329. goto done;
  330. }
  331. switch (ds1305->ctrl[2] & 0x03) {
  332. case DS1305_TRICKLE_2K:
  333. resistors = "2k Ohm";
  334. break;
  335. case DS1305_TRICKLE_4K:
  336. resistors = "4k Ohm";
  337. break;
  338. case DS1305_TRICKLE_8K:
  339. resistors = "8k Ohm";
  340. break;
  341. default:
  342. diodes = "no";
  343. break;
  344. }
  345. }
  346. done:
  347. seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
  348. return 0;
  349. }
  350. #else
  351. #define ds1305_proc NULL
  352. #endif
  353. static const struct rtc_class_ops ds1305_ops = {
  354. .read_time = ds1305_get_time,
  355. .set_time = ds1305_set_time,
  356. .read_alarm = ds1305_get_alarm,
  357. .set_alarm = ds1305_set_alarm,
  358. .proc = ds1305_proc,
  359. .alarm_irq_enable = ds1305_alarm_irq_enable,
  360. };
  361. static void ds1305_work(struct work_struct *work)
  362. {
  363. struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
  364. struct mutex *lock = &ds1305->rtc->ops_lock;
  365. struct spi_device *spi = ds1305->spi;
  366. u8 buf[3];
  367. int status;
  368. /* lock to protect ds1305->ctrl */
  369. mutex_lock(lock);
  370. /* Disable the IRQ, and clear its status ... for now, we "know"
  371. * that if more than one alarm is active, they're in sync.
  372. * Note that reading ALM data registers also clears IRQ status.
  373. */
  374. ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
  375. ds1305->ctrl[1] = 0;
  376. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  377. buf[1] = ds1305->ctrl[0];
  378. buf[2] = 0;
  379. status = spi_write_then_read(spi, buf, sizeof(buf),
  380. NULL, 0);
  381. if (status < 0)
  382. dev_dbg(&spi->dev, "clear irq --> %d\n", status);
  383. mutex_unlock(lock);
  384. if (!test_bit(FLAG_EXITING, &ds1305->flags))
  385. enable_irq(spi->irq);
  386. rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
  387. }
  388. /*
  389. * This "real" IRQ handler hands off to a workqueue mostly to allow
  390. * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
  391. * I/O requests in IRQ context (to clear the IRQ status).
  392. */
  393. static irqreturn_t ds1305_irq(int irq, void *p)
  394. {
  395. struct ds1305 *ds1305 = p;
  396. disable_irq(irq);
  397. schedule_work(&ds1305->work);
  398. return IRQ_HANDLED;
  399. }
  400. /*----------------------------------------------------------------------*/
  401. /*
  402. * Interface for NVRAM
  403. */
  404. static void msg_init(struct spi_message *m, struct spi_transfer *x,
  405. u8 *addr, size_t count, char *tx, char *rx)
  406. {
  407. spi_message_init(m);
  408. memset(x, 0, 2 * sizeof(*x));
  409. x->tx_buf = addr;
  410. x->len = 1;
  411. spi_message_add_tail(x, m);
  412. x++;
  413. x->tx_buf = tx;
  414. x->rx_buf = rx;
  415. x->len = count;
  416. spi_message_add_tail(x, m);
  417. }
  418. static int ds1305_nvram_read(void *priv, unsigned int off, void *buf,
  419. size_t count)
  420. {
  421. struct ds1305 *ds1305 = priv;
  422. struct spi_device *spi = ds1305->spi;
  423. u8 addr;
  424. struct spi_message m;
  425. struct spi_transfer x[2];
  426. addr = DS1305_NVRAM + off;
  427. msg_init(&m, x, &addr, count, NULL, buf);
  428. return spi_sync(spi, &m);
  429. }
  430. static int ds1305_nvram_write(void *priv, unsigned int off, void *buf,
  431. size_t count)
  432. {
  433. struct ds1305 *ds1305 = priv;
  434. struct spi_device *spi = ds1305->spi;
  435. u8 addr;
  436. struct spi_message m;
  437. struct spi_transfer x[2];
  438. addr = (DS1305_WRITE | DS1305_NVRAM) + off;
  439. msg_init(&m, x, &addr, count, buf, NULL);
  440. return spi_sync(spi, &m);
  441. }
  442. /*----------------------------------------------------------------------*/
  443. /*
  444. * Interface to SPI stack
  445. */
  446. static int ds1305_probe(struct spi_device *spi)
  447. {
  448. struct ds1305 *ds1305;
  449. int status;
  450. u8 addr, value;
  451. struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
  452. bool write_ctrl = false;
  453. struct nvmem_config ds1305_nvmem_cfg = {
  454. .name = "ds1305_nvram",
  455. .word_size = 1,
  456. .stride = 1,
  457. .size = DS1305_NVRAM_LEN,
  458. .reg_read = ds1305_nvram_read,
  459. .reg_write = ds1305_nvram_write,
  460. };
  461. /* Sanity check board setup data. This may be hooked up
  462. * in 3wire mode, but we don't care. Note that unless
  463. * there's an inverter in place, this needs SPI_CS_HIGH!
  464. */
  465. if ((spi->bits_per_word && spi->bits_per_word != 8)
  466. || (spi->max_speed_hz > 2000000)
  467. || !(spi->mode & SPI_CPHA))
  468. return -EINVAL;
  469. /* set up driver data */
  470. ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
  471. if (!ds1305)
  472. return -ENOMEM;
  473. ds1305->spi = spi;
  474. spi_set_drvdata(spi, ds1305);
  475. /* read and cache control registers */
  476. addr = DS1305_CONTROL;
  477. status = spi_write_then_read(spi, &addr, sizeof(addr),
  478. ds1305->ctrl, sizeof(ds1305->ctrl));
  479. if (status < 0) {
  480. dev_dbg(&spi->dev, "can't %s, %d\n",
  481. "read", status);
  482. return status;
  483. }
  484. dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
  485. /* Sanity check register values ... partially compensating for the
  486. * fact that SPI has no device handshake. A pullup on MISO would
  487. * make these tests fail; but not all systems will have one. If
  488. * some register is neither 0x00 nor 0xff, a chip is likely there.
  489. */
  490. if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
  491. dev_dbg(&spi->dev, "RTC chip is not present\n");
  492. return -ENODEV;
  493. }
  494. if (ds1305->ctrl[2] == 0)
  495. dev_dbg(&spi->dev, "chip may not be present\n");
  496. /* enable writes if needed ... if we were paranoid it would
  497. * make sense to enable them only when absolutely necessary.
  498. */
  499. if (ds1305->ctrl[0] & DS1305_WP) {
  500. u8 buf[2];
  501. ds1305->ctrl[0] &= ~DS1305_WP;
  502. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  503. buf[1] = ds1305->ctrl[0];
  504. status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
  505. dev_dbg(&spi->dev, "clear WP --> %d\n", status);
  506. if (status < 0)
  507. return status;
  508. }
  509. /* on DS1305, maybe start oscillator; like most low power
  510. * oscillators, it may take a second to stabilize
  511. */
  512. if (ds1305->ctrl[0] & DS1305_nEOSC) {
  513. ds1305->ctrl[0] &= ~DS1305_nEOSC;
  514. write_ctrl = true;
  515. dev_warn(&spi->dev, "SET TIME!\n");
  516. }
  517. /* ack any pending IRQs */
  518. if (ds1305->ctrl[1]) {
  519. ds1305->ctrl[1] = 0;
  520. write_ctrl = true;
  521. }
  522. /* this may need one-time (re)init */
  523. if (pdata) {
  524. /* maybe enable trickle charge */
  525. if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
  526. ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
  527. | pdata->trickle;
  528. write_ctrl = true;
  529. }
  530. /* on DS1306, configure 1 Hz signal */
  531. if (pdata->is_ds1306) {
  532. if (pdata->en_1hz) {
  533. if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
  534. ds1305->ctrl[0] |= DS1306_1HZ;
  535. write_ctrl = true;
  536. }
  537. } else {
  538. if (ds1305->ctrl[0] & DS1306_1HZ) {
  539. ds1305->ctrl[0] &= ~DS1306_1HZ;
  540. write_ctrl = true;
  541. }
  542. }
  543. }
  544. }
  545. if (write_ctrl) {
  546. u8 buf[4];
  547. buf[0] = DS1305_WRITE | DS1305_CONTROL;
  548. buf[1] = ds1305->ctrl[0];
  549. buf[2] = ds1305->ctrl[1];
  550. buf[3] = ds1305->ctrl[2];
  551. status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
  552. if (status < 0) {
  553. dev_dbg(&spi->dev, "can't %s, %d\n",
  554. "write", status);
  555. return status;
  556. }
  557. dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
  558. }
  559. /* see if non-Linux software set up AM/PM mode */
  560. addr = DS1305_HOUR;
  561. status = spi_write_then_read(spi, &addr, sizeof(addr),
  562. &value, sizeof(value));
  563. if (status < 0) {
  564. dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
  565. return status;
  566. }
  567. ds1305->hr12 = (DS1305_HR_12 & value) != 0;
  568. if (ds1305->hr12)
  569. dev_dbg(&spi->dev, "AM/PM\n");
  570. /* register RTC ... from here on, ds1305->ctrl needs locking */
  571. ds1305->rtc = devm_rtc_allocate_device(&spi->dev);
  572. if (IS_ERR(ds1305->rtc))
  573. return PTR_ERR(ds1305->rtc);
  574. ds1305->rtc->ops = &ds1305_ops;
  575. ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  576. ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099;
  577. ds1305_nvmem_cfg.priv = ds1305;
  578. ds1305->rtc->nvram_old_abi = true;
  579. status = rtc_register_device(ds1305->rtc);
  580. if (status)
  581. return status;
  582. rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg);
  583. /* Maybe set up alarm IRQ; be ready to handle it triggering right
  584. * away. NOTE that we don't share this. The signal is active low,
  585. * and we can't ack it before a SPI message delay. We temporarily
  586. * disable the IRQ until it's acked, which lets us work with more
  587. * IRQ trigger modes (not all IRQ controllers can do falling edge).
  588. */
  589. if (spi->irq) {
  590. INIT_WORK(&ds1305->work, ds1305_work);
  591. status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
  592. 0, dev_name(&ds1305->rtc->dev), ds1305);
  593. if (status < 0) {
  594. dev_err(&spi->dev, "request_irq %d --> %d\n",
  595. spi->irq, status);
  596. } else {
  597. device_set_wakeup_capable(&spi->dev, 1);
  598. }
  599. }
  600. return 0;
  601. }
  602. static int ds1305_remove(struct spi_device *spi)
  603. {
  604. struct ds1305 *ds1305 = spi_get_drvdata(spi);
  605. /* carefully shut down irq and workqueue, if present */
  606. if (spi->irq) {
  607. set_bit(FLAG_EXITING, &ds1305->flags);
  608. devm_free_irq(&spi->dev, spi->irq, ds1305);
  609. cancel_work_sync(&ds1305->work);
  610. }
  611. return 0;
  612. }
  613. static struct spi_driver ds1305_driver = {
  614. .driver.name = "rtc-ds1305",
  615. .probe = ds1305_probe,
  616. .remove = ds1305_remove,
  617. /* REVISIT add suspend/resume */
  618. };
  619. module_spi_driver(ds1305_driver);
  620. MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
  621. MODULE_LICENSE("GPL");
  622. MODULE_ALIAS("spi:rtc-ds1305");