rtc-ds1302.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Dallas DS1302 RTC Support
  4. *
  5. * Copyright (C) 2002 David McCullough
  6. * Copyright (C) 2003 - 2007 Paul Mundt
  7. */
  8. #include <linux/bcd.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/rtc.h>
  15. #include <linux/spi/spi.h>
  16. #define RTC_CMD_READ 0x81 /* Read command */
  17. #define RTC_CMD_WRITE 0x80 /* Write command */
  18. #define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
  19. #define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
  20. #define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
  21. #define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
  22. #define RTC_CLCK_BURST 0x1F /* Address of clock burst */
  23. #define RTC_CLCK_LEN 0x08 /* Size of clock burst */
  24. #define RTC_ADDR_CTRL 0x07 /* Address of control register */
  25. #define RTC_ADDR_YEAR 0x06 /* Address of year register */
  26. #define RTC_ADDR_DAY 0x05 /* Address of day of week register */
  27. #define RTC_ADDR_MON 0x04 /* Address of month register */
  28. #define RTC_ADDR_DATE 0x03 /* Address of day of month register */
  29. #define RTC_ADDR_HOUR 0x02 /* Address of hour register */
  30. #define RTC_ADDR_MIN 0x01 /* Address of minute register */
  31. #define RTC_ADDR_SEC 0x00 /* Address of second register */
  32. static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
  33. {
  34. struct spi_device *spi = dev_get_drvdata(dev);
  35. u8 buf[1 + RTC_CLCK_LEN];
  36. u8 *bp;
  37. int status;
  38. /* Enable writing */
  39. bp = buf;
  40. *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
  41. *bp++ = RTC_CMD_WRITE_ENABLE;
  42. status = spi_write_then_read(spi, buf, 2,
  43. NULL, 0);
  44. if (status)
  45. return status;
  46. /* Write registers starting at the first time/date address. */
  47. bp = buf;
  48. *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
  49. *bp++ = bin2bcd(time->tm_sec);
  50. *bp++ = bin2bcd(time->tm_min);
  51. *bp++ = bin2bcd(time->tm_hour);
  52. *bp++ = bin2bcd(time->tm_mday);
  53. *bp++ = bin2bcd(time->tm_mon + 1);
  54. *bp++ = time->tm_wday + 1;
  55. *bp++ = bin2bcd(time->tm_year % 100);
  56. *bp++ = RTC_CMD_WRITE_DISABLE;
  57. /* use write-then-read since dma from stack is nonportable */
  58. return spi_write_then_read(spi, buf, sizeof(buf),
  59. NULL, 0);
  60. }
  61. static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
  62. {
  63. struct spi_device *spi = dev_get_drvdata(dev);
  64. u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
  65. u8 buf[RTC_CLCK_LEN - 1];
  66. int status;
  67. /* Use write-then-read to get all the date/time registers
  68. * since dma from stack is nonportable
  69. */
  70. status = spi_write_then_read(spi, &addr, sizeof(addr),
  71. buf, sizeof(buf));
  72. if (status < 0)
  73. return status;
  74. /* Decode the registers */
  75. time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
  76. time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
  77. time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
  78. time->tm_wday = buf[RTC_ADDR_DAY] - 1;
  79. time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
  80. time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
  81. time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
  82. return 0;
  83. }
  84. static const struct rtc_class_ops ds1302_rtc_ops = {
  85. .read_time = ds1302_rtc_get_time,
  86. .set_time = ds1302_rtc_set_time,
  87. };
  88. static int ds1302_probe(struct spi_device *spi)
  89. {
  90. struct rtc_device *rtc;
  91. u8 addr;
  92. u8 buf[4];
  93. u8 *bp;
  94. int status;
  95. /* Sanity check board setup data. This may be hooked up
  96. * in 3wire mode, but we don't care. Note that unless
  97. * there's an inverter in place, this needs SPI_CS_HIGH!
  98. */
  99. if (spi->bits_per_word && (spi->bits_per_word != 8)) {
  100. dev_err(&spi->dev, "bad word length\n");
  101. return -EINVAL;
  102. } else if (spi->max_speed_hz > 2000000) {
  103. dev_err(&spi->dev, "speed is too high\n");
  104. return -EINVAL;
  105. } else if (spi->mode & SPI_CPHA) {
  106. dev_err(&spi->dev, "bad mode\n");
  107. return -EINVAL;
  108. }
  109. addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
  110. status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
  111. if (status < 0) {
  112. dev_err(&spi->dev, "control register read error %d\n",
  113. status);
  114. return status;
  115. }
  116. if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
  117. status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
  118. if (status < 0) {
  119. dev_err(&spi->dev, "control register read error %d\n",
  120. status);
  121. return status;
  122. }
  123. if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
  124. dev_err(&spi->dev, "junk in control register\n");
  125. return -ENODEV;
  126. }
  127. }
  128. if (buf[0] == 0) {
  129. bp = buf;
  130. *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
  131. *bp++ = RTC_CMD_WRITE_DISABLE;
  132. status = spi_write_then_read(spi, buf, 2, NULL, 0);
  133. if (status < 0) {
  134. dev_err(&spi->dev, "control register write error %d\n",
  135. status);
  136. return status;
  137. }
  138. addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
  139. status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
  140. if (status < 0) {
  141. dev_err(&spi->dev,
  142. "error %d reading control register\n",
  143. status);
  144. return status;
  145. }
  146. if (buf[0] != RTC_CMD_WRITE_DISABLE) {
  147. dev_err(&spi->dev, "failed to detect chip\n");
  148. return -ENODEV;
  149. }
  150. }
  151. spi_set_drvdata(spi, spi);
  152. rtc = devm_rtc_device_register(&spi->dev, "ds1302",
  153. &ds1302_rtc_ops, THIS_MODULE);
  154. if (IS_ERR(rtc)) {
  155. status = PTR_ERR(rtc);
  156. dev_err(&spi->dev, "error %d registering rtc\n", status);
  157. return status;
  158. }
  159. return 0;
  160. }
  161. static int ds1302_remove(struct spi_device *spi)
  162. {
  163. spi_set_drvdata(spi, NULL);
  164. return 0;
  165. }
  166. #ifdef CONFIG_OF
  167. static const struct of_device_id ds1302_dt_ids[] = {
  168. { .compatible = "maxim,ds1302", },
  169. { /* sentinel */ }
  170. };
  171. MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
  172. #endif
  173. static struct spi_driver ds1302_driver = {
  174. .driver.name = "rtc-ds1302",
  175. .driver.of_match_table = of_match_ptr(ds1302_dt_ids),
  176. .probe = ds1302_probe,
  177. .remove = ds1302_remove,
  178. };
  179. module_spi_driver(ds1302_driver);
  180. MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
  181. MODULE_AUTHOR("Paul Mundt, David McCullough");
  182. MODULE_LICENSE("GPL v2");