rtc-at91sam9.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
  4. *
  5. * (C) 2007 Michel Benoit
  6. *
  7. * Based on rtc-at91rm9200.c by Rick Bronson
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/ioctl.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regmap.h>
  19. #include <linux/rtc.h>
  20. #include <linux/slab.h>
  21. #include <linux/suspend.h>
  22. #include <linux/time.h>
  23. /*
  24. * This driver uses two configurable hardware resources that live in the
  25. * AT91SAM9 backup power domain (intended to be powered at all times)
  26. * to implement the Real Time Clock interfaces
  27. *
  28. * - A "Real-time Timer" (RTT) counts up in seconds from a base time.
  29. * We can't assign the counter value (CRTV) ... but we can reset it.
  30. *
  31. * - One of the "General Purpose Backup Registers" (GPBRs) holds the
  32. * base time, normally an offset from the beginning of the POSIX
  33. * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
  34. * local timezone's offset.
  35. *
  36. * The RTC's value is the RTT counter plus that offset. The RTC's alarm
  37. * is likewise a base (ALMV) plus that offset.
  38. *
  39. * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
  40. * choose from, or a "real" RTC module. All systems have multiple GPBR
  41. * registers available, likewise usable for more than "RTC" support.
  42. */
  43. #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
  44. #define AT91_RTT_RTPRES (0xffff << 0) /* Timer Prescaler Value */
  45. #define AT91_RTT_ALMIEN BIT(16) /* Alarm Interrupt Enable */
  46. #define AT91_RTT_RTTINCIEN BIT(17) /* Increment Interrupt Enable */
  47. #define AT91_RTT_RTTRST BIT(18) /* Timer Restart */
  48. #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
  49. #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
  50. #define AT91_RTT_VR 0x08 /* Real-time Value Register */
  51. #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
  52. #define AT91_RTT_SR 0x0c /* Real-time Status Register */
  53. #define AT91_RTT_ALMS BIT(0) /* Alarm Status */
  54. #define AT91_RTT_RTTINC BIT(1) /* Timer Increment */
  55. /*
  56. * We store ALARM_DISABLED in ALMV to record that no alarm is set.
  57. * It's also the reset value for that field.
  58. */
  59. #define ALARM_DISABLED ((u32)~0)
  60. struct sam9_rtc {
  61. void __iomem *rtt;
  62. struct rtc_device *rtcdev;
  63. u32 imr;
  64. struct regmap *gpbr;
  65. unsigned int gpbr_offset;
  66. int irq;
  67. struct clk *sclk;
  68. bool suspended;
  69. unsigned long events;
  70. spinlock_t lock;
  71. };
  72. #define rtt_readl(rtc, field) \
  73. readl((rtc)->rtt + AT91_RTT_ ## field)
  74. #define rtt_writel(rtc, field, val) \
  75. writel((val), (rtc)->rtt + AT91_RTT_ ## field)
  76. static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
  77. {
  78. unsigned int val;
  79. regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
  80. return val;
  81. }
  82. static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
  83. {
  84. regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
  85. }
  86. /*
  87. * Read current time and date in RTC
  88. */
  89. static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
  90. {
  91. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  92. u32 secs, secs2;
  93. u32 offset;
  94. /* read current time offset */
  95. offset = gpbr_readl(rtc);
  96. if (offset == 0)
  97. return -EILSEQ;
  98. /* reread the counter to help sync the two clock domains */
  99. secs = rtt_readl(rtc, VR);
  100. secs2 = rtt_readl(rtc, VR);
  101. if (secs != secs2)
  102. secs = rtt_readl(rtc, VR);
  103. rtc_time64_to_tm(offset + secs, tm);
  104. dev_dbg(dev, "%s: %ptR\n", __func__, tm);
  105. return 0;
  106. }
  107. /*
  108. * Set current time and date in RTC
  109. */
  110. static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
  111. {
  112. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  113. u32 offset, alarm, mr;
  114. unsigned long secs;
  115. dev_dbg(dev, "%s: %ptR\n", __func__, tm);
  116. secs = rtc_tm_to_time64(tm);
  117. mr = rtt_readl(rtc, MR);
  118. /* disable interrupts */
  119. rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  120. /* read current time offset */
  121. offset = gpbr_readl(rtc);
  122. /* store the new base time in a battery backup register */
  123. secs += 1;
  124. gpbr_writel(rtc, secs);
  125. /* adjust the alarm time for the new base */
  126. alarm = rtt_readl(rtc, AR);
  127. if (alarm != ALARM_DISABLED) {
  128. if (offset > secs) {
  129. /* time jumped backwards, increase time until alarm */
  130. alarm += (offset - secs);
  131. } else if ((alarm + offset) > secs) {
  132. /* time jumped forwards, decrease time until alarm */
  133. alarm -= (secs - offset);
  134. } else {
  135. /* time jumped past the alarm, disable alarm */
  136. alarm = ALARM_DISABLED;
  137. mr &= ~AT91_RTT_ALMIEN;
  138. }
  139. rtt_writel(rtc, AR, alarm);
  140. }
  141. /* reset the timer, and re-enable interrupts */
  142. rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);
  143. return 0;
  144. }
  145. static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
  146. {
  147. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  148. struct rtc_time *tm = &alrm->time;
  149. u32 alarm = rtt_readl(rtc, AR);
  150. u32 offset;
  151. offset = gpbr_readl(rtc);
  152. if (offset == 0)
  153. return -EILSEQ;
  154. memset(alrm, 0, sizeof(*alrm));
  155. if (alarm != ALARM_DISABLED && offset != 0) {
  156. rtc_time64_to_tm(offset + alarm, tm);
  157. dev_dbg(dev, "%s: %ptR\n", __func__, tm);
  158. if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
  159. alrm->enabled = 1;
  160. }
  161. return 0;
  162. }
  163. static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  164. {
  165. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  166. struct rtc_time *tm = &alrm->time;
  167. unsigned long secs;
  168. u32 offset;
  169. u32 mr;
  170. secs = rtc_tm_to_time64(tm);
  171. offset = gpbr_readl(rtc);
  172. if (offset == 0) {
  173. /* time is not set */
  174. return -EILSEQ;
  175. }
  176. mr = rtt_readl(rtc, MR);
  177. rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
  178. /* alarm in the past? finish and leave disabled */
  179. if (secs <= offset) {
  180. rtt_writel(rtc, AR, ALARM_DISABLED);
  181. return 0;
  182. }
  183. /* else set alarm and maybe enable it */
  184. rtt_writel(rtc, AR, secs - offset);
  185. if (alrm->enabled)
  186. rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
  187. dev_dbg(dev, "%s: %ptR\n", __func__, tm);
  188. return 0;
  189. }
  190. static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  191. {
  192. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  193. u32 mr = rtt_readl(rtc, MR);
  194. dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
  195. if (enabled)
  196. rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
  197. else
  198. rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
  199. return 0;
  200. }
  201. /*
  202. * Provide additional RTC information in /proc/driver/rtc
  203. */
  204. static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
  205. {
  206. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  207. u32 mr = rtt_readl(rtc, MR);
  208. seq_printf(seq, "update_IRQ\t: %s\n",
  209. (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
  210. return 0;
  211. }
  212. static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
  213. {
  214. u32 sr, mr;
  215. /* Shared interrupt may be for another device. Note: reading
  216. * SR clears it, so we must only read it in this irq handler!
  217. */
  218. mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  219. sr = rtt_readl(rtc, SR) & (mr >> 16);
  220. if (!sr)
  221. return IRQ_NONE;
  222. /* alarm status */
  223. if (sr & AT91_RTT_ALMS)
  224. rtc->events |= (RTC_AF | RTC_IRQF);
  225. /* timer update/increment */
  226. if (sr & AT91_RTT_RTTINC)
  227. rtc->events |= (RTC_UF | RTC_IRQF);
  228. return IRQ_HANDLED;
  229. }
  230. static void at91_rtc_flush_events(struct sam9_rtc *rtc)
  231. {
  232. if (!rtc->events)
  233. return;
  234. rtc_update_irq(rtc->rtcdev, 1, rtc->events);
  235. rtc->events = 0;
  236. pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
  237. rtc->events >> 8, rtc->events & 0x000000FF);
  238. }
  239. /*
  240. * IRQ handler for the RTC
  241. */
  242. static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
  243. {
  244. struct sam9_rtc *rtc = _rtc;
  245. int ret;
  246. spin_lock(&rtc->lock);
  247. ret = at91_rtc_cache_events(rtc);
  248. /* We're called in suspended state */
  249. if (rtc->suspended) {
  250. /* Mask irqs coming from this peripheral */
  251. rtt_writel(rtc, MR,
  252. rtt_readl(rtc, MR) &
  253. ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  254. /* Trigger a system wakeup */
  255. pm_system_wakeup();
  256. } else {
  257. at91_rtc_flush_events(rtc);
  258. }
  259. spin_unlock(&rtc->lock);
  260. return ret;
  261. }
  262. static const struct rtc_class_ops at91_rtc_ops = {
  263. .read_time = at91_rtc_readtime,
  264. .set_time = at91_rtc_settime,
  265. .read_alarm = at91_rtc_readalarm,
  266. .set_alarm = at91_rtc_setalarm,
  267. .proc = at91_rtc_proc,
  268. .alarm_irq_enable = at91_rtc_alarm_irq_enable,
  269. };
  270. /*
  271. * Initialize and install RTC driver
  272. */
  273. static int at91_rtc_probe(struct platform_device *pdev)
  274. {
  275. struct sam9_rtc *rtc;
  276. int ret, irq;
  277. u32 mr;
  278. unsigned int sclk_rate;
  279. struct of_phandle_args args;
  280. irq = platform_get_irq(pdev, 0);
  281. if (irq < 0)
  282. return irq;
  283. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  284. if (!rtc)
  285. return -ENOMEM;
  286. spin_lock_init(&rtc->lock);
  287. rtc->irq = irq;
  288. /* platform setup code should have handled this; sigh */
  289. if (!device_can_wakeup(&pdev->dev))
  290. device_init_wakeup(&pdev->dev, 1);
  291. platform_set_drvdata(pdev, rtc);
  292. rtc->rtt = devm_platform_ioremap_resource(pdev, 0);
  293. if (IS_ERR(rtc->rtt))
  294. return PTR_ERR(rtc->rtt);
  295. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  296. "atmel,rtt-rtc-time-reg", 1, 0,
  297. &args);
  298. if (ret)
  299. return ret;
  300. rtc->gpbr = syscon_node_to_regmap(args.np);
  301. rtc->gpbr_offset = args.args[0];
  302. if (IS_ERR(rtc->gpbr)) {
  303. dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
  304. return -ENOMEM;
  305. }
  306. rtc->sclk = devm_clk_get(&pdev->dev, NULL);
  307. if (IS_ERR(rtc->sclk))
  308. return PTR_ERR(rtc->sclk);
  309. ret = clk_prepare_enable(rtc->sclk);
  310. if (ret) {
  311. dev_err(&pdev->dev, "Could not enable slow clock\n");
  312. return ret;
  313. }
  314. sclk_rate = clk_get_rate(rtc->sclk);
  315. if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
  316. dev_err(&pdev->dev, "Invalid slow clock rate\n");
  317. ret = -EINVAL;
  318. goto err_clk;
  319. }
  320. mr = rtt_readl(rtc, MR);
  321. /* unless RTT is counting at 1 Hz, re-initialize it */
  322. if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
  323. mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
  324. gpbr_writel(rtc, 0);
  325. }
  326. /* disable all interrupts (same as on shutdown path) */
  327. mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  328. rtt_writel(rtc, MR, mr);
  329. rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
  330. if (IS_ERR(rtc->rtcdev)) {
  331. ret = PTR_ERR(rtc->rtcdev);
  332. goto err_clk;
  333. }
  334. rtc->rtcdev->ops = &at91_rtc_ops;
  335. rtc->rtcdev->range_max = U32_MAX;
  336. /* register irq handler after we know what name we'll use */
  337. ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
  338. IRQF_SHARED | IRQF_COND_SUSPEND,
  339. dev_name(&rtc->rtcdev->dev), rtc);
  340. if (ret) {
  341. dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
  342. goto err_clk;
  343. }
  344. /* NOTE: sam9260 rev A silicon has a ROM bug which resets the
  345. * RTT on at least some reboots. If you have that chip, you must
  346. * initialize the time from some external source like a GPS, wall
  347. * clock, discrete RTC, etc
  348. */
  349. if (gpbr_readl(rtc) == 0)
  350. dev_warn(&pdev->dev, "%s: SET TIME!\n",
  351. dev_name(&rtc->rtcdev->dev));
  352. return rtc_register_device(rtc->rtcdev);
  353. err_clk:
  354. clk_disable_unprepare(rtc->sclk);
  355. return ret;
  356. }
  357. /*
  358. * Disable and remove the RTC driver
  359. */
  360. static int at91_rtc_remove(struct platform_device *pdev)
  361. {
  362. struct sam9_rtc *rtc = platform_get_drvdata(pdev);
  363. u32 mr = rtt_readl(rtc, MR);
  364. /* disable all interrupts */
  365. rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  366. clk_disable_unprepare(rtc->sclk);
  367. return 0;
  368. }
  369. static void at91_rtc_shutdown(struct platform_device *pdev)
  370. {
  371. struct sam9_rtc *rtc = platform_get_drvdata(pdev);
  372. u32 mr = rtt_readl(rtc, MR);
  373. rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  374. rtt_writel(rtc, MR, mr & ~rtc->imr);
  375. }
  376. #ifdef CONFIG_PM_SLEEP
  377. /* AT91SAM9 RTC Power management control */
  378. static int at91_rtc_suspend(struct device *dev)
  379. {
  380. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  381. u32 mr = rtt_readl(rtc, MR);
  382. /*
  383. * This IRQ is shared with DBGU and other hardware which isn't
  384. * necessarily a wakeup event source.
  385. */
  386. rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  387. if (rtc->imr) {
  388. if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
  389. unsigned long flags;
  390. enable_irq_wake(rtc->irq);
  391. spin_lock_irqsave(&rtc->lock, flags);
  392. rtc->suspended = true;
  393. spin_unlock_irqrestore(&rtc->lock, flags);
  394. /* don't let RTTINC cause wakeups */
  395. if (mr & AT91_RTT_RTTINCIEN)
  396. rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
  397. } else {
  398. rtt_writel(rtc, MR, mr & ~rtc->imr);
  399. }
  400. }
  401. return 0;
  402. }
  403. static int at91_rtc_resume(struct device *dev)
  404. {
  405. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  406. u32 mr;
  407. if (rtc->imr) {
  408. unsigned long flags;
  409. if (device_may_wakeup(dev))
  410. disable_irq_wake(rtc->irq);
  411. mr = rtt_readl(rtc, MR);
  412. rtt_writel(rtc, MR, mr | rtc->imr);
  413. spin_lock_irqsave(&rtc->lock, flags);
  414. rtc->suspended = false;
  415. at91_rtc_cache_events(rtc);
  416. at91_rtc_flush_events(rtc);
  417. spin_unlock_irqrestore(&rtc->lock, flags);
  418. }
  419. return 0;
  420. }
  421. #endif
  422. static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
  423. static const struct of_device_id at91_rtc_dt_ids[] = {
  424. { .compatible = "atmel,at91sam9260-rtt" },
  425. { /* sentinel */ }
  426. };
  427. MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
  428. static struct platform_driver at91_rtc_driver = {
  429. .probe = at91_rtc_probe,
  430. .remove = at91_rtc_remove,
  431. .shutdown = at91_rtc_shutdown,
  432. .driver = {
  433. .name = "rtc-at91sam9",
  434. .pm = &at91_rtc_pm_ops,
  435. .of_match_table = of_match_ptr(at91_rtc_dt_ids),
  436. },
  437. };
  438. module_platform_driver(at91_rtc_driver);
  439. MODULE_AUTHOR("Michel Benoit");
  440. MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
  441. MODULE_LICENSE("GPL");