rtc-at91rm9200.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Real Time Clock interface for Linux on Atmel AT91RM9200
  4. *
  5. * Copyright (C) 2002 Rick Bronson
  6. *
  7. * Converted to RTC class model by Andrew Victor
  8. *
  9. * Ported to Linux 2.6 by Steven Scholz
  10. * Based on s3c2410-rtc.c Simtec Electronics
  11. *
  12. * Based on sa1100-rtc.c by Nils Faerber
  13. * Based on rtc.c by Paul Gortmaker
  14. */
  15. #include <linux/bcd.h>
  16. #include <linux/bitfield.h>
  17. #include <linux/clk.h>
  18. #include <linux/completion.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioctl.h>
  21. #include <linux/io.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/of_device.h>
  25. #include <linux/of.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/rtc.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/suspend.h>
  30. #include <linux/time.h>
  31. #include <linux/uaccess.h>
  32. #define AT91_RTC_CR 0x00 /* Control Register */
  33. #define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */
  34. #define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */
  35. #define AT91_RTC_MR 0x04 /* Mode Register */
  36. #define AT91_RTC_TIMR 0x08 /* Time Register */
  37. #define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */
  38. #define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */
  39. #define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */
  40. #define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */
  41. #define AT91_RTC_CALR 0x0c /* Calendar Register */
  42. #define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */
  43. #define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */
  44. #define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */
  45. #define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */
  46. #define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */
  47. #define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
  48. #define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */
  49. #define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */
  50. #define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */
  51. #define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
  52. #define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */
  53. #define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */
  54. #define AT91_RTC_SR 0x18 /* Status Register */
  55. #define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */
  56. #define AT91_RTC_ALARM BIT(1) /* Alarm Flag */
  57. #define AT91_RTC_SECEV BIT(2) /* Second Event */
  58. #define AT91_RTC_TIMEV BIT(3) /* Time Event */
  59. #define AT91_RTC_CALEV BIT(4) /* Calendar Event */
  60. #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
  61. #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
  62. #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
  63. #define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
  64. #define AT91_RTC_VER 0x2c /* Valid Entry Register */
  65. #define AT91_RTC_NVTIM BIT(0) /* Non valid Time */
  66. #define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */
  67. #define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */
  68. #define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */
  69. #define at91_rtc_read(field) \
  70. readl_relaxed(at91_rtc_regs + field)
  71. #define at91_rtc_write(field, val) \
  72. writel_relaxed((val), at91_rtc_regs + field)
  73. struct at91_rtc_config {
  74. bool use_shadow_imr;
  75. };
  76. static const struct at91_rtc_config *at91_rtc_config;
  77. static DECLARE_COMPLETION(at91_rtc_updated);
  78. static DECLARE_COMPLETION(at91_rtc_upd_rdy);
  79. static void __iomem *at91_rtc_regs;
  80. static int irq;
  81. static DEFINE_SPINLOCK(at91_rtc_lock);
  82. static u32 at91_rtc_shadow_imr;
  83. static bool suspended;
  84. static DEFINE_SPINLOCK(suspended_lock);
  85. static unsigned long cached_events;
  86. static u32 at91_rtc_imr;
  87. static struct clk *sclk;
  88. static void at91_rtc_write_ier(u32 mask)
  89. {
  90. unsigned long flags;
  91. spin_lock_irqsave(&at91_rtc_lock, flags);
  92. at91_rtc_shadow_imr |= mask;
  93. at91_rtc_write(AT91_RTC_IER, mask);
  94. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  95. }
  96. static void at91_rtc_write_idr(u32 mask)
  97. {
  98. unsigned long flags;
  99. spin_lock_irqsave(&at91_rtc_lock, flags);
  100. at91_rtc_write(AT91_RTC_IDR, mask);
  101. /*
  102. * Register read back (of any RTC-register) needed to make sure
  103. * IDR-register write has reached the peripheral before updating
  104. * shadow mask.
  105. *
  106. * Note that there is still a possibility that the mask is updated
  107. * before interrupts have actually been disabled in hardware. The only
  108. * way to be certain would be to poll the IMR-register, which is is
  109. * the very register we are trying to emulate. The register read back
  110. * is a reasonable heuristic.
  111. */
  112. at91_rtc_read(AT91_RTC_SR);
  113. at91_rtc_shadow_imr &= ~mask;
  114. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  115. }
  116. static u32 at91_rtc_read_imr(void)
  117. {
  118. unsigned long flags;
  119. u32 mask;
  120. if (at91_rtc_config->use_shadow_imr) {
  121. spin_lock_irqsave(&at91_rtc_lock, flags);
  122. mask = at91_rtc_shadow_imr;
  123. spin_unlock_irqrestore(&at91_rtc_lock, flags);
  124. } else {
  125. mask = at91_rtc_read(AT91_RTC_IMR);
  126. }
  127. return mask;
  128. }
  129. /*
  130. * Decode time/date into rtc_time structure
  131. */
  132. static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
  133. struct rtc_time *tm)
  134. {
  135. unsigned int time, date;
  136. /* must read twice in case it changes */
  137. do {
  138. time = at91_rtc_read(timereg);
  139. date = at91_rtc_read(calreg);
  140. } while ((time != at91_rtc_read(timereg)) ||
  141. (date != at91_rtc_read(calreg)));
  142. tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
  143. tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
  144. tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
  145. /*
  146. * The Calendar Alarm register does not have a field for
  147. * the year - so these will return an invalid value.
  148. */
  149. tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */
  150. tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
  151. tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */
  152. tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
  153. tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
  154. }
  155. /*
  156. * Read current time and date in RTC
  157. */
  158. static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
  159. {
  160. at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
  161. tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
  162. tm->tm_year = tm->tm_year - 1900;
  163. dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
  164. return 0;
  165. }
  166. /*
  167. * Set current time and date in RTC
  168. */
  169. static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
  170. {
  171. unsigned long cr;
  172. dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
  173. wait_for_completion(&at91_rtc_upd_rdy);
  174. /* Stop Time/Calendar from counting */
  175. cr = at91_rtc_read(AT91_RTC_CR);
  176. at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
  177. at91_rtc_write_ier(AT91_RTC_ACKUPD);
  178. wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
  179. at91_rtc_write_idr(AT91_RTC_ACKUPD);
  180. at91_rtc_write(AT91_RTC_TIMR,
  181. FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
  182. | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
  183. | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
  184. at91_rtc_write(AT91_RTC_CALR,
  185. FIELD_PREP(AT91_RTC_CENT,
  186. bin2bcd((tm->tm_year + 1900) / 100))
  187. | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
  188. | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
  189. | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
  190. | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
  191. /* Restart Time/Calendar */
  192. cr = at91_rtc_read(AT91_RTC_CR);
  193. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
  194. at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
  195. at91_rtc_write_ier(AT91_RTC_SECEV);
  196. return 0;
  197. }
  198. /*
  199. * Read alarm time and date in RTC
  200. */
  201. static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
  202. {
  203. struct rtc_time *tm = &alrm->time;
  204. at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
  205. tm->tm_year = -1;
  206. alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
  207. ? 1 : 0;
  208. dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
  209. alrm->enabled ? "en" : "dis");
  210. return 0;
  211. }
  212. /*
  213. * Set alarm time and date in RTC
  214. */
  215. static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  216. {
  217. struct rtc_time tm = alrm->time;
  218. at91_rtc_write_idr(AT91_RTC_ALARM);
  219. at91_rtc_write(AT91_RTC_TIMALR,
  220. FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
  221. | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
  222. | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
  223. | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
  224. at91_rtc_write(AT91_RTC_CALALR,
  225. FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
  226. | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
  227. | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
  228. if (alrm->enabled) {
  229. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  230. at91_rtc_write_ier(AT91_RTC_ALARM);
  231. }
  232. dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
  233. return 0;
  234. }
  235. static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  236. {
  237. dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
  238. if (enabled) {
  239. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  240. at91_rtc_write_ier(AT91_RTC_ALARM);
  241. } else
  242. at91_rtc_write_idr(AT91_RTC_ALARM);
  243. return 0;
  244. }
  245. /*
  246. * IRQ handler for the RTC
  247. */
  248. static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
  249. {
  250. struct platform_device *pdev = dev_id;
  251. struct rtc_device *rtc = platform_get_drvdata(pdev);
  252. unsigned int rtsr;
  253. unsigned long events = 0;
  254. int ret = IRQ_NONE;
  255. spin_lock(&suspended_lock);
  256. rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
  257. if (rtsr) { /* this interrupt is shared! Is it ours? */
  258. if (rtsr & AT91_RTC_ALARM)
  259. events |= (RTC_AF | RTC_IRQF);
  260. if (rtsr & AT91_RTC_SECEV) {
  261. complete(&at91_rtc_upd_rdy);
  262. at91_rtc_write_idr(AT91_RTC_SECEV);
  263. }
  264. if (rtsr & AT91_RTC_ACKUPD)
  265. complete(&at91_rtc_updated);
  266. at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
  267. if (!suspended) {
  268. rtc_update_irq(rtc, 1, events);
  269. dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
  270. __func__, events >> 8, events & 0x000000FF);
  271. } else {
  272. cached_events |= events;
  273. at91_rtc_write_idr(at91_rtc_imr);
  274. pm_system_wakeup();
  275. }
  276. ret = IRQ_HANDLED;
  277. }
  278. spin_unlock(&suspended_lock);
  279. return ret;
  280. }
  281. static const struct at91_rtc_config at91rm9200_config = {
  282. };
  283. static const struct at91_rtc_config at91sam9x5_config = {
  284. .use_shadow_imr = true,
  285. };
  286. static const struct of_device_id at91_rtc_dt_ids[] = {
  287. {
  288. .compatible = "atmel,at91rm9200-rtc",
  289. .data = &at91rm9200_config,
  290. }, {
  291. .compatible = "atmel,at91sam9x5-rtc",
  292. .data = &at91sam9x5_config,
  293. }, {
  294. .compatible = "atmel,sama5d4-rtc",
  295. .data = &at91rm9200_config,
  296. }, {
  297. .compatible = "atmel,sama5d2-rtc",
  298. .data = &at91rm9200_config,
  299. }, {
  300. /* sentinel */
  301. }
  302. };
  303. MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
  304. static const struct rtc_class_ops at91_rtc_ops = {
  305. .read_time = at91_rtc_readtime,
  306. .set_time = at91_rtc_settime,
  307. .read_alarm = at91_rtc_readalarm,
  308. .set_alarm = at91_rtc_setalarm,
  309. .alarm_irq_enable = at91_rtc_alarm_irq_enable,
  310. };
  311. /*
  312. * Initialize and install RTC driver
  313. */
  314. static int __init at91_rtc_probe(struct platform_device *pdev)
  315. {
  316. struct rtc_device *rtc;
  317. struct resource *regs;
  318. int ret = 0;
  319. at91_rtc_config = of_device_get_match_data(&pdev->dev);
  320. if (!at91_rtc_config)
  321. return -ENODEV;
  322. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  323. if (!regs) {
  324. dev_err(&pdev->dev, "no mmio resource defined\n");
  325. return -ENXIO;
  326. }
  327. irq = platform_get_irq(pdev, 0);
  328. if (irq < 0)
  329. return -ENXIO;
  330. at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
  331. resource_size(regs));
  332. if (!at91_rtc_regs) {
  333. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  334. return -ENOMEM;
  335. }
  336. rtc = devm_rtc_allocate_device(&pdev->dev);
  337. if (IS_ERR(rtc))
  338. return PTR_ERR(rtc);
  339. platform_set_drvdata(pdev, rtc);
  340. sclk = devm_clk_get(&pdev->dev, NULL);
  341. if (IS_ERR(sclk))
  342. return PTR_ERR(sclk);
  343. ret = clk_prepare_enable(sclk);
  344. if (ret) {
  345. dev_err(&pdev->dev, "Could not enable slow clock\n");
  346. return ret;
  347. }
  348. at91_rtc_write(AT91_RTC_CR, 0);
  349. at91_rtc_write(AT91_RTC_MR, 0); /* 24 hour mode */
  350. /* Disable all interrupts */
  351. at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  352. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  353. AT91_RTC_CALEV);
  354. ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
  355. IRQF_SHARED | IRQF_COND_SUSPEND,
  356. "at91_rtc", pdev);
  357. if (ret) {
  358. dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
  359. goto err_clk;
  360. }
  361. /* cpu init code should really have flagged this device as
  362. * being wake-capable; if it didn't, do that here.
  363. */
  364. if (!device_can_wakeup(&pdev->dev))
  365. device_init_wakeup(&pdev->dev, 1);
  366. rtc->ops = &at91_rtc_ops;
  367. rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
  368. rtc->range_max = RTC_TIMESTAMP_END_2099;
  369. ret = rtc_register_device(rtc);
  370. if (ret)
  371. goto err_clk;
  372. /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
  373. * completion.
  374. */
  375. at91_rtc_write_ier(AT91_RTC_SECEV);
  376. dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
  377. return 0;
  378. err_clk:
  379. clk_disable_unprepare(sclk);
  380. return ret;
  381. }
  382. /*
  383. * Disable and remove the RTC driver
  384. */
  385. static int __exit at91_rtc_remove(struct platform_device *pdev)
  386. {
  387. /* Disable all interrupts */
  388. at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  389. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  390. AT91_RTC_CALEV);
  391. clk_disable_unprepare(sclk);
  392. return 0;
  393. }
  394. static void at91_rtc_shutdown(struct platform_device *pdev)
  395. {
  396. /* Disable all interrupts */
  397. at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
  398. AT91_RTC_SECEV | AT91_RTC_TIMEV |
  399. AT91_RTC_CALEV);
  400. }
  401. #ifdef CONFIG_PM_SLEEP
  402. /* AT91RM9200 RTC Power management control */
  403. static int at91_rtc_suspend(struct device *dev)
  404. {
  405. /* this IRQ is shared with DBGU and other hardware which isn't
  406. * necessarily doing PM like we are...
  407. */
  408. at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
  409. at91_rtc_imr = at91_rtc_read_imr()
  410. & (AT91_RTC_ALARM|AT91_RTC_SECEV);
  411. if (at91_rtc_imr) {
  412. if (device_may_wakeup(dev)) {
  413. unsigned long flags;
  414. enable_irq_wake(irq);
  415. spin_lock_irqsave(&suspended_lock, flags);
  416. suspended = true;
  417. spin_unlock_irqrestore(&suspended_lock, flags);
  418. } else {
  419. at91_rtc_write_idr(at91_rtc_imr);
  420. }
  421. }
  422. return 0;
  423. }
  424. static int at91_rtc_resume(struct device *dev)
  425. {
  426. struct rtc_device *rtc = dev_get_drvdata(dev);
  427. if (at91_rtc_imr) {
  428. if (device_may_wakeup(dev)) {
  429. unsigned long flags;
  430. spin_lock_irqsave(&suspended_lock, flags);
  431. if (cached_events) {
  432. rtc_update_irq(rtc, 1, cached_events);
  433. cached_events = 0;
  434. }
  435. suspended = false;
  436. spin_unlock_irqrestore(&suspended_lock, flags);
  437. disable_irq_wake(irq);
  438. }
  439. at91_rtc_write_ier(at91_rtc_imr);
  440. }
  441. return 0;
  442. }
  443. #endif
  444. static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
  445. static struct platform_driver at91_rtc_driver = {
  446. .remove = __exit_p(at91_rtc_remove),
  447. .shutdown = at91_rtc_shutdown,
  448. .driver = {
  449. .name = "at91_rtc",
  450. .pm = &at91_rtc_pm_ops,
  451. .of_match_table = of_match_ptr(at91_rtc_dt_ids),
  452. },
  453. };
  454. module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
  455. MODULE_AUTHOR("Rick Bronson");
  456. MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
  457. MODULE_LICENSE("GPL");
  458. MODULE_ALIAS("platform:at91_rtc");