rtc-armada38x.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * RTC driver for the Armada 38x Marvell SoCs
  4. *
  5. * Copyright (C) 2015 Marvell
  6. *
  7. * Gregory Clement <gregory.clement@free-electrons.com>
  8. */
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/rtc.h>
  16. #define RTC_STATUS 0x0
  17. #define RTC_STATUS_ALARM1 BIT(0)
  18. #define RTC_STATUS_ALARM2 BIT(1)
  19. #define RTC_IRQ1_CONF 0x4
  20. #define RTC_IRQ2_CONF 0x8
  21. #define RTC_IRQ_AL_EN BIT(0)
  22. #define RTC_IRQ_FREQ_EN BIT(1)
  23. #define RTC_IRQ_FREQ_1HZ BIT(2)
  24. #define RTC_CCR 0x18
  25. #define RTC_CCR_MODE BIT(15)
  26. #define RTC_CONF_TEST 0x1C
  27. #define RTC_NOMINAL_TIMING BIT(13)
  28. #define RTC_TIME 0xC
  29. #define RTC_ALARM1 0x10
  30. #define RTC_ALARM2 0x14
  31. /* Armada38x SoC registers */
  32. #define RTC_38X_BRIDGE_TIMING_CTL 0x0
  33. #define RTC_38X_PERIOD_OFFS 0
  34. #define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
  35. #define RTC_38X_READ_DELAY_OFFS 26
  36. #define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
  37. /* Armada 7K/8K registers */
  38. #define RTC_8K_BRIDGE_TIMING_CTL0 0x0
  39. #define RTC_8K_WRCLK_PERIOD_OFFS 0
  40. #define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
  41. #define RTC_8K_WRCLK_SETUP_OFFS 16
  42. #define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
  43. #define RTC_8K_BRIDGE_TIMING_CTL1 0x4
  44. #define RTC_8K_READ_DELAY_OFFS 0
  45. #define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
  46. #define RTC_8K_ISR 0x10
  47. #define RTC_8K_IMR 0x14
  48. #define RTC_8K_ALARM2 BIT(0)
  49. #define SOC_RTC_INTERRUPT 0x8
  50. #define SOC_RTC_ALARM1 BIT(0)
  51. #define SOC_RTC_ALARM2 BIT(1)
  52. #define SOC_RTC_ALARM1_MASK BIT(2)
  53. #define SOC_RTC_ALARM2_MASK BIT(3)
  54. #define SAMPLE_NR 100
  55. struct value_to_freq {
  56. u32 value;
  57. u8 freq;
  58. };
  59. struct armada38x_rtc {
  60. struct rtc_device *rtc_dev;
  61. void __iomem *regs;
  62. void __iomem *regs_soc;
  63. spinlock_t lock;
  64. int irq;
  65. bool initialized;
  66. struct value_to_freq *val_to_freq;
  67. const struct armada38x_rtc_data *data;
  68. };
  69. #define ALARM1 0
  70. #define ALARM2 1
  71. #define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
  72. struct armada38x_rtc_data {
  73. /* Initialize the RTC-MBUS bridge timing */
  74. void (*update_mbus_timing)(struct armada38x_rtc *rtc);
  75. u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
  76. void (*clear_isr)(struct armada38x_rtc *rtc);
  77. void (*unmask_interrupt)(struct armada38x_rtc *rtc);
  78. u32 alarm;
  79. };
  80. /*
  81. * According to the datasheet, the OS should wait 5us after every
  82. * register write to the RTC hard macro so that the required update
  83. * can occur without holding off the system bus
  84. * According to errata RES-3124064, Write to any RTC register
  85. * may fail. As a workaround, before writing to RTC
  86. * register, issue a dummy write of 0x0 twice to RTC Status
  87. * register.
  88. */
  89. static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
  90. {
  91. writel(0, rtc->regs + RTC_STATUS);
  92. writel(0, rtc->regs + RTC_STATUS);
  93. writel(val, rtc->regs + offset);
  94. udelay(5);
  95. }
  96. /* Update RTC-MBUS bridge timing parameters */
  97. static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
  98. {
  99. u32 reg;
  100. reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
  101. reg &= ~RTC_38X_PERIOD_MASK;
  102. reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
  103. reg &= ~RTC_38X_READ_DELAY_MASK;
  104. reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
  105. writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
  106. }
  107. static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
  108. {
  109. u32 reg;
  110. reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
  111. reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
  112. reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
  113. reg &= ~RTC_8K_WRCLK_SETUP_MASK;
  114. reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
  115. writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
  116. reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
  117. reg &= ~RTC_8K_READ_DELAY_MASK;
  118. reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
  119. writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
  120. }
  121. static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
  122. {
  123. return readl(rtc->regs + rtc_reg);
  124. }
  125. static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
  126. {
  127. int i, index_max = 0, max = 0;
  128. for (i = 0; i < SAMPLE_NR; i++) {
  129. rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
  130. rtc->val_to_freq[i].freq = 0;
  131. }
  132. for (i = 0; i < SAMPLE_NR; i++) {
  133. int j = 0;
  134. u32 value = rtc->val_to_freq[i].value;
  135. while (rtc->val_to_freq[j].freq) {
  136. if (rtc->val_to_freq[j].value == value) {
  137. rtc->val_to_freq[j].freq++;
  138. break;
  139. }
  140. j++;
  141. }
  142. if (!rtc->val_to_freq[j].freq) {
  143. rtc->val_to_freq[j].value = value;
  144. rtc->val_to_freq[j].freq = 1;
  145. }
  146. if (rtc->val_to_freq[j].freq > max) {
  147. index_max = j;
  148. max = rtc->val_to_freq[j].freq;
  149. }
  150. /*
  151. * If a value already has half of the sample this is the most
  152. * frequent one and we can stop the research right now
  153. */
  154. if (max > SAMPLE_NR / 2)
  155. break;
  156. }
  157. return rtc->val_to_freq[index_max].value;
  158. }
  159. static void armada38x_clear_isr(struct armada38x_rtc *rtc)
  160. {
  161. u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
  162. writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
  163. }
  164. static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
  165. {
  166. u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
  167. writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
  168. }
  169. static void armada8k_clear_isr(struct armada38x_rtc *rtc)
  170. {
  171. writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
  172. }
  173. static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
  174. {
  175. writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
  176. }
  177. static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
  178. {
  179. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  180. unsigned long time, flags;
  181. spin_lock_irqsave(&rtc->lock, flags);
  182. time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
  183. spin_unlock_irqrestore(&rtc->lock, flags);
  184. rtc_time64_to_tm(time, tm);
  185. return 0;
  186. }
  187. static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
  188. {
  189. u32 reg;
  190. reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
  191. /* If bits [7:0] are non-zero, assume RTC was uninitialized */
  192. if (reg & 0xff) {
  193. rtc_delayed_write(0, rtc, RTC_CONF_TEST);
  194. msleep(500); /* Oscillator startup time */
  195. rtc_delayed_write(0, rtc, RTC_TIME);
  196. rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
  197. RTC_STATUS);
  198. rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
  199. }
  200. rtc->initialized = true;
  201. }
  202. static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
  203. {
  204. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  205. unsigned long time, flags;
  206. time = rtc_tm_to_time64(tm);
  207. if (!rtc->initialized)
  208. armada38x_rtc_reset(rtc);
  209. spin_lock_irqsave(&rtc->lock, flags);
  210. rtc_delayed_write(time, rtc, RTC_TIME);
  211. spin_unlock_irqrestore(&rtc->lock, flags);
  212. return 0;
  213. }
  214. static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  215. {
  216. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  217. unsigned long time, flags;
  218. u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
  219. u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
  220. u32 val;
  221. spin_lock_irqsave(&rtc->lock, flags);
  222. time = rtc->data->read_rtc_reg(rtc, reg);
  223. val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
  224. spin_unlock_irqrestore(&rtc->lock, flags);
  225. alrm->enabled = val ? 1 : 0;
  226. rtc_time64_to_tm(time, &alrm->time);
  227. return 0;
  228. }
  229. static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  230. {
  231. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  232. u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
  233. u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
  234. unsigned long time, flags;
  235. time = rtc_tm_to_time64(&alrm->time);
  236. spin_lock_irqsave(&rtc->lock, flags);
  237. rtc_delayed_write(time, rtc, reg);
  238. if (alrm->enabled) {
  239. rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
  240. rtc->data->unmask_interrupt(rtc);
  241. }
  242. spin_unlock_irqrestore(&rtc->lock, flags);
  243. return 0;
  244. }
  245. static int armada38x_rtc_alarm_irq_enable(struct device *dev,
  246. unsigned int enabled)
  247. {
  248. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  249. u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
  250. unsigned long flags;
  251. spin_lock_irqsave(&rtc->lock, flags);
  252. if (enabled)
  253. rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
  254. else
  255. rtc_delayed_write(0, rtc, reg_irq);
  256. spin_unlock_irqrestore(&rtc->lock, flags);
  257. return 0;
  258. }
  259. static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
  260. {
  261. struct armada38x_rtc *rtc = data;
  262. u32 val;
  263. int event = RTC_IRQF | RTC_AF;
  264. u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
  265. dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
  266. spin_lock(&rtc->lock);
  267. rtc->data->clear_isr(rtc);
  268. val = rtc->data->read_rtc_reg(rtc, reg_irq);
  269. /* disable all the interrupts for alarm*/
  270. rtc_delayed_write(0, rtc, reg_irq);
  271. /* Ack the event */
  272. rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
  273. spin_unlock(&rtc->lock);
  274. if (val & RTC_IRQ_FREQ_EN) {
  275. if (val & RTC_IRQ_FREQ_1HZ)
  276. event |= RTC_UF;
  277. else
  278. event |= RTC_PF;
  279. }
  280. rtc_update_irq(rtc->rtc_dev, 1, event);
  281. return IRQ_HANDLED;
  282. }
  283. /*
  284. * The information given in the Armada 388 functional spec is complex.
  285. * They give two different formulas for calculating the offset value,
  286. * but when considering "Offset" as an 8-bit signed integer, they both
  287. * reduce down to (we shall rename "Offset" as "val" here):
  288. *
  289. * val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
  290. *
  291. * Converting to time, f = 1/t:
  292. * val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
  293. *
  294. * => t_measured / t_ideal = val * resolution + 1
  295. *
  296. * "offset" in the RTC interface is defined as:
  297. * t = t0 * (1 + offset * 1e-9)
  298. * where t is the desired period, t0 is the measured period with a zero
  299. * offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
  300. * offset = (t_ideal / t_measured - 1) / 1e-9
  301. *
  302. * => t_ideal / t_measured = offset * 1e-9 + 1
  303. *
  304. * so:
  305. *
  306. * offset * 1e-9 + 1 = 1 / (val * resolution + 1)
  307. *
  308. * We want "resolution" to be an integer, so resolution = R * 1e-9, giving
  309. * offset = 1e18 / (val * R + 1e9) - 1e9
  310. * val = (1e18 / (offset + 1e9) - 1e9) / R
  311. * with a common transformation:
  312. * f(x) = 1e18 / (x + 1e9) - 1e9
  313. * offset = f(val * R)
  314. * val = f(offset) / R
  315. *
  316. * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
  317. */
  318. static long armada38x_ppb_convert(long ppb)
  319. {
  320. long div = ppb + 1000000000L;
  321. return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
  322. }
  323. static int armada38x_rtc_read_offset(struct device *dev, long *offset)
  324. {
  325. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  326. unsigned long ccr, flags;
  327. long ppb_cor;
  328. spin_lock_irqsave(&rtc->lock, flags);
  329. ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
  330. spin_unlock_irqrestore(&rtc->lock, flags);
  331. ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
  332. /* ppb_cor + 1000000000L can never be zero */
  333. *offset = armada38x_ppb_convert(ppb_cor);
  334. return 0;
  335. }
  336. static int armada38x_rtc_set_offset(struct device *dev, long offset)
  337. {
  338. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  339. unsigned long ccr = 0;
  340. long ppb_cor, off;
  341. /*
  342. * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
  343. * need to clamp the input. This equates to -484270 .. 488558.
  344. * Not only is this to stop out of range "off" but also to
  345. * avoid the division by zero in armada38x_ppb_convert().
  346. */
  347. offset = clamp(offset, -484270L, 488558L);
  348. ppb_cor = armada38x_ppb_convert(offset);
  349. /*
  350. * Use low update mode where possible, which gives a better
  351. * resolution of correction.
  352. */
  353. off = DIV_ROUND_CLOSEST(ppb_cor, 954);
  354. if (off > 127 || off < -128) {
  355. ccr = RTC_CCR_MODE;
  356. off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
  357. }
  358. /*
  359. * Armada 388 requires a bit pattern in bits 14..8 depending on
  360. * the sign bit: { 0, ~S, S, S, S, S, S }
  361. */
  362. ccr |= (off & 0x3fff) ^ 0x2000;
  363. rtc_delayed_write(ccr, rtc, RTC_CCR);
  364. return 0;
  365. }
  366. static const struct rtc_class_ops armada38x_rtc_ops = {
  367. .read_time = armada38x_rtc_read_time,
  368. .set_time = armada38x_rtc_set_time,
  369. .read_alarm = armada38x_rtc_read_alarm,
  370. .set_alarm = armada38x_rtc_set_alarm,
  371. .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
  372. .read_offset = armada38x_rtc_read_offset,
  373. .set_offset = armada38x_rtc_set_offset,
  374. };
  375. static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
  376. .read_time = armada38x_rtc_read_time,
  377. .set_time = armada38x_rtc_set_time,
  378. .read_alarm = armada38x_rtc_read_alarm,
  379. .read_offset = armada38x_rtc_read_offset,
  380. .set_offset = armada38x_rtc_set_offset,
  381. };
  382. static const struct armada38x_rtc_data armada38x_data = {
  383. .update_mbus_timing = rtc_update_38x_mbus_timing_params,
  384. .read_rtc_reg = read_rtc_register_38x_wa,
  385. .clear_isr = armada38x_clear_isr,
  386. .unmask_interrupt = armada38x_unmask_interrupt,
  387. .alarm = ALARM1,
  388. };
  389. static const struct armada38x_rtc_data armada8k_data = {
  390. .update_mbus_timing = rtc_update_8k_mbus_timing_params,
  391. .read_rtc_reg = read_rtc_register,
  392. .clear_isr = armada8k_clear_isr,
  393. .unmask_interrupt = armada8k_unmask_interrupt,
  394. .alarm = ALARM2,
  395. };
  396. #ifdef CONFIG_OF
  397. static const struct of_device_id armada38x_rtc_of_match_table[] = {
  398. {
  399. .compatible = "marvell,armada-380-rtc",
  400. .data = &armada38x_data,
  401. },
  402. {
  403. .compatible = "marvell,armada-8k-rtc",
  404. .data = &armada8k_data,
  405. },
  406. {}
  407. };
  408. MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
  409. #endif
  410. static __init int armada38x_rtc_probe(struct platform_device *pdev)
  411. {
  412. struct resource *res;
  413. struct armada38x_rtc *rtc;
  414. rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
  415. GFP_KERNEL);
  416. if (!rtc)
  417. return -ENOMEM;
  418. rtc->data = of_device_get_match_data(&pdev->dev);
  419. rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
  420. sizeof(struct value_to_freq), GFP_KERNEL);
  421. if (!rtc->val_to_freq)
  422. return -ENOMEM;
  423. spin_lock_init(&rtc->lock);
  424. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
  425. rtc->regs = devm_ioremap_resource(&pdev->dev, res);
  426. if (IS_ERR(rtc->regs))
  427. return PTR_ERR(rtc->regs);
  428. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
  429. rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
  430. if (IS_ERR(rtc->regs_soc))
  431. return PTR_ERR(rtc->regs_soc);
  432. rtc->irq = platform_get_irq(pdev, 0);
  433. if (rtc->irq < 0)
  434. return rtc->irq;
  435. rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
  436. if (IS_ERR(rtc->rtc_dev))
  437. return PTR_ERR(rtc->rtc_dev);
  438. if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
  439. 0, pdev->name, rtc) < 0) {
  440. dev_warn(&pdev->dev, "Interrupt not available.\n");
  441. rtc->irq = -1;
  442. }
  443. platform_set_drvdata(pdev, rtc);
  444. if (rtc->irq != -1) {
  445. device_init_wakeup(&pdev->dev, 1);
  446. rtc->rtc_dev->ops = &armada38x_rtc_ops;
  447. } else {
  448. /*
  449. * If there is no interrupt available then we can't
  450. * use the alarm
  451. */
  452. rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq;
  453. }
  454. /* Update RTC-MBUS bridge timing parameters */
  455. rtc->data->update_mbus_timing(rtc);
  456. rtc->rtc_dev->range_max = U32_MAX;
  457. return rtc_register_device(rtc->rtc_dev);
  458. }
  459. #ifdef CONFIG_PM_SLEEP
  460. static int armada38x_rtc_suspend(struct device *dev)
  461. {
  462. if (device_may_wakeup(dev)) {
  463. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  464. return enable_irq_wake(rtc->irq);
  465. }
  466. return 0;
  467. }
  468. static int armada38x_rtc_resume(struct device *dev)
  469. {
  470. if (device_may_wakeup(dev)) {
  471. struct armada38x_rtc *rtc = dev_get_drvdata(dev);
  472. /* Update RTC-MBUS bridge timing parameters */
  473. rtc->data->update_mbus_timing(rtc);
  474. return disable_irq_wake(rtc->irq);
  475. }
  476. return 0;
  477. }
  478. #endif
  479. static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
  480. armada38x_rtc_suspend, armada38x_rtc_resume);
  481. static struct platform_driver armada38x_rtc_driver = {
  482. .driver = {
  483. .name = "armada38x-rtc",
  484. .pm = &armada38x_rtc_pm_ops,
  485. .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
  486. },
  487. };
  488. module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
  489. MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
  490. MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
  491. MODULE_LICENSE("GPL");