rtc-ac100.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * RTC Driver for X-Powers AC100
  4. *
  5. * Copyright (c) 2016 Chen-Yu Tsai
  6. *
  7. * Chen-Yu Tsai <wens@csie.org>
  8. */
  9. #include <linux/bcd.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/device.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mfd/ac100.h>
  15. #include <linux/module.h>
  16. #include <linux/mutex.h>
  17. #include <linux/of.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/rtc.h>
  21. #include <linux/types.h>
  22. /* Control register */
  23. #define AC100_RTC_CTRL_24HOUR BIT(0)
  24. /* Clock output register bits */
  25. #define AC100_CLKOUT_PRE_DIV_SHIFT 5
  26. #define AC100_CLKOUT_PRE_DIV_WIDTH 3
  27. #define AC100_CLKOUT_MUX_SHIFT 4
  28. #define AC100_CLKOUT_MUX_WIDTH 1
  29. #define AC100_CLKOUT_DIV_SHIFT 1
  30. #define AC100_CLKOUT_DIV_WIDTH 3
  31. #define AC100_CLKOUT_EN BIT(0)
  32. /* RTC */
  33. #define AC100_RTC_SEC_MASK GENMASK(6, 0)
  34. #define AC100_RTC_MIN_MASK GENMASK(6, 0)
  35. #define AC100_RTC_HOU_MASK GENMASK(5, 0)
  36. #define AC100_RTC_WEE_MASK GENMASK(2, 0)
  37. #define AC100_RTC_DAY_MASK GENMASK(5, 0)
  38. #define AC100_RTC_MON_MASK GENMASK(4, 0)
  39. #define AC100_RTC_YEA_MASK GENMASK(7, 0)
  40. #define AC100_RTC_YEA_LEAP BIT(15)
  41. #define AC100_RTC_UPD_TRIGGER BIT(15)
  42. /* Alarm (wall clock) */
  43. #define AC100_ALM_INT_ENABLE BIT(0)
  44. #define AC100_ALM_SEC_MASK GENMASK(6, 0)
  45. #define AC100_ALM_MIN_MASK GENMASK(6, 0)
  46. #define AC100_ALM_HOU_MASK GENMASK(5, 0)
  47. #define AC100_ALM_WEE_MASK GENMASK(2, 0)
  48. #define AC100_ALM_DAY_MASK GENMASK(5, 0)
  49. #define AC100_ALM_MON_MASK GENMASK(4, 0)
  50. #define AC100_ALM_YEA_MASK GENMASK(7, 0)
  51. #define AC100_ALM_ENABLE_FLAG BIT(15)
  52. #define AC100_ALM_UPD_TRIGGER BIT(15)
  53. /*
  54. * The year parameter passed to the driver is usually an offset relative to
  55. * the year 1900. This macro is used to convert this offset to another one
  56. * relative to the minimum year allowed by the hardware.
  57. *
  58. * The year range is 1970 - 2069. This range is selected to match Allwinner's
  59. * driver.
  60. */
  61. #define AC100_YEAR_MIN 1970
  62. #define AC100_YEAR_MAX 2069
  63. #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
  64. struct ac100_clkout {
  65. struct clk_hw hw;
  66. struct regmap *regmap;
  67. u8 offset;
  68. };
  69. #define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
  70. #define AC100_RTC_32K_NAME "ac100-rtc-32k"
  71. #define AC100_RTC_32K_RATE 32768
  72. #define AC100_CLKOUT_NUM 3
  73. static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
  74. "ac100-cko1-rtc",
  75. "ac100-cko2-rtc",
  76. "ac100-cko3-rtc",
  77. };
  78. struct ac100_rtc_dev {
  79. struct rtc_device *rtc;
  80. struct device *dev;
  81. struct regmap *regmap;
  82. int irq;
  83. unsigned long alarm;
  84. struct clk_hw *rtc_32k_clk;
  85. struct ac100_clkout clks[AC100_CLKOUT_NUM];
  86. struct clk_hw_onecell_data *clk_data;
  87. };
  88. /**
  89. * Clock controls for 3 clock output pins
  90. */
  91. static const struct clk_div_table ac100_clkout_prediv[] = {
  92. { .val = 0, .div = 1 },
  93. { .val = 1, .div = 2 },
  94. { .val = 2, .div = 4 },
  95. { .val = 3, .div = 8 },
  96. { .val = 4, .div = 16 },
  97. { .val = 5, .div = 32 },
  98. { .val = 6, .div = 64 },
  99. { .val = 7, .div = 122 },
  100. { },
  101. };
  102. /* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
  103. static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
  104. unsigned long prate)
  105. {
  106. struct ac100_clkout *clk = to_ac100_clkout(hw);
  107. unsigned int reg, div;
  108. regmap_read(clk->regmap, clk->offset, &reg);
  109. /* Handle pre-divider first */
  110. if (prate != AC100_RTC_32K_RATE) {
  111. div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
  112. ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
  113. prate = divider_recalc_rate(hw, prate, div,
  114. ac100_clkout_prediv, 0,
  115. AC100_CLKOUT_PRE_DIV_WIDTH);
  116. }
  117. div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
  118. (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
  119. return divider_recalc_rate(hw, prate, div, NULL,
  120. CLK_DIVIDER_POWER_OF_TWO,
  121. AC100_CLKOUT_DIV_WIDTH);
  122. }
  123. static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
  124. unsigned long prate)
  125. {
  126. unsigned long best_rate = 0, tmp_rate, tmp_prate;
  127. int i;
  128. if (prate == AC100_RTC_32K_RATE)
  129. return divider_round_rate(hw, rate, &prate, NULL,
  130. AC100_CLKOUT_DIV_WIDTH,
  131. CLK_DIVIDER_POWER_OF_TWO);
  132. for (i = 0; ac100_clkout_prediv[i].div; i++) {
  133. tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
  134. tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
  135. AC100_CLKOUT_DIV_WIDTH,
  136. CLK_DIVIDER_POWER_OF_TWO);
  137. if (tmp_rate > rate)
  138. continue;
  139. if (rate - tmp_rate < best_rate - tmp_rate)
  140. best_rate = tmp_rate;
  141. }
  142. return best_rate;
  143. }
  144. static int ac100_clkout_determine_rate(struct clk_hw *hw,
  145. struct clk_rate_request *req)
  146. {
  147. struct clk_hw *best_parent;
  148. unsigned long best = 0;
  149. int i, num_parents = clk_hw_get_num_parents(hw);
  150. for (i = 0; i < num_parents; i++) {
  151. struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
  152. unsigned long tmp, prate;
  153. /*
  154. * The clock has two parents, one is a fixed clock which is
  155. * internally registered by the ac100 driver. The other parent
  156. * is a clock from the codec side of the chip, which we
  157. * properly declare and reference in the devicetree and is
  158. * not implemented in any driver right now.
  159. * If the clock core looks for the parent of that second
  160. * missing clock, it can't find one that is registered and
  161. * returns NULL.
  162. * So we end up in a situation where clk_hw_get_num_parents
  163. * returns the amount of clocks we can be parented to, but
  164. * clk_hw_get_parent_by_index will not return the orphan
  165. * clocks.
  166. * Thus we need to check if the parent exists before
  167. * we get the parent rate, so we could use the RTC
  168. * without waiting for the codec to be supported.
  169. */
  170. if (!parent)
  171. continue;
  172. prate = clk_hw_get_rate(parent);
  173. tmp = ac100_clkout_round_rate(hw, req->rate, prate);
  174. if (tmp > req->rate)
  175. continue;
  176. if (req->rate - tmp < req->rate - best) {
  177. best = tmp;
  178. best_parent = parent;
  179. }
  180. }
  181. if (!best)
  182. return -EINVAL;
  183. req->best_parent_hw = best_parent;
  184. req->best_parent_rate = best;
  185. req->rate = best;
  186. return 0;
  187. }
  188. static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
  189. unsigned long prate)
  190. {
  191. struct ac100_clkout *clk = to_ac100_clkout(hw);
  192. int div = 0, pre_div = 0;
  193. do {
  194. div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
  195. prate, NULL, AC100_CLKOUT_DIV_WIDTH,
  196. CLK_DIVIDER_POWER_OF_TWO);
  197. if (div >= 0)
  198. break;
  199. } while (prate != AC100_RTC_32K_RATE &&
  200. ac100_clkout_prediv[++pre_div].div);
  201. if (div < 0)
  202. return div;
  203. pre_div = ac100_clkout_prediv[pre_div].val;
  204. regmap_update_bits(clk->regmap, clk->offset,
  205. ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
  206. ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
  207. (div - 1) << AC100_CLKOUT_DIV_SHIFT |
  208. (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
  209. return 0;
  210. }
  211. static int ac100_clkout_prepare(struct clk_hw *hw)
  212. {
  213. struct ac100_clkout *clk = to_ac100_clkout(hw);
  214. return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
  215. AC100_CLKOUT_EN);
  216. }
  217. static void ac100_clkout_unprepare(struct clk_hw *hw)
  218. {
  219. struct ac100_clkout *clk = to_ac100_clkout(hw);
  220. regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
  221. }
  222. static int ac100_clkout_is_prepared(struct clk_hw *hw)
  223. {
  224. struct ac100_clkout *clk = to_ac100_clkout(hw);
  225. unsigned int reg;
  226. regmap_read(clk->regmap, clk->offset, &reg);
  227. return reg & AC100_CLKOUT_EN;
  228. }
  229. static u8 ac100_clkout_get_parent(struct clk_hw *hw)
  230. {
  231. struct ac100_clkout *clk = to_ac100_clkout(hw);
  232. unsigned int reg;
  233. regmap_read(clk->regmap, clk->offset, &reg);
  234. return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
  235. }
  236. static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
  237. {
  238. struct ac100_clkout *clk = to_ac100_clkout(hw);
  239. return regmap_update_bits(clk->regmap, clk->offset,
  240. BIT(AC100_CLKOUT_MUX_SHIFT),
  241. index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
  242. }
  243. static const struct clk_ops ac100_clkout_ops = {
  244. .prepare = ac100_clkout_prepare,
  245. .unprepare = ac100_clkout_unprepare,
  246. .is_prepared = ac100_clkout_is_prepared,
  247. .recalc_rate = ac100_clkout_recalc_rate,
  248. .determine_rate = ac100_clkout_determine_rate,
  249. .get_parent = ac100_clkout_get_parent,
  250. .set_parent = ac100_clkout_set_parent,
  251. .set_rate = ac100_clkout_set_rate,
  252. };
  253. static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
  254. {
  255. struct device_node *np = chip->dev->of_node;
  256. const char *parents[2] = {AC100_RTC_32K_NAME};
  257. int i, ret;
  258. chip->clk_data = devm_kzalloc(chip->dev,
  259. struct_size(chip->clk_data, hws,
  260. AC100_CLKOUT_NUM),
  261. GFP_KERNEL);
  262. if (!chip->clk_data)
  263. return -ENOMEM;
  264. chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
  265. AC100_RTC_32K_NAME,
  266. NULL, 0,
  267. AC100_RTC_32K_RATE);
  268. if (IS_ERR(chip->rtc_32k_clk)) {
  269. ret = PTR_ERR(chip->rtc_32k_clk);
  270. dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
  271. ret);
  272. return ret;
  273. }
  274. parents[1] = of_clk_get_parent_name(np, 0);
  275. if (!parents[1]) {
  276. dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
  277. return -EINVAL;
  278. }
  279. for (i = 0; i < AC100_CLKOUT_NUM; i++) {
  280. struct ac100_clkout *clk = &chip->clks[i];
  281. struct clk_init_data init = {
  282. .name = ac100_clkout_names[i],
  283. .ops = &ac100_clkout_ops,
  284. .parent_names = parents,
  285. .num_parents = ARRAY_SIZE(parents),
  286. .flags = 0,
  287. };
  288. of_property_read_string_index(np, "clock-output-names",
  289. i, &init.name);
  290. clk->regmap = chip->regmap;
  291. clk->offset = AC100_CLKOUT_CTRL1 + i;
  292. clk->hw.init = &init;
  293. ret = devm_clk_hw_register(chip->dev, &clk->hw);
  294. if (ret) {
  295. dev_err(chip->dev, "Failed to register clk '%s': %d\n",
  296. init.name, ret);
  297. goto err_unregister_rtc_32k;
  298. }
  299. chip->clk_data->hws[i] = &clk->hw;
  300. }
  301. chip->clk_data->num = i;
  302. ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
  303. if (ret)
  304. goto err_unregister_rtc_32k;
  305. return 0;
  306. err_unregister_rtc_32k:
  307. clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
  308. return ret;
  309. }
  310. static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
  311. {
  312. of_clk_del_provider(chip->dev->of_node);
  313. clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
  314. }
  315. /**
  316. * RTC related bits
  317. */
  318. static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
  319. {
  320. struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
  321. struct regmap *regmap = chip->regmap;
  322. u16 reg[7];
  323. int ret;
  324. ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
  325. if (ret)
  326. return ret;
  327. rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
  328. rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
  329. rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
  330. rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
  331. rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
  332. rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
  333. rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
  334. AC100_YEAR_OFF;
  335. return 0;
  336. }
  337. static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
  338. {
  339. struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
  340. struct regmap *regmap = chip->regmap;
  341. int year;
  342. u16 reg[8];
  343. /* our RTC has a limited year range... */
  344. year = rtc_tm->tm_year - AC100_YEAR_OFF;
  345. if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
  346. dev_err(dev, "rtc only supports year in range %d - %d\n",
  347. AC100_YEAR_MIN, AC100_YEAR_MAX);
  348. return -EINVAL;
  349. }
  350. /* convert to BCD */
  351. reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
  352. reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
  353. reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
  354. reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
  355. reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
  356. reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
  357. reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
  358. /* trigger write */
  359. reg[7] = AC100_RTC_UPD_TRIGGER;
  360. /* Is it a leap year? */
  361. if (is_leap_year(year + AC100_YEAR_OFF + 1900))
  362. reg[6] |= AC100_RTC_YEA_LEAP;
  363. return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
  364. }
  365. static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
  366. {
  367. struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
  368. struct regmap *regmap = chip->regmap;
  369. unsigned int val;
  370. val = en ? AC100_ALM_INT_ENABLE : 0;
  371. return regmap_write(regmap, AC100_ALM_INT_ENA, val);
  372. }
  373. static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  374. {
  375. struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
  376. struct regmap *regmap = chip->regmap;
  377. struct rtc_time *alrm_tm = &alrm->time;
  378. u16 reg[7];
  379. unsigned int val;
  380. int ret;
  381. ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
  382. if (ret)
  383. return ret;
  384. alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
  385. ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
  386. if (ret)
  387. return ret;
  388. alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
  389. alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
  390. alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
  391. alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
  392. alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
  393. alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
  394. alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
  395. AC100_YEAR_OFF;
  396. return 0;
  397. }
  398. static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  399. {
  400. struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
  401. struct regmap *regmap = chip->regmap;
  402. struct rtc_time *alrm_tm = &alrm->time;
  403. u16 reg[8];
  404. int year;
  405. int ret;
  406. /* our alarm has a limited year range... */
  407. year = alrm_tm->tm_year - AC100_YEAR_OFF;
  408. if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
  409. dev_err(dev, "alarm only supports year in range %d - %d\n",
  410. AC100_YEAR_MIN, AC100_YEAR_MAX);
  411. return -EINVAL;
  412. }
  413. /* convert to BCD */
  414. reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) |
  415. AC100_ALM_ENABLE_FLAG;
  416. reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) |
  417. AC100_ALM_ENABLE_FLAG;
  418. reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
  419. AC100_ALM_ENABLE_FLAG;
  420. /* Do not enable weekday alarm */
  421. reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
  422. reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
  423. AC100_ALM_ENABLE_FLAG;
  424. reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) |
  425. AC100_ALM_ENABLE_FLAG;
  426. reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
  427. AC100_ALM_ENABLE_FLAG;
  428. /* trigger write */
  429. reg[7] = AC100_ALM_UPD_TRIGGER;
  430. ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
  431. if (ret)
  432. return ret;
  433. return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
  434. }
  435. static irqreturn_t ac100_rtc_irq(int irq, void *data)
  436. {
  437. struct ac100_rtc_dev *chip = data;
  438. struct regmap *regmap = chip->regmap;
  439. unsigned int val = 0;
  440. int ret;
  441. mutex_lock(&chip->rtc->ops_lock);
  442. /* read status */
  443. ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
  444. if (ret)
  445. goto out;
  446. if (val & AC100_ALM_INT_ENABLE) {
  447. /* signal rtc framework */
  448. rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
  449. /* clear status */
  450. ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
  451. if (ret)
  452. goto out;
  453. /* disable interrupt */
  454. ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
  455. if (ret)
  456. goto out;
  457. }
  458. out:
  459. mutex_unlock(&chip->rtc->ops_lock);
  460. return IRQ_HANDLED;
  461. }
  462. static const struct rtc_class_ops ac100_rtc_ops = {
  463. .read_time = ac100_rtc_get_time,
  464. .set_time = ac100_rtc_set_time,
  465. .read_alarm = ac100_rtc_get_alarm,
  466. .set_alarm = ac100_rtc_set_alarm,
  467. .alarm_irq_enable = ac100_rtc_alarm_irq_enable,
  468. };
  469. static int ac100_rtc_probe(struct platform_device *pdev)
  470. {
  471. struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
  472. struct ac100_rtc_dev *chip;
  473. int ret;
  474. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  475. if (!chip)
  476. return -ENOMEM;
  477. platform_set_drvdata(pdev, chip);
  478. chip->dev = &pdev->dev;
  479. chip->regmap = ac100->regmap;
  480. chip->irq = platform_get_irq(pdev, 0);
  481. if (chip->irq < 0)
  482. return chip->irq;
  483. chip->rtc = devm_rtc_allocate_device(&pdev->dev);
  484. if (IS_ERR(chip->rtc))
  485. return PTR_ERR(chip->rtc);
  486. chip->rtc->ops = &ac100_rtc_ops;
  487. ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
  488. ac100_rtc_irq,
  489. IRQF_SHARED | IRQF_ONESHOT,
  490. dev_name(&pdev->dev), chip);
  491. if (ret) {
  492. dev_err(&pdev->dev, "Could not request IRQ\n");
  493. return ret;
  494. }
  495. /* always use 24 hour mode */
  496. regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
  497. AC100_RTC_CTRL_24HOUR);
  498. /* disable counter alarm interrupt */
  499. regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
  500. /* clear counter alarm pending interrupts */
  501. regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
  502. ret = ac100_rtc_register_clks(chip);
  503. if (ret)
  504. return ret;
  505. return rtc_register_device(chip->rtc);
  506. }
  507. static int ac100_rtc_remove(struct platform_device *pdev)
  508. {
  509. struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);
  510. ac100_rtc_unregister_clks(chip);
  511. return 0;
  512. }
  513. static const struct of_device_id ac100_rtc_match[] = {
  514. { .compatible = "x-powers,ac100-rtc" },
  515. { },
  516. };
  517. MODULE_DEVICE_TABLE(of, ac100_rtc_match);
  518. static struct platform_driver ac100_rtc_driver = {
  519. .probe = ac100_rtc_probe,
  520. .remove = ac100_rtc_remove,
  521. .driver = {
  522. .name = "ac100-rtc",
  523. .of_match_table = of_match_ptr(ac100_rtc_match),
  524. },
  525. };
  526. module_platform_driver(ac100_rtc_driver);
  527. MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
  528. MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
  529. MODULE_LICENSE("GPL v2");