rtc-ab-eoz9.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Real Time Clock driver for AB-RTCMC-32.768kHz-EOZ9 chip.
  4. * Copyright (C) 2019 Orolia
  5. *
  6. */
  7. #include <linux/module.h>
  8. #include <linux/rtc.h>
  9. #include <linux/i2c.h>
  10. #include <linux/bcd.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <linux/hwmon.h>
  14. #include <linux/hwmon-sysfs.h>
  15. #define ABEOZ9_REG_CTRL1 0x00
  16. #define ABEOZ9_REG_CTRL1_MASK GENMASK(7, 0)
  17. #define ABEOZ9_REG_CTRL1_WE BIT(0)
  18. #define ABEOZ9_REG_CTRL1_TE BIT(1)
  19. #define ABEOZ9_REG_CTRL1_TAR BIT(2)
  20. #define ABEOZ9_REG_CTRL1_EERE BIT(3)
  21. #define ABEOZ9_REG_CTRL1_SRON BIT(4)
  22. #define ABEOZ9_REG_CTRL1_TD0 BIT(5)
  23. #define ABEOZ9_REG_CTRL1_TD1 BIT(6)
  24. #define ABEOZ9_REG_CTRL1_CLKINT BIT(7)
  25. #define ABEOZ9_REG_CTRL_INT 0x01
  26. #define ABEOZ9_REG_CTRL_INT_AIE BIT(0)
  27. #define ABEOZ9_REG_CTRL_INT_TIE BIT(1)
  28. #define ABEOZ9_REG_CTRL_INT_V1IE BIT(2)
  29. #define ABEOZ9_REG_CTRL_INT_V2IE BIT(3)
  30. #define ABEOZ9_REG_CTRL_INT_SRIE BIT(4)
  31. #define ABEOZ9_REG_CTRL_INT_FLAG 0x02
  32. #define ABEOZ9_REG_CTRL_INT_FLAG_AF BIT(0)
  33. #define ABEOZ9_REG_CTRL_INT_FLAG_TF BIT(1)
  34. #define ABEOZ9_REG_CTRL_INT_FLAG_V1IF BIT(2)
  35. #define ABEOZ9_REG_CTRL_INT_FLAG_V2IF BIT(3)
  36. #define ABEOZ9_REG_CTRL_INT_FLAG_SRF BIT(4)
  37. #define ABEOZ9_REG_CTRL_STATUS 0x03
  38. #define ABEOZ9_REG_CTRL_STATUS_V1F BIT(2)
  39. #define ABEOZ9_REG_CTRL_STATUS_V2F BIT(3)
  40. #define ABEOZ9_REG_CTRL_STATUS_SR BIT(4)
  41. #define ABEOZ9_REG_CTRL_STATUS_PON BIT(5)
  42. #define ABEOZ9_REG_CTRL_STATUS_EEBUSY BIT(7)
  43. #define ABEOZ9_REG_SEC 0x08
  44. #define ABEOZ9_REG_MIN 0x09
  45. #define ABEOZ9_REG_HOURS 0x0A
  46. #define ABEOZ9_HOURS_PM BIT(6)
  47. #define ABEOZ9_REG_DAYS 0x0B
  48. #define ABEOZ9_REG_WEEKDAYS 0x0C
  49. #define ABEOZ9_REG_MONTHS 0x0D
  50. #define ABEOZ9_REG_YEARS 0x0E
  51. #define ABEOZ9_SEC_LEN 7
  52. #define ABEOZ9_REG_REG_TEMP 0x20
  53. #define ABEOZ953_TEMP_MAX 120
  54. #define ABEOZ953_TEMP_MIN -60
  55. #define ABEOZ9_REG_EEPROM 0x30
  56. #define ABEOZ9_REG_EEPROM_MASK GENMASK(8, 0)
  57. #define ABEOZ9_REG_EEPROM_THP BIT(0)
  58. #define ABEOZ9_REG_EEPROM_THE BIT(1)
  59. #define ABEOZ9_REG_EEPROM_FD0 BIT(2)
  60. #define ABEOZ9_REG_EEPROM_FD1 BIT(3)
  61. #define ABEOZ9_REG_EEPROM_R1K BIT(4)
  62. #define ABEOZ9_REG_EEPROM_R5K BIT(5)
  63. #define ABEOZ9_REG_EEPROM_R20K BIT(6)
  64. #define ABEOZ9_REG_EEPROM_R80K BIT(7)
  65. struct abeoz9_rtc_data {
  66. struct rtc_device *rtc;
  67. struct regmap *regmap;
  68. struct device *hwmon_dev;
  69. };
  70. static int abeoz9_check_validity(struct device *dev)
  71. {
  72. struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
  73. struct regmap *regmap = data->regmap;
  74. int ret;
  75. int val;
  76. ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
  77. if (ret < 0) {
  78. dev_err(dev,
  79. "unable to get CTRL_STATUS register (%d)\n", ret);
  80. return ret;
  81. }
  82. if (val & ABEOZ9_REG_CTRL_STATUS_PON) {
  83. dev_warn(dev, "power-on reset detected, date is invalid\n");
  84. return -EINVAL;
  85. }
  86. if (val & ABEOZ9_REG_CTRL_STATUS_V1F) {
  87. dev_warn(dev,
  88. "voltage drops below VLOW1 threshold, date is invalid\n");
  89. return -EINVAL;
  90. }
  91. if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
  92. dev_warn(dev,
  93. "voltage drops below VLOW2 threshold, date is invalid\n");
  94. return -EINVAL;
  95. }
  96. return 0;
  97. }
  98. static int abeoz9_reset_validity(struct regmap *regmap)
  99. {
  100. return regmap_update_bits(regmap, ABEOZ9_REG_CTRL_STATUS,
  101. ABEOZ9_REG_CTRL_STATUS_V1F |
  102. ABEOZ9_REG_CTRL_STATUS_V2F |
  103. ABEOZ9_REG_CTRL_STATUS_PON,
  104. 0);
  105. }
  106. static int abeoz9_rtc_get_time(struct device *dev, struct rtc_time *tm)
  107. {
  108. struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
  109. u8 regs[ABEOZ9_SEC_LEN];
  110. int ret;
  111. ret = abeoz9_check_validity(dev);
  112. if (ret)
  113. return ret;
  114. ret = regmap_bulk_read(data->regmap, ABEOZ9_REG_SEC,
  115. regs,
  116. sizeof(regs));
  117. if (ret) {
  118. dev_err(dev, "reading RTC time failed (%d)\n", ret);
  119. return ret;
  120. }
  121. tm->tm_sec = bcd2bin(regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] & 0x7F);
  122. tm->tm_min = bcd2bin(regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] & 0x7F);
  123. if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM) {
  124. tm->tm_hour =
  125. bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & 0x1f);
  126. if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM)
  127. tm->tm_hour += 12;
  128. } else {
  129. tm->tm_hour = bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC]);
  130. }
  131. tm->tm_mday = bcd2bin(regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC]);
  132. tm->tm_wday = bcd2bin(regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC]);
  133. tm->tm_mon = bcd2bin(regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC]) - 1;
  134. tm->tm_year = bcd2bin(regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC]) + 100;
  135. return ret;
  136. }
  137. static int abeoz9_rtc_set_time(struct device *dev, struct rtc_time *tm)
  138. {
  139. struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
  140. struct regmap *regmap = data->regmap;
  141. u8 regs[ABEOZ9_SEC_LEN];
  142. int ret;
  143. regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_sec);
  144. regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_min);
  145. regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_hour);
  146. regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mday);
  147. regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_wday);
  148. regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mon + 1);
  149. regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_year - 100);
  150. ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_SEC,
  151. regs,
  152. sizeof(regs));
  153. if (ret) {
  154. dev_err(dev, "set RTC time failed (%d)\n", ret);
  155. return ret;
  156. }
  157. return abeoz9_reset_validity(regmap);
  158. }
  159. static int abeoz9_trickle_parse_dt(struct device_node *node)
  160. {
  161. u32 ohms = 0;
  162. if (of_property_read_u32(node, "trickle-resistor-ohms", &ohms))
  163. return 0;
  164. switch (ohms) {
  165. case 1000:
  166. return ABEOZ9_REG_EEPROM_R1K;
  167. case 5000:
  168. return ABEOZ9_REG_EEPROM_R5K;
  169. case 20000:
  170. return ABEOZ9_REG_EEPROM_R20K;
  171. case 80000:
  172. return ABEOZ9_REG_EEPROM_R80K;
  173. default:
  174. return 0;
  175. }
  176. }
  177. static int abeoz9_rtc_setup(struct device *dev, struct device_node *node)
  178. {
  179. struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
  180. struct regmap *regmap = data->regmap;
  181. int ret;
  182. /* Enable Self Recovery, Clock for Watch and EEPROM refresh functions */
  183. ret = regmap_update_bits(regmap, ABEOZ9_REG_CTRL1,
  184. ABEOZ9_REG_CTRL1_MASK,
  185. ABEOZ9_REG_CTRL1_WE |
  186. ABEOZ9_REG_CTRL1_EERE |
  187. ABEOZ9_REG_CTRL1_SRON);
  188. if (ret < 0) {
  189. dev_err(dev, "unable to set CTRL_1 register (%d)\n", ret);
  190. return ret;
  191. }
  192. ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT, 0);
  193. if (ret < 0) {
  194. dev_err(dev,
  195. "unable to set control CTRL_INT register (%d)\n",
  196. ret);
  197. return ret;
  198. }
  199. ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT_FLAG, 0);
  200. if (ret < 0) {
  201. dev_err(dev,
  202. "unable to set control CTRL_INT_FLAG register (%d)\n",
  203. ret);
  204. return ret;
  205. }
  206. ret = abeoz9_trickle_parse_dt(node);
  207. /* Enable built-in termometer */
  208. ret |= ABEOZ9_REG_EEPROM_THE;
  209. ret = regmap_update_bits(regmap, ABEOZ9_REG_EEPROM,
  210. ABEOZ9_REG_EEPROM_MASK,
  211. ret);
  212. if (ret < 0) {
  213. dev_err(dev, "unable to set EEPROM register (%d)\n", ret);
  214. return ret;
  215. }
  216. return ret;
  217. }
  218. static const struct rtc_class_ops rtc_ops = {
  219. .read_time = abeoz9_rtc_get_time,
  220. .set_time = abeoz9_rtc_set_time,
  221. };
  222. static const struct regmap_config abeoz9_rtc_regmap_config = {
  223. .reg_bits = 8,
  224. .val_bits = 8,
  225. };
  226. #if IS_REACHABLE(CONFIG_HWMON)
  227. static int abeoz9z3_temp_read(struct device *dev,
  228. enum hwmon_sensor_types type,
  229. u32 attr, int channel, long *temp)
  230. {
  231. struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
  232. struct regmap *regmap = data->regmap;
  233. int ret;
  234. unsigned int val;
  235. ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
  236. if (ret < 0)
  237. return ret;
  238. if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) ||
  239. (val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
  240. dev_err(dev,
  241. "thermometer might be disabled due to low voltage\n");
  242. return -EINVAL;
  243. }
  244. switch (attr) {
  245. case hwmon_temp_input:
  246. ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val);
  247. if (ret < 0)
  248. return ret;
  249. *temp = 1000 * (val + ABEOZ953_TEMP_MIN);
  250. return 0;
  251. case hwmon_temp_max:
  252. *temp = 1000 * ABEOZ953_TEMP_MAX;
  253. return 0;
  254. case hwmon_temp_min:
  255. *temp = 1000 * ABEOZ953_TEMP_MIN;
  256. return 0;
  257. default:
  258. return -EOPNOTSUPP;
  259. }
  260. }
  261. static umode_t abeoz9_is_visible(const void *data,
  262. enum hwmon_sensor_types type,
  263. u32 attr, int channel)
  264. {
  265. switch (attr) {
  266. case hwmon_temp_input:
  267. case hwmon_temp_max:
  268. case hwmon_temp_min:
  269. return 0444;
  270. default:
  271. return 0;
  272. }
  273. }
  274. static const u32 abeoz9_chip_config[] = {
  275. HWMON_C_REGISTER_TZ,
  276. 0
  277. };
  278. static const struct hwmon_channel_info abeoz9_chip = {
  279. .type = hwmon_chip,
  280. .config = abeoz9_chip_config,
  281. };
  282. static const u32 abeoz9_temp_config[] = {
  283. HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN,
  284. 0
  285. };
  286. static const struct hwmon_channel_info abeoz9_temp = {
  287. .type = hwmon_temp,
  288. .config = abeoz9_temp_config,
  289. };
  290. static const struct hwmon_channel_info *abeoz9_info[] = {
  291. &abeoz9_chip,
  292. &abeoz9_temp,
  293. NULL
  294. };
  295. static const struct hwmon_ops abeoz9_hwmon_ops = {
  296. .is_visible = abeoz9_is_visible,
  297. .read = abeoz9z3_temp_read,
  298. };
  299. static const struct hwmon_chip_info abeoz9_chip_info = {
  300. .ops = &abeoz9_hwmon_ops,
  301. .info = abeoz9_info,
  302. };
  303. static void abeoz9_hwmon_register(struct device *dev,
  304. struct abeoz9_rtc_data *data)
  305. {
  306. data->hwmon_dev =
  307. devm_hwmon_device_register_with_info(dev,
  308. "abeoz9",
  309. data,
  310. &abeoz9_chip_info,
  311. NULL);
  312. if (IS_ERR(data->hwmon_dev)) {
  313. dev_warn(dev, "unable to register hwmon device %ld\n",
  314. PTR_ERR(data->hwmon_dev));
  315. }
  316. }
  317. #else
  318. static void abeoz9_hwmon_register(struct device *dev,
  319. struct abeoz9_rtc_data *data)
  320. {
  321. }
  322. #endif
  323. static int abeoz9_probe(struct i2c_client *client,
  324. const struct i2c_device_id *id)
  325. {
  326. struct abeoz9_rtc_data *data = NULL;
  327. struct device *dev = &client->dev;
  328. struct regmap *regmap;
  329. int ret;
  330. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
  331. I2C_FUNC_SMBUS_BYTE_DATA |
  332. I2C_FUNC_SMBUS_I2C_BLOCK))
  333. return -ENODEV;
  334. regmap = devm_regmap_init_i2c(client, &abeoz9_rtc_regmap_config);
  335. if (IS_ERR(regmap)) {
  336. ret = PTR_ERR(regmap);
  337. dev_err(dev, "regmap allocation failed: %d\n", ret);
  338. return ret;
  339. }
  340. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  341. if (!data)
  342. return -ENOMEM;
  343. data->regmap = regmap;
  344. dev_set_drvdata(dev, data);
  345. ret = abeoz9_rtc_setup(dev, client->dev.of_node);
  346. if (ret)
  347. return ret;
  348. data->rtc = devm_rtc_allocate_device(dev);
  349. ret = PTR_ERR_OR_ZERO(data->rtc);
  350. if (ret)
  351. return ret;
  352. data->rtc->ops = &rtc_ops;
  353. data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
  354. data->rtc->range_max = RTC_TIMESTAMP_END_2099;
  355. ret = rtc_register_device(data->rtc);
  356. if (ret)
  357. return ret;
  358. abeoz9_hwmon_register(dev, data);
  359. return 0;
  360. }
  361. #ifdef CONFIG_OF
  362. static const struct of_device_id abeoz9_dt_match[] = {
  363. { .compatible = "abracon,abeoz9" },
  364. { },
  365. };
  366. MODULE_DEVICE_TABLE(of, abeoz9_dt_match);
  367. #endif
  368. static const struct i2c_device_id abeoz9_id[] = {
  369. { "abeoz9", 0 },
  370. { }
  371. };
  372. static struct i2c_driver abeoz9_driver = {
  373. .driver = {
  374. .name = "rtc-ab-eoz9",
  375. .of_match_table = of_match_ptr(abeoz9_dt_match),
  376. },
  377. .probe = abeoz9_probe,
  378. .id_table = abeoz9_id,
  379. };
  380. module_i2c_driver(abeoz9_driver);
  381. MODULE_AUTHOR("Artem Panfilov <panfilov.artyom@gmail.com>");
  382. MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-EOZ9 RTC driver");
  383. MODULE_LICENSE("GPL");