reset-npcm.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Nuvoton Technology corporation.
  3. #include <linux/delay.h>
  4. #include <linux/err.h>
  5. #include <linux/io.h>
  6. #include <linux/init.h>
  7. #include <linux/of.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/reboot.h>
  11. #include <linux/reset-controller.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/regmap.h>
  15. #include <linux/of_address.h>
  16. /* NPCM7xx GCR registers */
  17. #define NPCM_MDLR_OFFSET 0x7C
  18. #define NPCM_MDLR_USBD0 BIT(9)
  19. #define NPCM_MDLR_USBD1 BIT(8)
  20. #define NPCM_MDLR_USBD2_4 BIT(21)
  21. #define NPCM_MDLR_USBD5_9 BIT(22)
  22. #define NPCM_USB1PHYCTL_OFFSET 0x140
  23. #define NPCM_USB2PHYCTL_OFFSET 0x144
  24. #define NPCM_USBXPHYCTL_RS BIT(28)
  25. /* NPCM7xx Reset registers */
  26. #define NPCM_SWRSTR 0x14
  27. #define NPCM_SWRST BIT(2)
  28. #define NPCM_IPSRST1 0x20
  29. #define NPCM_IPSRST1_USBD1 BIT(5)
  30. #define NPCM_IPSRST1_USBD2 BIT(8)
  31. #define NPCM_IPSRST1_USBD3 BIT(25)
  32. #define NPCM_IPSRST1_USBD4 BIT(22)
  33. #define NPCM_IPSRST1_USBD5 BIT(23)
  34. #define NPCM_IPSRST1_USBD6 BIT(24)
  35. #define NPCM_IPSRST2 0x24
  36. #define NPCM_IPSRST2_USB_HOST BIT(26)
  37. #define NPCM_IPSRST3 0x34
  38. #define NPCM_IPSRST3_USBD0 BIT(4)
  39. #define NPCM_IPSRST3_USBD7 BIT(5)
  40. #define NPCM_IPSRST3_USBD8 BIT(6)
  41. #define NPCM_IPSRST3_USBD9 BIT(7)
  42. #define NPCM_IPSRST3_USBPHY1 BIT(24)
  43. #define NPCM_IPSRST3_USBPHY2 BIT(25)
  44. #define NPCM_RC_RESETS_PER_REG 32
  45. #define NPCM_MASK_RESETS GENMASK(4, 0)
  46. struct npcm_rc_data {
  47. struct reset_controller_dev rcdev;
  48. struct notifier_block restart_nb;
  49. u32 sw_reset_number;
  50. void __iomem *base;
  51. spinlock_t lock;
  52. };
  53. #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
  54. static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
  55. void *cmd)
  56. {
  57. struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
  58. restart_nb);
  59. writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
  60. mdelay(1000);
  61. pr_emerg("%s: unable to restart system\n", __func__);
  62. return NOTIFY_DONE;
  63. }
  64. static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
  65. unsigned long id, bool set)
  66. {
  67. struct npcm_rc_data *rc = to_rc_data(rcdev);
  68. unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
  69. unsigned int ctrl_offset = id >> 8;
  70. unsigned long flags;
  71. u32 stat;
  72. spin_lock_irqsave(&rc->lock, flags);
  73. stat = readl(rc->base + ctrl_offset);
  74. if (set)
  75. writel(stat | rst_bit, rc->base + ctrl_offset);
  76. else
  77. writel(stat & ~rst_bit, rc->base + ctrl_offset);
  78. spin_unlock_irqrestore(&rc->lock, flags);
  79. return 0;
  80. }
  81. static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
  82. {
  83. return npcm_rc_setclear_reset(rcdev, id, true);
  84. }
  85. static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
  86. unsigned long id)
  87. {
  88. return npcm_rc_setclear_reset(rcdev, id, false);
  89. }
  90. static int npcm_rc_status(struct reset_controller_dev *rcdev,
  91. unsigned long id)
  92. {
  93. struct npcm_rc_data *rc = to_rc_data(rcdev);
  94. unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
  95. unsigned int ctrl_offset = id >> 8;
  96. return (readl(rc->base + ctrl_offset) & rst_bit);
  97. }
  98. static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
  99. const struct of_phandle_args *reset_spec)
  100. {
  101. unsigned int offset, bit;
  102. offset = reset_spec->args[0];
  103. if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 &&
  104. offset != NPCM_IPSRST3) {
  105. dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
  106. return -EINVAL;
  107. }
  108. bit = reset_spec->args[1];
  109. if (bit >= NPCM_RC_RESETS_PER_REG) {
  110. dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
  111. return -EINVAL;
  112. }
  113. return (offset << 8) | bit;
  114. }
  115. static const struct of_device_id npcm_rc_match[] = {
  116. { .compatible = "nuvoton,npcm750-reset",
  117. .data = (void *)"nuvoton,npcm750-gcr" },
  118. { }
  119. };
  120. /*
  121. * The following procedure should be observed in USB PHY, USB device and
  122. * USB host initialization at BMC boot
  123. */
  124. static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
  125. {
  126. u32 mdlr, iprst1, iprst2, iprst3;
  127. struct device *dev = &pdev->dev;
  128. struct regmap *gcr_regmap;
  129. u32 ipsrst1_bits = 0;
  130. u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
  131. u32 ipsrst3_bits = 0;
  132. const char *gcr_dt;
  133. gcr_dt = (const char *)
  134. of_match_device(dev->driver->of_match_table, dev)->data;
  135. gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
  136. if (IS_ERR(gcr_regmap)) {
  137. dev_err(&pdev->dev, "Failed to find %s\n", gcr_dt);
  138. return PTR_ERR(gcr_regmap);
  139. }
  140. /* checking which USB device is enabled */
  141. regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
  142. if (!(mdlr & NPCM_MDLR_USBD0))
  143. ipsrst3_bits |= NPCM_IPSRST3_USBD0;
  144. if (!(mdlr & NPCM_MDLR_USBD1))
  145. ipsrst1_bits |= NPCM_IPSRST1_USBD1;
  146. if (!(mdlr & NPCM_MDLR_USBD2_4))
  147. ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
  148. NPCM_IPSRST1_USBD3 |
  149. NPCM_IPSRST1_USBD4);
  150. if (!(mdlr & NPCM_MDLR_USBD0)) {
  151. ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
  152. NPCM_IPSRST1_USBD6);
  153. ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
  154. NPCM_IPSRST3_USBD8 |
  155. NPCM_IPSRST3_USBD9);
  156. }
  157. /* assert reset USB PHY and USB devices */
  158. iprst1 = readl(rc->base + NPCM_IPSRST1);
  159. iprst2 = readl(rc->base + NPCM_IPSRST2);
  160. iprst3 = readl(rc->base + NPCM_IPSRST3);
  161. iprst1 |= ipsrst1_bits;
  162. iprst2 |= ipsrst2_bits;
  163. iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
  164. NPCM_IPSRST3_USBPHY2);
  165. writel(iprst1, rc->base + NPCM_IPSRST1);
  166. writel(iprst2, rc->base + NPCM_IPSRST2);
  167. writel(iprst3, rc->base + NPCM_IPSRST3);
  168. /* clear USB PHY RS bit */
  169. regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  170. NPCM_USBXPHYCTL_RS, 0);
  171. regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  172. NPCM_USBXPHYCTL_RS, 0);
  173. /* deassert reset USB PHY */
  174. iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
  175. writel(iprst3, rc->base + NPCM_IPSRST3);
  176. udelay(50);
  177. /* set USB PHY RS bit */
  178. regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
  179. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  180. regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
  181. NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
  182. /* deassert reset USB devices*/
  183. iprst1 &= ~ipsrst1_bits;
  184. iprst2 &= ~ipsrst2_bits;
  185. iprst3 &= ~ipsrst3_bits;
  186. writel(iprst1, rc->base + NPCM_IPSRST1);
  187. writel(iprst2, rc->base + NPCM_IPSRST2);
  188. writel(iprst3, rc->base + NPCM_IPSRST3);
  189. return 0;
  190. }
  191. static const struct reset_control_ops npcm_rc_ops = {
  192. .assert = npcm_rc_assert,
  193. .deassert = npcm_rc_deassert,
  194. .status = npcm_rc_status,
  195. };
  196. static int npcm_rc_probe(struct platform_device *pdev)
  197. {
  198. struct npcm_rc_data *rc;
  199. int ret;
  200. rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
  201. if (!rc)
  202. return -ENOMEM;
  203. rc->base = devm_platform_ioremap_resource(pdev, 0);
  204. if (IS_ERR(rc->base))
  205. return PTR_ERR(rc->base);
  206. spin_lock_init(&rc->lock);
  207. rc->rcdev.owner = THIS_MODULE;
  208. rc->rcdev.ops = &npcm_rc_ops;
  209. rc->rcdev.of_node = pdev->dev.of_node;
  210. rc->rcdev.of_reset_n_cells = 2;
  211. rc->rcdev.of_xlate = npcm_reset_xlate;
  212. platform_set_drvdata(pdev, rc);
  213. ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
  214. if (ret) {
  215. dev_err(&pdev->dev, "unable to register device\n");
  216. return ret;
  217. }
  218. if (npcm_usb_reset(pdev, rc))
  219. dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
  220. if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
  221. &rc->sw_reset_number)) {
  222. if (rc->sw_reset_number && rc->sw_reset_number < 5) {
  223. rc->restart_nb.priority = 192,
  224. rc->restart_nb.notifier_call = npcm_rc_restart,
  225. ret = register_restart_handler(&rc->restart_nb);
  226. if (ret)
  227. dev_warn(&pdev->dev, "failed to register restart handler\n");
  228. }
  229. }
  230. return ret;
  231. }
  232. static struct platform_driver npcm_rc_driver = {
  233. .probe = npcm_rc_probe,
  234. .driver = {
  235. .name = "npcm-reset",
  236. .of_match_table = npcm_rc_match,
  237. .suppress_bind_attrs = true,
  238. },
  239. };
  240. builtin_platform_driver(npcm_rc_driver);