reset-lpc18xx.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
  4. *
  5. * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/init.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/reboot.h>
  15. #include <linux/reset-controller.h>
  16. #include <linux/spinlock.h>
  17. /* LPC18xx RGU registers */
  18. #define LPC18XX_RGU_CTRL0 0x100
  19. #define LPC18XX_RGU_CTRL1 0x104
  20. #define LPC18XX_RGU_ACTIVE_STATUS0 0x150
  21. #define LPC18XX_RGU_ACTIVE_STATUS1 0x154
  22. #define LPC18XX_RGU_RESETS_PER_REG 32
  23. /* Internal reset outputs */
  24. #define LPC18XX_RGU_CORE_RST 0
  25. #define LPC43XX_RGU_M0SUB_RST 12
  26. #define LPC43XX_RGU_M0APP_RST 56
  27. struct lpc18xx_rgu_data {
  28. struct reset_controller_dev rcdev;
  29. struct notifier_block restart_nb;
  30. struct clk *clk_delay;
  31. struct clk *clk_reg;
  32. void __iomem *base;
  33. spinlock_t lock;
  34. u32 delay_us;
  35. };
  36. #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
  37. static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
  38. void *cmd)
  39. {
  40. struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
  41. restart_nb);
  42. writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
  43. mdelay(2000);
  44. pr_emerg("%s: unable to restart system\n", __func__);
  45. return NOTIFY_DONE;
  46. }
  47. /*
  48. * The LPC18xx RGU has mostly self-deasserting resets except for the
  49. * two reset lines going to the internal Cortex-M0 cores.
  50. *
  51. * To prevent the M0 core resets from accidentally getting deasserted
  52. * status register must be check and bits in control register set to
  53. * preserve the state.
  54. */
  55. static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
  56. unsigned long id, bool set)
  57. {
  58. struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
  59. u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
  60. u32 ctrl_offset = LPC18XX_RGU_CTRL0;
  61. unsigned long flags;
  62. u32 stat, rst_bit;
  63. stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
  64. ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
  65. rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
  66. spin_lock_irqsave(&rc->lock, flags);
  67. stat = ~readl(rc->base + stat_offset);
  68. if (set)
  69. writel(stat | rst_bit, rc->base + ctrl_offset);
  70. else
  71. writel(stat & ~rst_bit, rc->base + ctrl_offset);
  72. spin_unlock_irqrestore(&rc->lock, flags);
  73. return 0;
  74. }
  75. static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
  76. unsigned long id)
  77. {
  78. return lpc18xx_rgu_setclear_reset(rcdev, id, true);
  79. }
  80. static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
  81. unsigned long id)
  82. {
  83. return lpc18xx_rgu_setclear_reset(rcdev, id, false);
  84. }
  85. /* Only M0 cores require explicit reset deassert */
  86. static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
  87. unsigned long id)
  88. {
  89. struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
  90. lpc18xx_rgu_assert(rcdev, id);
  91. udelay(rc->delay_us);
  92. switch (id) {
  93. case LPC43XX_RGU_M0SUB_RST:
  94. case LPC43XX_RGU_M0APP_RST:
  95. lpc18xx_rgu_setclear_reset(rcdev, id, false);
  96. }
  97. return 0;
  98. }
  99. static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
  100. unsigned long id)
  101. {
  102. struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
  103. u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
  104. offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
  105. bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
  106. return !(readl(rc->base + offset) & bit);
  107. }
  108. static const struct reset_control_ops lpc18xx_rgu_ops = {
  109. .reset = lpc18xx_rgu_reset,
  110. .assert = lpc18xx_rgu_assert,
  111. .deassert = lpc18xx_rgu_deassert,
  112. .status = lpc18xx_rgu_status,
  113. };
  114. static int lpc18xx_rgu_probe(struct platform_device *pdev)
  115. {
  116. struct lpc18xx_rgu_data *rc;
  117. struct resource *res;
  118. u32 fcclk, firc;
  119. int ret;
  120. rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
  121. if (!rc)
  122. return -ENOMEM;
  123. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  124. rc->base = devm_ioremap_resource(&pdev->dev, res);
  125. if (IS_ERR(rc->base))
  126. return PTR_ERR(rc->base);
  127. rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
  128. if (IS_ERR(rc->clk_reg)) {
  129. dev_err(&pdev->dev, "reg clock not found\n");
  130. return PTR_ERR(rc->clk_reg);
  131. }
  132. rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
  133. if (IS_ERR(rc->clk_delay)) {
  134. dev_err(&pdev->dev, "delay clock not found\n");
  135. return PTR_ERR(rc->clk_delay);
  136. }
  137. ret = clk_prepare_enable(rc->clk_reg);
  138. if (ret) {
  139. dev_err(&pdev->dev, "unable to enable reg clock\n");
  140. return ret;
  141. }
  142. ret = clk_prepare_enable(rc->clk_delay);
  143. if (ret) {
  144. dev_err(&pdev->dev, "unable to enable delay clock\n");
  145. goto dis_clk_reg;
  146. }
  147. fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
  148. firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
  149. if (fcclk == 0 || firc == 0)
  150. rc->delay_us = 2;
  151. else
  152. rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
  153. spin_lock_init(&rc->lock);
  154. rc->rcdev.owner = THIS_MODULE;
  155. rc->rcdev.nr_resets = 64;
  156. rc->rcdev.ops = &lpc18xx_rgu_ops;
  157. rc->rcdev.of_node = pdev->dev.of_node;
  158. platform_set_drvdata(pdev, rc);
  159. ret = reset_controller_register(&rc->rcdev);
  160. if (ret) {
  161. dev_err(&pdev->dev, "unable to register device\n");
  162. goto dis_clks;
  163. }
  164. rc->restart_nb.priority = 192,
  165. rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
  166. ret = register_restart_handler(&rc->restart_nb);
  167. if (ret)
  168. dev_warn(&pdev->dev, "failed to register restart handler\n");
  169. return 0;
  170. dis_clks:
  171. clk_disable_unprepare(rc->clk_delay);
  172. dis_clk_reg:
  173. clk_disable_unprepare(rc->clk_reg);
  174. return ret;
  175. }
  176. static const struct of_device_id lpc18xx_rgu_match[] = {
  177. { .compatible = "nxp,lpc1850-rgu" },
  178. { }
  179. };
  180. static struct platform_driver lpc18xx_rgu_driver = {
  181. .probe = lpc18xx_rgu_probe,
  182. .driver = {
  183. .name = "lpc18xx-reset",
  184. .of_match_table = lpc18xx_rgu_match,
  185. .suppress_bind_attrs = true,
  186. },
  187. };
  188. builtin_platform_driver(lpc18xx_rgu_driver);