reset-intel-gw.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 Intel Corporation.
  4. * Lei Chuanhua <Chuanhua.lei@intel.com>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/init.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/reboot.h>
  11. #include <linux/regmap.h>
  12. #include <linux/reset-controller.h>
  13. #define RCU_RST_STAT 0x0024
  14. #define RCU_RST_REQ 0x0048
  15. #define REG_OFFSET_MASK GENMASK(31, 16)
  16. #define BIT_OFFSET_MASK GENMASK(15, 8)
  17. #define STAT_BIT_OFFSET_MASK GENMASK(7, 0)
  18. #define to_reset_data(x) container_of(x, struct intel_reset_data, rcdev)
  19. struct intel_reset_soc {
  20. bool legacy;
  21. u32 reset_cell_count;
  22. };
  23. struct intel_reset_data {
  24. struct reset_controller_dev rcdev;
  25. struct notifier_block restart_nb;
  26. const struct intel_reset_soc *soc_data;
  27. struct regmap *regmap;
  28. struct device *dev;
  29. u32 reboot_id;
  30. };
  31. static const struct regmap_config intel_rcu_regmap_config = {
  32. .name = "intel-reset",
  33. .reg_bits = 32,
  34. .reg_stride = 4,
  35. .val_bits = 32,
  36. .fast_io = true,
  37. };
  38. /*
  39. * Reset status register offset relative to
  40. * the reset control register(X) is X + 4
  41. */
  42. static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data,
  43. unsigned long id, u32 *rst_req,
  44. u32 *req_bit, u32 *stat_bit)
  45. {
  46. *rst_req = FIELD_GET(REG_OFFSET_MASK, id);
  47. *req_bit = FIELD_GET(BIT_OFFSET_MASK, id);
  48. if (data->soc_data->legacy)
  49. *stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id);
  50. else
  51. *stat_bit = *req_bit;
  52. if (data->soc_data->legacy && *rst_req == RCU_RST_REQ)
  53. return RCU_RST_STAT;
  54. else
  55. return *rst_req + 0x4;
  56. }
  57. static int intel_set_clr_bits(struct intel_reset_data *data, unsigned long id,
  58. bool set)
  59. {
  60. u32 rst_req, req_bit, rst_stat, stat_bit, val;
  61. int ret;
  62. rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req,
  63. &req_bit, &stat_bit);
  64. val = set ? BIT(req_bit) : 0;
  65. ret = regmap_update_bits(data->regmap, rst_req, BIT(req_bit), val);
  66. if (ret)
  67. return ret;
  68. return regmap_read_poll_timeout(data->regmap, rst_stat, val,
  69. set == !!(val & BIT(stat_bit)), 20,
  70. 200);
  71. }
  72. static int intel_assert_device(struct reset_controller_dev *rcdev,
  73. unsigned long id)
  74. {
  75. struct intel_reset_data *data = to_reset_data(rcdev);
  76. int ret;
  77. ret = intel_set_clr_bits(data, id, true);
  78. if (ret)
  79. dev_err(data->dev, "Reset assert failed %d\n", ret);
  80. return ret;
  81. }
  82. static int intel_deassert_device(struct reset_controller_dev *rcdev,
  83. unsigned long id)
  84. {
  85. struct intel_reset_data *data = to_reset_data(rcdev);
  86. int ret;
  87. ret = intel_set_clr_bits(data, id, false);
  88. if (ret)
  89. dev_err(data->dev, "Reset deassert failed %d\n", ret);
  90. return ret;
  91. }
  92. static int intel_reset_status(struct reset_controller_dev *rcdev,
  93. unsigned long id)
  94. {
  95. struct intel_reset_data *data = to_reset_data(rcdev);
  96. u32 rst_req, req_bit, rst_stat, stat_bit, val;
  97. int ret;
  98. rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req,
  99. &req_bit, &stat_bit);
  100. ret = regmap_read(data->regmap, rst_stat, &val);
  101. if (ret)
  102. return ret;
  103. return !!(val & BIT(stat_bit));
  104. }
  105. static const struct reset_control_ops intel_reset_ops = {
  106. .assert = intel_assert_device,
  107. .deassert = intel_deassert_device,
  108. .status = intel_reset_status,
  109. };
  110. static int intel_reset_xlate(struct reset_controller_dev *rcdev,
  111. const struct of_phandle_args *spec)
  112. {
  113. struct intel_reset_data *data = to_reset_data(rcdev);
  114. u32 id;
  115. if (spec->args[1] > 31)
  116. return -EINVAL;
  117. id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]);
  118. id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]);
  119. if (data->soc_data->legacy) {
  120. if (spec->args[2] > 31)
  121. return -EINVAL;
  122. id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]);
  123. }
  124. return id;
  125. }
  126. static int intel_reset_restart_handler(struct notifier_block *nb,
  127. unsigned long action, void *data)
  128. {
  129. struct intel_reset_data *reset_data;
  130. reset_data = container_of(nb, struct intel_reset_data, restart_nb);
  131. intel_assert_device(&reset_data->rcdev, reset_data->reboot_id);
  132. return NOTIFY_DONE;
  133. }
  134. static int intel_reset_probe(struct platform_device *pdev)
  135. {
  136. struct device_node *np = pdev->dev.of_node;
  137. struct device *dev = &pdev->dev;
  138. struct intel_reset_data *data;
  139. void __iomem *base;
  140. u32 rb_id[3];
  141. int ret;
  142. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  143. if (!data)
  144. return -ENOMEM;
  145. data->soc_data = of_device_get_match_data(dev);
  146. if (!data->soc_data)
  147. return -ENODEV;
  148. base = devm_platform_ioremap_resource(pdev, 0);
  149. if (IS_ERR(base))
  150. return PTR_ERR(base);
  151. data->regmap = devm_regmap_init_mmio(dev, base,
  152. &intel_rcu_regmap_config);
  153. if (IS_ERR(data->regmap)) {
  154. dev_err(dev, "regmap initialization failed\n");
  155. return PTR_ERR(data->regmap);
  156. }
  157. ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id,
  158. data->soc_data->reset_cell_count);
  159. if (ret) {
  160. dev_err(dev, "Failed to get global reset offset!\n");
  161. return ret;
  162. }
  163. data->dev = dev;
  164. data->rcdev.of_node = np;
  165. data->rcdev.owner = dev->driver->owner;
  166. data->rcdev.ops = &intel_reset_ops;
  167. data->rcdev.of_xlate = intel_reset_xlate;
  168. data->rcdev.of_reset_n_cells = data->soc_data->reset_cell_count;
  169. ret = devm_reset_controller_register(&pdev->dev, &data->rcdev);
  170. if (ret)
  171. return ret;
  172. data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]);
  173. data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]);
  174. if (data->soc_data->legacy)
  175. data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]);
  176. data->restart_nb.notifier_call = intel_reset_restart_handler;
  177. data->restart_nb.priority = 128;
  178. register_restart_handler(&data->restart_nb);
  179. return 0;
  180. }
  181. static const struct intel_reset_soc xrx200_data = {
  182. .legacy = true,
  183. .reset_cell_count = 3,
  184. };
  185. static const struct intel_reset_soc lgm_data = {
  186. .legacy = false,
  187. .reset_cell_count = 2,
  188. };
  189. static const struct of_device_id intel_reset_match[] = {
  190. { .compatible = "intel,rcu-lgm", .data = &lgm_data },
  191. { .compatible = "intel,rcu-xrx200", .data = &xrx200_data },
  192. {}
  193. };
  194. static struct platform_driver intel_reset_driver = {
  195. .probe = intel_reset_probe,
  196. .driver = {
  197. .name = "intel-reset",
  198. .of_match_table = intel_reset_match,
  199. },
  200. };
  201. static int __init intel_reset_init(void)
  202. {
  203. return platform_driver_register(&intel_reset_driver);
  204. }
  205. /*
  206. * RCU is system core entity which is in Always On Domain whose clocks
  207. * or resource initialization happens in system core initialization.
  208. * Also, it is required for most of the platform or architecture
  209. * specific devices to perform reset operation as part of initialization.
  210. * So perform RCU as post core initialization.
  211. */
  212. postcore_initcall(intel_reset_init);