qcom_q6v5_wcss.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Linaro Ltd.
  4. * Copyright (C) 2014 Sony Mobile Communications AB
  5. * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/iopoll.h>
  8. #include <linux/kernel.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/module.h>
  11. #include <linux/of_reserved_mem.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset.h>
  15. #include <linux/soc/qcom/mdt_loader.h>
  16. #include "qcom_common.h"
  17. #include "qcom_pil_info.h"
  18. #include "qcom_q6v5.h"
  19. #define WCSS_CRASH_REASON 421
  20. /* Q6SS Register Offsets */
  21. #define Q6SS_RESET_REG 0x014
  22. #define Q6SS_GFMUX_CTL_REG 0x020
  23. #define Q6SS_PWR_CTL_REG 0x030
  24. #define Q6SS_MEM_PWR_CTL 0x0B0
  25. /* AXI Halt Register Offsets */
  26. #define AXI_HALTREQ_REG 0x0
  27. #define AXI_HALTACK_REG 0x4
  28. #define AXI_IDLE_REG 0x8
  29. #define HALT_ACK_TIMEOUT_MS 100
  30. /* Q6SS_RESET */
  31. #define Q6SS_STOP_CORE BIT(0)
  32. #define Q6SS_CORE_ARES BIT(1)
  33. #define Q6SS_BUS_ARES_ENABLE BIT(2)
  34. /* Q6SS_GFMUX_CTL */
  35. #define Q6SS_CLK_ENABLE BIT(1)
  36. /* Q6SS_PWR_CTL */
  37. #define Q6SS_L2DATA_STBY_N BIT(18)
  38. #define Q6SS_SLP_RET_N BIT(19)
  39. #define Q6SS_CLAMP_IO BIT(20)
  40. #define QDSS_BHS_ON BIT(21)
  41. /* Q6SS parameters */
  42. #define Q6SS_LDO_BYP BIT(25)
  43. #define Q6SS_BHS_ON BIT(24)
  44. #define Q6SS_CLAMP_WL BIT(21)
  45. #define Q6SS_CLAMP_QMC_MEM BIT(22)
  46. #define HALT_CHECK_MAX_LOOPS 200
  47. #define Q6SS_XO_CBCR GENMASK(5, 3)
  48. /* Q6SS config/status registers */
  49. #define TCSR_GLOBAL_CFG0 0x0
  50. #define TCSR_GLOBAL_CFG1 0x4
  51. #define SSCAON_CONFIG 0x8
  52. #define SSCAON_STATUS 0xc
  53. #define Q6SS_BHS_STATUS 0x78
  54. #define Q6SS_RST_EVB 0x10
  55. #define BHS_EN_REST_ACK BIT(0)
  56. #define SSCAON_ENABLE BIT(13)
  57. #define SSCAON_BUS_EN BIT(15)
  58. #define SSCAON_BUS_MUX_MASK GENMASK(18, 16)
  59. #define MEM_BANKS 19
  60. #define TCSR_WCSS_CLK_MASK 0x1F
  61. #define TCSR_WCSS_CLK_ENABLE 0x14
  62. struct q6v5_wcss {
  63. struct device *dev;
  64. void __iomem *reg_base;
  65. void __iomem *rmb_base;
  66. struct regmap *halt_map;
  67. u32 halt_q6;
  68. u32 halt_wcss;
  69. u32 halt_nc;
  70. struct reset_control *wcss_aon_reset;
  71. struct reset_control *wcss_reset;
  72. struct reset_control *wcss_q6_reset;
  73. struct qcom_q6v5 q6v5;
  74. phys_addr_t mem_phys;
  75. phys_addr_t mem_reloc;
  76. void *mem_region;
  77. size_t mem_size;
  78. struct qcom_rproc_glink glink_subdev;
  79. struct qcom_rproc_ssr ssr_subdev;
  80. };
  81. static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
  82. {
  83. int ret;
  84. u32 val;
  85. int i;
  86. /* Assert resets, stop core */
  87. val = readl(wcss->reg_base + Q6SS_RESET_REG);
  88. val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
  89. writel(val, wcss->reg_base + Q6SS_RESET_REG);
  90. /* BHS require xo cbcr to be enabled */
  91. val = readl(wcss->reg_base + Q6SS_XO_CBCR);
  92. val |= 0x1;
  93. writel(val, wcss->reg_base + Q6SS_XO_CBCR);
  94. /* Read CLKOFF bit to go low indicating CLK is enabled */
  95. ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
  96. val, !(val & BIT(31)), 1,
  97. HALT_CHECK_MAX_LOOPS);
  98. if (ret) {
  99. dev_err(wcss->dev,
  100. "xo cbcr enabling timed out (rc:%d)\n", ret);
  101. return ret;
  102. }
  103. /* Enable power block headswitch and wait for it to stabilize */
  104. val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
  105. val |= Q6SS_BHS_ON;
  106. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  107. udelay(1);
  108. /* Put LDO in bypass mode */
  109. val |= Q6SS_LDO_BYP;
  110. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  111. /* Deassert Q6 compiler memory clamp */
  112. val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
  113. val &= ~Q6SS_CLAMP_QMC_MEM;
  114. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  115. /* Deassert memory peripheral sleep and L2 memory standby */
  116. val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
  117. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  118. /* Turn on L1, L2, ETB and JU memories 1 at a time */
  119. val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
  120. for (i = MEM_BANKS; i >= 0; i--) {
  121. val |= BIT(i);
  122. writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
  123. /*
  124. * Read back value to ensure the write is done then
  125. * wait for 1us for both memory peripheral and data
  126. * array to turn on.
  127. */
  128. val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
  129. udelay(1);
  130. }
  131. /* Remove word line clamp */
  132. val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
  133. val &= ~Q6SS_CLAMP_WL;
  134. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  135. /* Remove IO clamp */
  136. val &= ~Q6SS_CLAMP_IO;
  137. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  138. /* Bring core out of reset */
  139. val = readl(wcss->reg_base + Q6SS_RESET_REG);
  140. val &= ~Q6SS_CORE_ARES;
  141. writel(val, wcss->reg_base + Q6SS_RESET_REG);
  142. /* Turn on core clock */
  143. val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
  144. val |= Q6SS_CLK_ENABLE;
  145. writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
  146. /* Start core execution */
  147. val = readl(wcss->reg_base + Q6SS_RESET_REG);
  148. val &= ~Q6SS_STOP_CORE;
  149. writel(val, wcss->reg_base + Q6SS_RESET_REG);
  150. return 0;
  151. }
  152. static int q6v5_wcss_start(struct rproc *rproc)
  153. {
  154. struct q6v5_wcss *wcss = rproc->priv;
  155. int ret;
  156. qcom_q6v5_prepare(&wcss->q6v5);
  157. /* Release Q6 and WCSS reset */
  158. ret = reset_control_deassert(wcss->wcss_reset);
  159. if (ret) {
  160. dev_err(wcss->dev, "wcss_reset failed\n");
  161. return ret;
  162. }
  163. ret = reset_control_deassert(wcss->wcss_q6_reset);
  164. if (ret) {
  165. dev_err(wcss->dev, "wcss_q6_reset failed\n");
  166. goto wcss_reset;
  167. }
  168. /* Lithium configuration - clock gating and bus arbitration */
  169. ret = regmap_update_bits(wcss->halt_map,
  170. wcss->halt_nc + TCSR_GLOBAL_CFG0,
  171. TCSR_WCSS_CLK_MASK,
  172. TCSR_WCSS_CLK_ENABLE);
  173. if (ret)
  174. goto wcss_q6_reset;
  175. ret = regmap_update_bits(wcss->halt_map,
  176. wcss->halt_nc + TCSR_GLOBAL_CFG1,
  177. 1, 0);
  178. if (ret)
  179. goto wcss_q6_reset;
  180. /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
  181. writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
  182. ret = q6v5_wcss_reset(wcss);
  183. if (ret)
  184. goto wcss_q6_reset;
  185. ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
  186. if (ret == -ETIMEDOUT)
  187. dev_err(wcss->dev, "start timed out\n");
  188. return ret;
  189. wcss_q6_reset:
  190. reset_control_assert(wcss->wcss_q6_reset);
  191. wcss_reset:
  192. reset_control_assert(wcss->wcss_reset);
  193. return ret;
  194. }
  195. static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
  196. struct regmap *halt_map,
  197. u32 offset)
  198. {
  199. unsigned long timeout;
  200. unsigned int val;
  201. int ret;
  202. /* Check if we're already idle */
  203. ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
  204. if (!ret && val)
  205. return;
  206. /* Assert halt request */
  207. regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
  208. /* Wait for halt */
  209. timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
  210. for (;;) {
  211. ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
  212. if (ret || val || time_after(jiffies, timeout))
  213. break;
  214. msleep(1);
  215. }
  216. ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
  217. if (ret || !val)
  218. dev_err(wcss->dev, "port failed halt\n");
  219. /* Clear halt request (port will remain halted until reset) */
  220. regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
  221. }
  222. static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
  223. {
  224. int ret;
  225. u32 val;
  226. /* 1 - Assert WCSS/Q6 HALTREQ */
  227. q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
  228. /* 2 - Enable WCSSAON_CONFIG */
  229. val = readl(wcss->rmb_base + SSCAON_CONFIG);
  230. val |= SSCAON_ENABLE;
  231. writel(val, wcss->rmb_base + SSCAON_CONFIG);
  232. /* 3 - Set SSCAON_CONFIG */
  233. val |= SSCAON_BUS_EN;
  234. val &= ~SSCAON_BUS_MUX_MASK;
  235. writel(val, wcss->rmb_base + SSCAON_CONFIG);
  236. /* 4 - SSCAON_CONFIG 1 */
  237. val |= BIT(1);
  238. writel(val, wcss->rmb_base + SSCAON_CONFIG);
  239. /* 5 - wait for SSCAON_STATUS */
  240. ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS,
  241. val, (val & 0xffff) == 0x400, 1000,
  242. HALT_CHECK_MAX_LOOPS);
  243. if (ret) {
  244. dev_err(wcss->dev,
  245. "can't get SSCAON_STATUS rc:%d)\n", ret);
  246. return ret;
  247. }
  248. /* 6 - De-assert WCSS_AON reset */
  249. reset_control_assert(wcss->wcss_aon_reset);
  250. /* 7 - Disable WCSSAON_CONFIG 13 */
  251. val = readl(wcss->rmb_base + SSCAON_CONFIG);
  252. val &= ~SSCAON_ENABLE;
  253. writel(val, wcss->rmb_base + SSCAON_CONFIG);
  254. /* 8 - De-assert WCSS/Q6 HALTREQ */
  255. reset_control_assert(wcss->wcss_reset);
  256. return 0;
  257. }
  258. static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
  259. {
  260. int ret;
  261. u32 val;
  262. int i;
  263. /* 1 - Halt Q6 bus interface */
  264. q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);
  265. /* 2 - Disable Q6 Core clock */
  266. val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
  267. val &= ~Q6SS_CLK_ENABLE;
  268. writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
  269. /* 3 - Clamp I/O */
  270. val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
  271. val |= Q6SS_CLAMP_IO;
  272. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  273. /* 4 - Clamp WL */
  274. val |= QDSS_BHS_ON;
  275. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  276. /* 5 - Clear Erase standby */
  277. val &= ~Q6SS_L2DATA_STBY_N;
  278. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  279. /* 6 - Clear Sleep RTN */
  280. val &= ~Q6SS_SLP_RET_N;
  281. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  282. /* 7 - turn off Q6 memory foot/head switch one bank at a time */
  283. for (i = 0; i < 20; i++) {
  284. val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
  285. val &= ~BIT(i);
  286. writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
  287. mdelay(1);
  288. }
  289. /* 8 - Assert QMC memory RTN */
  290. val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
  291. val |= Q6SS_CLAMP_QMC_MEM;
  292. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  293. /* 9 - Turn off BHS */
  294. val &= ~Q6SS_BHS_ON;
  295. writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
  296. udelay(1);
  297. /* 10 - Wait till BHS Reset is done */
  298. ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
  299. val, !(val & BHS_EN_REST_ACK), 1000,
  300. HALT_CHECK_MAX_LOOPS);
  301. if (ret) {
  302. dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret);
  303. return ret;
  304. }
  305. /* 11 - Assert WCSS reset */
  306. reset_control_assert(wcss->wcss_reset);
  307. /* 12 - Assert Q6 reset */
  308. reset_control_assert(wcss->wcss_q6_reset);
  309. return 0;
  310. }
  311. static int q6v5_wcss_stop(struct rproc *rproc)
  312. {
  313. struct q6v5_wcss *wcss = rproc->priv;
  314. int ret;
  315. /* WCSS powerdown */
  316. ret = qcom_q6v5_request_stop(&wcss->q6v5);
  317. if (ret == -ETIMEDOUT) {
  318. dev_err(wcss->dev, "timed out on wait\n");
  319. return ret;
  320. }
  321. ret = q6v5_wcss_powerdown(wcss);
  322. if (ret)
  323. return ret;
  324. /* Q6 Power down */
  325. ret = q6v5_q6_powerdown(wcss);
  326. if (ret)
  327. return ret;
  328. qcom_q6v5_unprepare(&wcss->q6v5);
  329. return 0;
  330. }
  331. static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  332. {
  333. struct q6v5_wcss *wcss = rproc->priv;
  334. int offset;
  335. offset = da - wcss->mem_reloc;
  336. if (offset < 0 || offset + len > wcss->mem_size)
  337. return NULL;
  338. return wcss->mem_region + offset;
  339. }
  340. static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
  341. {
  342. struct q6v5_wcss *wcss = rproc->priv;
  343. int ret;
  344. ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
  345. 0, wcss->mem_region, wcss->mem_phys,
  346. wcss->mem_size, &wcss->mem_reloc);
  347. if (ret)
  348. return ret;
  349. qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size);
  350. return ret;
  351. }
  352. static const struct rproc_ops q6v5_wcss_ops = {
  353. .start = q6v5_wcss_start,
  354. .stop = q6v5_wcss_stop,
  355. .da_to_va = q6v5_wcss_da_to_va,
  356. .load = q6v5_wcss_load,
  357. .get_boot_addr = rproc_elf_get_boot_addr,
  358. };
  359. static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
  360. {
  361. struct device *dev = wcss->dev;
  362. wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
  363. if (IS_ERR(wcss->wcss_aon_reset)) {
  364. dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
  365. return PTR_ERR(wcss->wcss_aon_reset);
  366. }
  367. wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
  368. if (IS_ERR(wcss->wcss_reset)) {
  369. dev_err(wcss->dev, "unable to acquire wcss_reset\n");
  370. return PTR_ERR(wcss->wcss_reset);
  371. }
  372. wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
  373. if (IS_ERR(wcss->wcss_q6_reset)) {
  374. dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
  375. return PTR_ERR(wcss->wcss_q6_reset);
  376. }
  377. return 0;
  378. }
  379. static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
  380. struct platform_device *pdev)
  381. {
  382. struct of_phandle_args args;
  383. struct resource *res;
  384. int ret;
  385. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
  386. wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
  387. if (IS_ERR(wcss->reg_base))
  388. return PTR_ERR(wcss->reg_base);
  389. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
  390. wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
  391. if (IS_ERR(wcss->rmb_base))
  392. return PTR_ERR(wcss->rmb_base);
  393. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  394. "qcom,halt-regs", 3, 0, &args);
  395. if (ret < 0) {
  396. dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
  397. return -EINVAL;
  398. }
  399. wcss->halt_map = syscon_node_to_regmap(args.np);
  400. of_node_put(args.np);
  401. if (IS_ERR(wcss->halt_map))
  402. return PTR_ERR(wcss->halt_map);
  403. wcss->halt_q6 = args.args[0];
  404. wcss->halt_wcss = args.args[1];
  405. wcss->halt_nc = args.args[2];
  406. return 0;
  407. }
  408. static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
  409. {
  410. struct reserved_mem *rmem = NULL;
  411. struct device_node *node;
  412. struct device *dev = wcss->dev;
  413. node = of_parse_phandle(dev->of_node, "memory-region", 0);
  414. if (node)
  415. rmem = of_reserved_mem_lookup(node);
  416. of_node_put(node);
  417. if (!rmem) {
  418. dev_err(dev, "unable to acquire memory-region\n");
  419. return -EINVAL;
  420. }
  421. wcss->mem_phys = rmem->base;
  422. wcss->mem_reloc = rmem->base;
  423. wcss->mem_size = rmem->size;
  424. wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size);
  425. if (!wcss->mem_region) {
  426. dev_err(dev, "unable to map memory region: %pa+%pa\n",
  427. &rmem->base, &rmem->size);
  428. return -EBUSY;
  429. }
  430. return 0;
  431. }
  432. static int q6v5_wcss_probe(struct platform_device *pdev)
  433. {
  434. struct q6v5_wcss *wcss;
  435. struct rproc *rproc;
  436. int ret;
  437. rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
  438. "IPQ8074/q6_fw.mdt", sizeof(*wcss));
  439. if (!rproc) {
  440. dev_err(&pdev->dev, "failed to allocate rproc\n");
  441. return -ENOMEM;
  442. }
  443. wcss = rproc->priv;
  444. wcss->dev = &pdev->dev;
  445. ret = q6v5_wcss_init_mmio(wcss, pdev);
  446. if (ret)
  447. goto free_rproc;
  448. ret = q6v5_alloc_memory_region(wcss);
  449. if (ret)
  450. goto free_rproc;
  451. ret = q6v5_wcss_init_reset(wcss);
  452. if (ret)
  453. goto free_rproc;
  454. ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
  455. if (ret)
  456. goto free_rproc;
  457. qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
  458. qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
  459. ret = rproc_add(rproc);
  460. if (ret)
  461. goto free_rproc;
  462. platform_set_drvdata(pdev, rproc);
  463. return 0;
  464. free_rproc:
  465. rproc_free(rproc);
  466. return ret;
  467. }
  468. static int q6v5_wcss_remove(struct platform_device *pdev)
  469. {
  470. struct rproc *rproc = platform_get_drvdata(pdev);
  471. rproc_del(rproc);
  472. rproc_free(rproc);
  473. return 0;
  474. }
  475. static const struct of_device_id q6v5_wcss_of_match[] = {
  476. { .compatible = "qcom,ipq8074-wcss-pil" },
  477. { },
  478. };
  479. MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
  480. static struct platform_driver q6v5_wcss_driver = {
  481. .probe = q6v5_wcss_probe,
  482. .remove = q6v5_wcss_remove,
  483. .driver = {
  484. .name = "qcom-q6v5-wcss-pil",
  485. .of_match_table = q6v5_wcss_of_match,
  486. },
  487. };
  488. module_platform_driver(q6v5_wcss_driver);
  489. MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");
  490. MODULE_LICENSE("GPL v2");