qcom_q6v5_pas.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
  4. *
  5. * Copyright (C) 2016 Linaro Ltd
  6. * Copyright (C) 2014 Sony Mobile Communications AB
  7. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/firmware.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_domain.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/qcom_scm.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/remoteproc.h>
  22. #include <linux/soc/qcom/mdt_loader.h>
  23. #include <linux/soc/qcom/smem.h>
  24. #include <linux/soc/qcom/smem_state.h>
  25. #include "qcom_common.h"
  26. #include "qcom_pil_info.h"
  27. #include "qcom_q6v5.h"
  28. #include "remoteproc_internal.h"
  29. struct adsp_data {
  30. int crash_reason_smem;
  31. const char *firmware_name;
  32. int pas_id;
  33. bool has_aggre2_clk;
  34. bool auto_boot;
  35. char **active_pd_names;
  36. char **proxy_pd_names;
  37. const char *ssr_name;
  38. const char *sysmon_name;
  39. int ssctl_id;
  40. };
  41. struct qcom_adsp {
  42. struct device *dev;
  43. struct rproc *rproc;
  44. struct qcom_q6v5 q6v5;
  45. struct clk *xo;
  46. struct clk *aggre2_clk;
  47. struct regulator *cx_supply;
  48. struct regulator *px_supply;
  49. struct device *active_pds[1];
  50. struct device *proxy_pds[3];
  51. int active_pd_count;
  52. int proxy_pd_count;
  53. int pas_id;
  54. int crash_reason_smem;
  55. bool has_aggre2_clk;
  56. const char *info_name;
  57. struct completion start_done;
  58. struct completion stop_done;
  59. phys_addr_t mem_phys;
  60. phys_addr_t mem_reloc;
  61. void *mem_region;
  62. size_t mem_size;
  63. struct qcom_rproc_glink glink_subdev;
  64. struct qcom_rproc_subdev smd_subdev;
  65. struct qcom_rproc_ssr ssr_subdev;
  66. struct qcom_sysmon *sysmon;
  67. };
  68. static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds,
  69. size_t pd_count)
  70. {
  71. int ret;
  72. int i;
  73. for (i = 0; i < pd_count; i++) {
  74. dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
  75. ret = pm_runtime_get_sync(pds[i]);
  76. if (ret < 0) {
  77. pm_runtime_put_noidle(pds[i]);
  78. dev_pm_genpd_set_performance_state(pds[i], 0);
  79. goto unroll_pd_votes;
  80. }
  81. }
  82. return 0;
  83. unroll_pd_votes:
  84. for (i--; i >= 0; i--) {
  85. dev_pm_genpd_set_performance_state(pds[i], 0);
  86. pm_runtime_put(pds[i]);
  87. }
  88. return ret;
  89. };
  90. static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds,
  91. size_t pd_count)
  92. {
  93. int i;
  94. for (i = 0; i < pd_count; i++) {
  95. dev_pm_genpd_set_performance_state(pds[i], 0);
  96. pm_runtime_put(pds[i]);
  97. }
  98. }
  99. static int adsp_load(struct rproc *rproc, const struct firmware *fw)
  100. {
  101. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  102. int ret;
  103. ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
  104. adsp->mem_region, adsp->mem_phys, adsp->mem_size,
  105. &adsp->mem_reloc);
  106. if (ret)
  107. return ret;
  108. qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
  109. return 0;
  110. }
  111. static int adsp_start(struct rproc *rproc)
  112. {
  113. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  114. int ret;
  115. qcom_q6v5_prepare(&adsp->q6v5);
  116. ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
  117. if (ret < 0)
  118. goto disable_irqs;
  119. ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
  120. if (ret < 0)
  121. goto disable_active_pds;
  122. ret = clk_prepare_enable(adsp->xo);
  123. if (ret)
  124. goto disable_proxy_pds;
  125. ret = clk_prepare_enable(adsp->aggre2_clk);
  126. if (ret)
  127. goto disable_xo_clk;
  128. ret = regulator_enable(adsp->cx_supply);
  129. if (ret)
  130. goto disable_aggre2_clk;
  131. ret = regulator_enable(adsp->px_supply);
  132. if (ret)
  133. goto disable_cx_supply;
  134. ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
  135. if (ret) {
  136. dev_err(adsp->dev,
  137. "failed to authenticate image and release reset\n");
  138. goto disable_px_supply;
  139. }
  140. ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
  141. if (ret == -ETIMEDOUT) {
  142. dev_err(adsp->dev, "start timed out\n");
  143. qcom_scm_pas_shutdown(adsp->pas_id);
  144. goto disable_px_supply;
  145. }
  146. return 0;
  147. disable_px_supply:
  148. regulator_disable(adsp->px_supply);
  149. disable_cx_supply:
  150. regulator_disable(adsp->cx_supply);
  151. disable_aggre2_clk:
  152. clk_disable_unprepare(adsp->aggre2_clk);
  153. disable_xo_clk:
  154. clk_disable_unprepare(adsp->xo);
  155. disable_proxy_pds:
  156. adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
  157. disable_active_pds:
  158. adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
  159. disable_irqs:
  160. qcom_q6v5_unprepare(&adsp->q6v5);
  161. return ret;
  162. }
  163. static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
  164. {
  165. struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
  166. regulator_disable(adsp->px_supply);
  167. regulator_disable(adsp->cx_supply);
  168. clk_disable_unprepare(adsp->aggre2_clk);
  169. clk_disable_unprepare(adsp->xo);
  170. adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
  171. }
  172. static int adsp_stop(struct rproc *rproc)
  173. {
  174. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  175. int handover;
  176. int ret;
  177. ret = qcom_q6v5_request_stop(&adsp->q6v5);
  178. if (ret == -ETIMEDOUT)
  179. dev_err(adsp->dev, "timed out on wait\n");
  180. ret = qcom_scm_pas_shutdown(adsp->pas_id);
  181. if (ret)
  182. dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
  183. adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
  184. handover = qcom_q6v5_unprepare(&adsp->q6v5);
  185. if (handover)
  186. qcom_pas_handover(&adsp->q6v5);
  187. return ret;
  188. }
  189. static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  190. {
  191. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  192. int offset;
  193. offset = da - adsp->mem_reloc;
  194. if (offset < 0 || offset + len > adsp->mem_size)
  195. return NULL;
  196. return adsp->mem_region + offset;
  197. }
  198. static unsigned long adsp_panic(struct rproc *rproc)
  199. {
  200. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  201. return qcom_q6v5_panic(&adsp->q6v5);
  202. }
  203. static const struct rproc_ops adsp_ops = {
  204. .start = adsp_start,
  205. .stop = adsp_stop,
  206. .da_to_va = adsp_da_to_va,
  207. .parse_fw = qcom_register_dump_segments,
  208. .load = adsp_load,
  209. .panic = adsp_panic,
  210. };
  211. static int adsp_init_clock(struct qcom_adsp *adsp)
  212. {
  213. int ret;
  214. adsp->xo = devm_clk_get(adsp->dev, "xo");
  215. if (IS_ERR(adsp->xo)) {
  216. ret = PTR_ERR(adsp->xo);
  217. if (ret != -EPROBE_DEFER)
  218. dev_err(adsp->dev, "failed to get xo clock");
  219. return ret;
  220. }
  221. if (adsp->has_aggre2_clk) {
  222. adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
  223. if (IS_ERR(adsp->aggre2_clk)) {
  224. ret = PTR_ERR(adsp->aggre2_clk);
  225. if (ret != -EPROBE_DEFER)
  226. dev_err(adsp->dev,
  227. "failed to get aggre2 clock");
  228. return ret;
  229. }
  230. }
  231. return 0;
  232. }
  233. static int adsp_init_regulator(struct qcom_adsp *adsp)
  234. {
  235. adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
  236. if (IS_ERR(adsp->cx_supply))
  237. return PTR_ERR(adsp->cx_supply);
  238. regulator_set_load(adsp->cx_supply, 100000);
  239. adsp->px_supply = devm_regulator_get(adsp->dev, "px");
  240. return PTR_ERR_OR_ZERO(adsp->px_supply);
  241. }
  242. static int adsp_pds_attach(struct device *dev, struct device **devs,
  243. char **pd_names)
  244. {
  245. size_t num_pds = 0;
  246. int ret;
  247. int i;
  248. if (!pd_names)
  249. return 0;
  250. /* Handle single power domain */
  251. if (dev->pm_domain) {
  252. devs[0] = dev;
  253. pm_runtime_enable(dev);
  254. return 1;
  255. }
  256. while (pd_names[num_pds])
  257. num_pds++;
  258. for (i = 0; i < num_pds; i++) {
  259. devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
  260. if (IS_ERR_OR_NULL(devs[i])) {
  261. ret = PTR_ERR(devs[i]) ? : -ENODATA;
  262. goto unroll_attach;
  263. }
  264. }
  265. return num_pds;
  266. unroll_attach:
  267. for (i--; i >= 0; i--)
  268. dev_pm_domain_detach(devs[i], false);
  269. return ret;
  270. };
  271. static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds,
  272. size_t pd_count)
  273. {
  274. struct device *dev = adsp->dev;
  275. int i;
  276. /* Handle single power domain */
  277. if (dev->pm_domain && pd_count) {
  278. pm_runtime_disable(dev);
  279. return;
  280. }
  281. for (i = 0; i < pd_count; i++)
  282. dev_pm_domain_detach(pds[i], false);
  283. }
  284. static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
  285. {
  286. struct device_node *node;
  287. struct resource r;
  288. int ret;
  289. node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
  290. if (!node) {
  291. dev_err(adsp->dev, "no memory-region specified\n");
  292. return -EINVAL;
  293. }
  294. ret = of_address_to_resource(node, 0, &r);
  295. if (ret)
  296. return ret;
  297. adsp->mem_phys = adsp->mem_reloc = r.start;
  298. adsp->mem_size = resource_size(&r);
  299. adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
  300. if (!adsp->mem_region) {
  301. dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
  302. &r.start, adsp->mem_size);
  303. return -EBUSY;
  304. }
  305. return 0;
  306. }
  307. static int adsp_probe(struct platform_device *pdev)
  308. {
  309. const struct adsp_data *desc;
  310. struct qcom_adsp *adsp;
  311. struct rproc *rproc;
  312. const char *fw_name;
  313. int ret;
  314. desc = of_device_get_match_data(&pdev->dev);
  315. if (!desc)
  316. return -EINVAL;
  317. if (!qcom_scm_is_available())
  318. return -EPROBE_DEFER;
  319. fw_name = desc->firmware_name;
  320. ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
  321. &fw_name);
  322. if (ret < 0 && ret != -EINVAL)
  323. return ret;
  324. rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
  325. fw_name, sizeof(*adsp));
  326. if (!rproc) {
  327. dev_err(&pdev->dev, "unable to allocate remoteproc\n");
  328. return -ENOMEM;
  329. }
  330. rproc->auto_boot = desc->auto_boot;
  331. rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
  332. adsp = (struct qcom_adsp *)rproc->priv;
  333. adsp->dev = &pdev->dev;
  334. adsp->rproc = rproc;
  335. adsp->pas_id = desc->pas_id;
  336. adsp->has_aggre2_clk = desc->has_aggre2_clk;
  337. adsp->info_name = desc->sysmon_name;
  338. platform_set_drvdata(pdev, adsp);
  339. device_wakeup_enable(adsp->dev);
  340. ret = adsp_alloc_memory_region(adsp);
  341. if (ret)
  342. goto free_rproc;
  343. ret = adsp_init_clock(adsp);
  344. if (ret)
  345. goto free_rproc;
  346. ret = adsp_init_regulator(adsp);
  347. if (ret)
  348. goto free_rproc;
  349. ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
  350. desc->active_pd_names);
  351. if (ret < 0)
  352. goto free_rproc;
  353. adsp->active_pd_count = ret;
  354. ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
  355. desc->proxy_pd_names);
  356. if (ret < 0)
  357. goto detach_active_pds;
  358. adsp->proxy_pd_count = ret;
  359. ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
  360. qcom_pas_handover);
  361. if (ret)
  362. goto detach_proxy_pds;
  363. qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
  364. qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
  365. qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
  366. adsp->sysmon = qcom_add_sysmon_subdev(rproc,
  367. desc->sysmon_name,
  368. desc->ssctl_id);
  369. if (IS_ERR(adsp->sysmon)) {
  370. ret = PTR_ERR(adsp->sysmon);
  371. goto detach_proxy_pds;
  372. }
  373. ret = rproc_add(rproc);
  374. if (ret)
  375. goto detach_proxy_pds;
  376. return 0;
  377. detach_proxy_pds:
  378. adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
  379. detach_active_pds:
  380. adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
  381. free_rproc:
  382. rproc_free(rproc);
  383. return ret;
  384. }
  385. static int adsp_remove(struct platform_device *pdev)
  386. {
  387. struct qcom_adsp *adsp = platform_get_drvdata(pdev);
  388. rproc_del(adsp->rproc);
  389. qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
  390. qcom_remove_sysmon_subdev(adsp->sysmon);
  391. qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
  392. qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
  393. rproc_free(adsp->rproc);
  394. return 0;
  395. }
  396. static const struct adsp_data adsp_resource_init = {
  397. .crash_reason_smem = 423,
  398. .firmware_name = "adsp.mdt",
  399. .pas_id = 1,
  400. .has_aggre2_clk = false,
  401. .auto_boot = true,
  402. .ssr_name = "lpass",
  403. .sysmon_name = "adsp",
  404. .ssctl_id = 0x14,
  405. };
  406. static const struct adsp_data sm8150_adsp_resource = {
  407. .crash_reason_smem = 423,
  408. .firmware_name = "adsp.mdt",
  409. .pas_id = 1,
  410. .has_aggre2_clk = false,
  411. .auto_boot = true,
  412. .active_pd_names = (char*[]){
  413. "load_state",
  414. NULL
  415. },
  416. .proxy_pd_names = (char*[]){
  417. "cx",
  418. NULL
  419. },
  420. .ssr_name = "lpass",
  421. .sysmon_name = "adsp",
  422. .ssctl_id = 0x14,
  423. };
  424. static const struct adsp_data sm8250_adsp_resource = {
  425. .crash_reason_smem = 423,
  426. .firmware_name = "adsp.mdt",
  427. .pas_id = 1,
  428. .has_aggre2_clk = false,
  429. .auto_boot = true,
  430. .active_pd_names = (char*[]){
  431. "load_state",
  432. NULL
  433. },
  434. .proxy_pd_names = (char*[]){
  435. "lcx",
  436. "lmx",
  437. NULL
  438. },
  439. .ssr_name = "lpass",
  440. .sysmon_name = "adsp",
  441. .ssctl_id = 0x14,
  442. };
  443. static const struct adsp_data msm8998_adsp_resource = {
  444. .crash_reason_smem = 423,
  445. .firmware_name = "adsp.mdt",
  446. .pas_id = 1,
  447. .has_aggre2_clk = false,
  448. .auto_boot = true,
  449. .proxy_pd_names = (char*[]){
  450. "cx",
  451. NULL
  452. },
  453. .ssr_name = "lpass",
  454. .sysmon_name = "adsp",
  455. .ssctl_id = 0x14,
  456. };
  457. static const struct adsp_data cdsp_resource_init = {
  458. .crash_reason_smem = 601,
  459. .firmware_name = "cdsp.mdt",
  460. .pas_id = 18,
  461. .has_aggre2_clk = false,
  462. .auto_boot = true,
  463. .ssr_name = "cdsp",
  464. .sysmon_name = "cdsp",
  465. .ssctl_id = 0x17,
  466. };
  467. static const struct adsp_data sm8150_cdsp_resource = {
  468. .crash_reason_smem = 601,
  469. .firmware_name = "cdsp.mdt",
  470. .pas_id = 18,
  471. .has_aggre2_clk = false,
  472. .auto_boot = true,
  473. .active_pd_names = (char*[]){
  474. "load_state",
  475. NULL
  476. },
  477. .proxy_pd_names = (char*[]){
  478. "cx",
  479. NULL
  480. },
  481. .ssr_name = "cdsp",
  482. .sysmon_name = "cdsp",
  483. .ssctl_id = 0x17,
  484. };
  485. static const struct adsp_data sm8250_cdsp_resource = {
  486. .crash_reason_smem = 601,
  487. .firmware_name = "cdsp.mdt",
  488. .pas_id = 18,
  489. .has_aggre2_clk = false,
  490. .auto_boot = true,
  491. .active_pd_names = (char*[]){
  492. "load_state",
  493. NULL
  494. },
  495. .proxy_pd_names = (char*[]){
  496. "cx",
  497. NULL
  498. },
  499. .ssr_name = "cdsp",
  500. .sysmon_name = "cdsp",
  501. .ssctl_id = 0x17,
  502. };
  503. static const struct adsp_data mpss_resource_init = {
  504. .crash_reason_smem = 421,
  505. .firmware_name = "modem.mdt",
  506. .pas_id = 4,
  507. .has_aggre2_clk = false,
  508. .auto_boot = false,
  509. .active_pd_names = (char*[]){
  510. "load_state",
  511. NULL
  512. },
  513. .proxy_pd_names = (char*[]){
  514. "cx",
  515. "mss",
  516. NULL
  517. },
  518. .ssr_name = "mpss",
  519. .sysmon_name = "modem",
  520. .ssctl_id = 0x12,
  521. };
  522. static const struct adsp_data slpi_resource_init = {
  523. .crash_reason_smem = 424,
  524. .firmware_name = "slpi.mdt",
  525. .pas_id = 12,
  526. .has_aggre2_clk = true,
  527. .auto_boot = true,
  528. .ssr_name = "dsps",
  529. .sysmon_name = "slpi",
  530. .ssctl_id = 0x16,
  531. };
  532. static const struct adsp_data sm8150_slpi_resource = {
  533. .crash_reason_smem = 424,
  534. .firmware_name = "slpi.mdt",
  535. .pas_id = 12,
  536. .has_aggre2_clk = false,
  537. .auto_boot = true,
  538. .active_pd_names = (char*[]){
  539. "load_state",
  540. NULL
  541. },
  542. .proxy_pd_names = (char*[]){
  543. "lcx",
  544. "lmx",
  545. NULL
  546. },
  547. .ssr_name = "dsps",
  548. .sysmon_name = "slpi",
  549. .ssctl_id = 0x16,
  550. };
  551. static const struct adsp_data sm8250_slpi_resource = {
  552. .crash_reason_smem = 424,
  553. .firmware_name = "slpi.mdt",
  554. .pas_id = 12,
  555. .has_aggre2_clk = false,
  556. .auto_boot = true,
  557. .active_pd_names = (char*[]){
  558. "load_state",
  559. NULL
  560. },
  561. .proxy_pd_names = (char*[]){
  562. "lcx",
  563. "lmx",
  564. NULL
  565. },
  566. .ssr_name = "dsps",
  567. .sysmon_name = "slpi",
  568. .ssctl_id = 0x16,
  569. };
  570. static const struct adsp_data msm8998_slpi_resource = {
  571. .crash_reason_smem = 424,
  572. .firmware_name = "slpi.mdt",
  573. .pas_id = 12,
  574. .has_aggre2_clk = true,
  575. .auto_boot = true,
  576. .proxy_pd_names = (char*[]){
  577. "ssc_cx",
  578. NULL
  579. },
  580. .ssr_name = "dsps",
  581. .sysmon_name = "slpi",
  582. .ssctl_id = 0x16,
  583. };
  584. static const struct adsp_data wcss_resource_init = {
  585. .crash_reason_smem = 421,
  586. .firmware_name = "wcnss.mdt",
  587. .pas_id = 6,
  588. .auto_boot = true,
  589. .ssr_name = "mpss",
  590. .sysmon_name = "wcnss",
  591. .ssctl_id = 0x12,
  592. };
  593. static const struct of_device_id adsp_of_match[] = {
  594. { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
  595. { .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
  596. { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
  597. { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
  598. { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
  599. { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
  600. { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
  601. { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
  602. { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
  603. { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
  604. { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
  605. { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
  606. { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
  607. { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
  608. { .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource},
  609. { .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource},
  610. { .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource},
  611. { .compatible = "qcom,sm8250-slpi-pas", .data = &sm8250_slpi_resource},
  612. { },
  613. };
  614. MODULE_DEVICE_TABLE(of, adsp_of_match);
  615. static struct platform_driver adsp_driver = {
  616. .probe = adsp_probe,
  617. .remove = adsp_remove,
  618. .driver = {
  619. .name = "qcom_q6v5_pas",
  620. .of_match_table = adsp_of_match,
  621. },
  622. };
  623. module_platform_driver(adsp_driver);
  624. MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
  625. MODULE_LICENSE("GPL v2");