qcom_q6v5_mss.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Qualcomm self-authenticating modem subsystem remoteproc driver
  4. *
  5. * Copyright (C) 2016 Linaro Ltd.
  6. * Copyright (C) 2014 Sony Mobile Communications AB
  7. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/devcoredump.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_domain.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/remoteproc.h>
  25. #include <linux/reset.h>
  26. #include <linux/soc/qcom/mdt_loader.h>
  27. #include <linux/iopoll.h>
  28. #include <linux/slab.h>
  29. #include "remoteproc_internal.h"
  30. #include "qcom_common.h"
  31. #include "qcom_pil_info.h"
  32. #include "qcom_q6v5.h"
  33. #include <linux/qcom_scm.h>
  34. #define MPSS_CRASH_REASON_SMEM 421
  35. #define MBA_LOG_SIZE SZ_4K
  36. /* RMB Status Register Values */
  37. #define RMB_PBL_SUCCESS 0x1
  38. #define RMB_MBA_XPU_UNLOCKED 0x1
  39. #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
  40. #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
  41. #define RMB_MBA_AUTH_COMPLETE 0x4
  42. /* PBL/MBA interface registers */
  43. #define RMB_MBA_IMAGE_REG 0x00
  44. #define RMB_PBL_STATUS_REG 0x04
  45. #define RMB_MBA_COMMAND_REG 0x08
  46. #define RMB_MBA_STATUS_REG 0x0C
  47. #define RMB_PMI_META_DATA_REG 0x10
  48. #define RMB_PMI_CODE_START_REG 0x14
  49. #define RMB_PMI_CODE_LENGTH_REG 0x18
  50. #define RMB_MBA_MSS_STATUS 0x40
  51. #define RMB_MBA_ALT_RESET 0x44
  52. #define RMB_CMD_META_DATA_READY 0x1
  53. #define RMB_CMD_LOAD_READY 0x2
  54. /* QDSP6SS Register Offsets */
  55. #define QDSP6SS_RESET_REG 0x014
  56. #define QDSP6SS_GFMUX_CTL_REG 0x020
  57. #define QDSP6SS_PWR_CTL_REG 0x030
  58. #define QDSP6SS_MEM_PWR_CTL 0x0B0
  59. #define QDSP6V6SS_MEM_PWR_CTL 0x034
  60. #define QDSP6SS_STRAP_ACC 0x110
  61. /* AXI Halt Register Offsets */
  62. #define AXI_HALTREQ_REG 0x0
  63. #define AXI_HALTACK_REG 0x4
  64. #define AXI_IDLE_REG 0x8
  65. #define AXI_GATING_VALID_OVERRIDE BIT(0)
  66. #define HALT_ACK_TIMEOUT_US 100000
  67. /* QDSP6SS_RESET */
  68. #define Q6SS_STOP_CORE BIT(0)
  69. #define Q6SS_CORE_ARES BIT(1)
  70. #define Q6SS_BUS_ARES_ENABLE BIT(2)
  71. /* QDSP6SS CBCR */
  72. #define Q6SS_CBCR_CLKEN BIT(0)
  73. #define Q6SS_CBCR_CLKOFF BIT(31)
  74. #define Q6SS_CBCR_TIMEOUT_US 200
  75. /* QDSP6SS_GFMUX_CTL */
  76. #define Q6SS_CLK_ENABLE BIT(1)
  77. /* QDSP6SS_PWR_CTL */
  78. #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
  79. #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
  80. #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
  81. #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
  82. #define Q6SS_ETB_SLP_NRET_N BIT(17)
  83. #define Q6SS_L2DATA_STBY_N BIT(18)
  84. #define Q6SS_SLP_RET_N BIT(19)
  85. #define Q6SS_CLAMP_IO BIT(20)
  86. #define QDSS_BHS_ON BIT(21)
  87. #define QDSS_LDO_BYP BIT(22)
  88. /* QDSP6v56 parameters */
  89. #define QDSP6v56_LDO_BYP BIT(25)
  90. #define QDSP6v56_BHS_ON BIT(24)
  91. #define QDSP6v56_CLAMP_WL BIT(21)
  92. #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
  93. #define QDSP6SS_XO_CBCR 0x0038
  94. #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
  95. /* QDSP6v65 parameters */
  96. #define QDSP6SS_CORE_CBCR 0x20
  97. #define QDSP6SS_SLEEP 0x3C
  98. #define QDSP6SS_BOOT_CORE_START 0x400
  99. #define QDSP6SS_BOOT_CMD 0x404
  100. #define BOOT_FSM_TIMEOUT 10000
  101. struct reg_info {
  102. struct regulator *reg;
  103. int uV;
  104. int uA;
  105. };
  106. struct qcom_mss_reg_res {
  107. const char *supply;
  108. int uV;
  109. int uA;
  110. };
  111. struct rproc_hexagon_res {
  112. const char *hexagon_mba_image;
  113. struct qcom_mss_reg_res *proxy_supply;
  114. struct qcom_mss_reg_res *active_supply;
  115. char **proxy_clk_names;
  116. char **reset_clk_names;
  117. char **active_clk_names;
  118. char **active_pd_names;
  119. char **proxy_pd_names;
  120. int version;
  121. bool need_mem_protection;
  122. bool has_alt_reset;
  123. bool has_mba_logs;
  124. bool has_spare_reg;
  125. };
  126. struct q6v5 {
  127. struct device *dev;
  128. struct rproc *rproc;
  129. void __iomem *reg_base;
  130. void __iomem *rmb_base;
  131. struct regmap *halt_map;
  132. struct regmap *conn_map;
  133. u32 halt_q6;
  134. u32 halt_modem;
  135. u32 halt_nc;
  136. u32 conn_box;
  137. struct reset_control *mss_restart;
  138. struct reset_control *pdc_reset;
  139. struct qcom_q6v5 q6v5;
  140. struct clk *active_clks[8];
  141. struct clk *reset_clks[4];
  142. struct clk *proxy_clks[4];
  143. struct device *active_pds[1];
  144. struct device *proxy_pds[3];
  145. int active_clk_count;
  146. int reset_clk_count;
  147. int proxy_clk_count;
  148. int active_pd_count;
  149. int proxy_pd_count;
  150. struct reg_info active_regs[1];
  151. struct reg_info proxy_regs[3];
  152. int active_reg_count;
  153. int proxy_reg_count;
  154. bool dump_mba_loaded;
  155. size_t current_dump_size;
  156. size_t total_dump_size;
  157. phys_addr_t mba_phys;
  158. void *mba_region;
  159. size_t mba_size;
  160. size_t dp_size;
  161. phys_addr_t mpss_phys;
  162. phys_addr_t mpss_reloc;
  163. size_t mpss_size;
  164. struct qcom_rproc_glink glink_subdev;
  165. struct qcom_rproc_subdev smd_subdev;
  166. struct qcom_rproc_ssr ssr_subdev;
  167. struct qcom_sysmon *sysmon;
  168. bool need_mem_protection;
  169. bool has_alt_reset;
  170. bool has_mba_logs;
  171. bool has_spare_reg;
  172. int mpss_perm;
  173. int mba_perm;
  174. const char *hexagon_mdt_image;
  175. int version;
  176. };
  177. enum {
  178. MSS_MSM8916,
  179. MSS_MSM8974,
  180. MSS_MSM8996,
  181. MSS_MSM8998,
  182. MSS_SC7180,
  183. MSS_SDM845,
  184. };
  185. static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
  186. const struct qcom_mss_reg_res *reg_res)
  187. {
  188. int rc;
  189. int i;
  190. if (!reg_res)
  191. return 0;
  192. for (i = 0; reg_res[i].supply; i++) {
  193. regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
  194. if (IS_ERR(regs[i].reg)) {
  195. rc = PTR_ERR(regs[i].reg);
  196. if (rc != -EPROBE_DEFER)
  197. dev_err(dev, "Failed to get %s\n regulator",
  198. reg_res[i].supply);
  199. return rc;
  200. }
  201. regs[i].uV = reg_res[i].uV;
  202. regs[i].uA = reg_res[i].uA;
  203. }
  204. return i;
  205. }
  206. static int q6v5_regulator_enable(struct q6v5 *qproc,
  207. struct reg_info *regs, int count)
  208. {
  209. int ret;
  210. int i;
  211. for (i = 0; i < count; i++) {
  212. if (regs[i].uV > 0) {
  213. ret = regulator_set_voltage(regs[i].reg,
  214. regs[i].uV, INT_MAX);
  215. if (ret) {
  216. dev_err(qproc->dev,
  217. "Failed to request voltage for %d.\n",
  218. i);
  219. goto err;
  220. }
  221. }
  222. if (regs[i].uA > 0) {
  223. ret = regulator_set_load(regs[i].reg,
  224. regs[i].uA);
  225. if (ret < 0) {
  226. dev_err(qproc->dev,
  227. "Failed to set regulator mode\n");
  228. goto err;
  229. }
  230. }
  231. ret = regulator_enable(regs[i].reg);
  232. if (ret) {
  233. dev_err(qproc->dev, "Regulator enable failed\n");
  234. goto err;
  235. }
  236. }
  237. return 0;
  238. err:
  239. for (; i >= 0; i--) {
  240. if (regs[i].uV > 0)
  241. regulator_set_voltage(regs[i].reg, 0, INT_MAX);
  242. if (regs[i].uA > 0)
  243. regulator_set_load(regs[i].reg, 0);
  244. regulator_disable(regs[i].reg);
  245. }
  246. return ret;
  247. }
  248. static void q6v5_regulator_disable(struct q6v5 *qproc,
  249. struct reg_info *regs, int count)
  250. {
  251. int i;
  252. for (i = 0; i < count; i++) {
  253. if (regs[i].uV > 0)
  254. regulator_set_voltage(regs[i].reg, 0, INT_MAX);
  255. if (regs[i].uA > 0)
  256. regulator_set_load(regs[i].reg, 0);
  257. regulator_disable(regs[i].reg);
  258. }
  259. }
  260. static int q6v5_clk_enable(struct device *dev,
  261. struct clk **clks, int count)
  262. {
  263. int rc;
  264. int i;
  265. for (i = 0; i < count; i++) {
  266. rc = clk_prepare_enable(clks[i]);
  267. if (rc) {
  268. dev_err(dev, "Clock enable failed\n");
  269. goto err;
  270. }
  271. }
  272. return 0;
  273. err:
  274. for (i--; i >= 0; i--)
  275. clk_disable_unprepare(clks[i]);
  276. return rc;
  277. }
  278. static void q6v5_clk_disable(struct device *dev,
  279. struct clk **clks, int count)
  280. {
  281. int i;
  282. for (i = 0; i < count; i++)
  283. clk_disable_unprepare(clks[i]);
  284. }
  285. static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
  286. size_t pd_count)
  287. {
  288. int ret;
  289. int i;
  290. for (i = 0; i < pd_count; i++) {
  291. dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
  292. ret = pm_runtime_get_sync(pds[i]);
  293. if (ret < 0) {
  294. pm_runtime_put_noidle(pds[i]);
  295. dev_pm_genpd_set_performance_state(pds[i], 0);
  296. goto unroll_pd_votes;
  297. }
  298. }
  299. return 0;
  300. unroll_pd_votes:
  301. for (i--; i >= 0; i--) {
  302. dev_pm_genpd_set_performance_state(pds[i], 0);
  303. pm_runtime_put(pds[i]);
  304. }
  305. return ret;
  306. }
  307. static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
  308. size_t pd_count)
  309. {
  310. int i;
  311. for (i = 0; i < pd_count; i++) {
  312. dev_pm_genpd_set_performance_state(pds[i], 0);
  313. pm_runtime_put(pds[i]);
  314. }
  315. }
  316. static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
  317. bool local, bool remote, phys_addr_t addr,
  318. size_t size)
  319. {
  320. struct qcom_scm_vmperm next[2];
  321. int perms = 0;
  322. if (!qproc->need_mem_protection)
  323. return 0;
  324. if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
  325. remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
  326. return 0;
  327. if (local) {
  328. next[perms].vmid = QCOM_SCM_VMID_HLOS;
  329. next[perms].perm = QCOM_SCM_PERM_RWX;
  330. perms++;
  331. }
  332. if (remote) {
  333. next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
  334. next[perms].perm = QCOM_SCM_PERM_RW;
  335. perms++;
  336. }
  337. return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
  338. current_perm, next, perms);
  339. }
  340. static void q6v5_debug_policy_load(struct q6v5 *qproc)
  341. {
  342. const struct firmware *dp_fw;
  343. if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
  344. return;
  345. if (SZ_1M + dp_fw->size <= qproc->mba_size) {
  346. memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size);
  347. qproc->dp_size = dp_fw->size;
  348. }
  349. release_firmware(dp_fw);
  350. }
  351. static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
  352. {
  353. struct q6v5 *qproc = rproc->priv;
  354. /* MBA is restricted to a maximum size of 1M */
  355. if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
  356. dev_err(qproc->dev, "MBA firmware load failed\n");
  357. return -EINVAL;
  358. }
  359. memcpy(qproc->mba_region, fw->data, fw->size);
  360. q6v5_debug_policy_load(qproc);
  361. return 0;
  362. }
  363. static int q6v5_reset_assert(struct q6v5 *qproc)
  364. {
  365. int ret;
  366. if (qproc->has_alt_reset) {
  367. reset_control_assert(qproc->pdc_reset);
  368. ret = reset_control_reset(qproc->mss_restart);
  369. reset_control_deassert(qproc->pdc_reset);
  370. } else if (qproc->has_spare_reg) {
  371. /*
  372. * When the AXI pipeline is being reset with the Q6 modem partly
  373. * operational there is possibility of AXI valid signal to
  374. * glitch, leading to spurious transactions and Q6 hangs. A work
  375. * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
  376. * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
  377. * is withdrawn post MSS assert followed by a MSS deassert,
  378. * while holding the PDC reset.
  379. */
  380. reset_control_assert(qproc->pdc_reset);
  381. regmap_update_bits(qproc->conn_map, qproc->conn_box,
  382. AXI_GATING_VALID_OVERRIDE, 1);
  383. reset_control_assert(qproc->mss_restart);
  384. reset_control_deassert(qproc->pdc_reset);
  385. regmap_update_bits(qproc->conn_map, qproc->conn_box,
  386. AXI_GATING_VALID_OVERRIDE, 0);
  387. ret = reset_control_deassert(qproc->mss_restart);
  388. } else {
  389. ret = reset_control_assert(qproc->mss_restart);
  390. }
  391. return ret;
  392. }
  393. static int q6v5_reset_deassert(struct q6v5 *qproc)
  394. {
  395. int ret;
  396. if (qproc->has_alt_reset) {
  397. reset_control_assert(qproc->pdc_reset);
  398. writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
  399. ret = reset_control_reset(qproc->mss_restart);
  400. writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
  401. reset_control_deassert(qproc->pdc_reset);
  402. } else if (qproc->has_spare_reg) {
  403. ret = reset_control_reset(qproc->mss_restart);
  404. } else {
  405. ret = reset_control_deassert(qproc->mss_restart);
  406. }
  407. return ret;
  408. }
  409. static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
  410. {
  411. unsigned long timeout;
  412. s32 val;
  413. timeout = jiffies + msecs_to_jiffies(ms);
  414. for (;;) {
  415. val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
  416. if (val)
  417. break;
  418. if (time_after(jiffies, timeout))
  419. return -ETIMEDOUT;
  420. msleep(1);
  421. }
  422. return val;
  423. }
  424. static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
  425. {
  426. unsigned long timeout;
  427. s32 val;
  428. timeout = jiffies + msecs_to_jiffies(ms);
  429. for (;;) {
  430. val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
  431. if (val < 0)
  432. break;
  433. if (!status && val)
  434. break;
  435. else if (status && val == status)
  436. break;
  437. if (time_after(jiffies, timeout))
  438. return -ETIMEDOUT;
  439. msleep(1);
  440. }
  441. return val;
  442. }
  443. static void q6v5_dump_mba_logs(struct q6v5 *qproc)
  444. {
  445. struct rproc *rproc = qproc->rproc;
  446. void *data;
  447. if (!qproc->has_mba_logs)
  448. return;
  449. if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
  450. qproc->mba_size))
  451. return;
  452. data = vmalloc(MBA_LOG_SIZE);
  453. if (!data)
  454. return;
  455. memcpy(data, qproc->mba_region, MBA_LOG_SIZE);
  456. dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
  457. }
  458. static int q6v5proc_reset(struct q6v5 *qproc)
  459. {
  460. u32 val;
  461. int ret;
  462. int i;
  463. if (qproc->version == MSS_SDM845) {
  464. val = readl(qproc->reg_base + QDSP6SS_SLEEP);
  465. val |= Q6SS_CBCR_CLKEN;
  466. writel(val, qproc->reg_base + QDSP6SS_SLEEP);
  467. ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
  468. val, !(val & Q6SS_CBCR_CLKOFF), 1,
  469. Q6SS_CBCR_TIMEOUT_US);
  470. if (ret) {
  471. dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
  472. return -ETIMEDOUT;
  473. }
  474. /* De-assert QDSP6 stop core */
  475. writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
  476. /* Trigger boot FSM */
  477. writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
  478. ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
  479. val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
  480. if (ret) {
  481. dev_err(qproc->dev, "Boot FSM failed to complete.\n");
  482. /* Reset the modem so that boot FSM is in reset state */
  483. q6v5_reset_deassert(qproc);
  484. return ret;
  485. }
  486. goto pbl_wait;
  487. } else if (qproc->version == MSS_SC7180) {
  488. val = readl(qproc->reg_base + QDSP6SS_SLEEP);
  489. val |= Q6SS_CBCR_CLKEN;
  490. writel(val, qproc->reg_base + QDSP6SS_SLEEP);
  491. ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
  492. val, !(val & Q6SS_CBCR_CLKOFF), 1,
  493. Q6SS_CBCR_TIMEOUT_US);
  494. if (ret) {
  495. dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
  496. return -ETIMEDOUT;
  497. }
  498. /* Turn on the XO clock needed for PLL setup */
  499. val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
  500. val |= Q6SS_CBCR_CLKEN;
  501. writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
  502. ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
  503. val, !(val & Q6SS_CBCR_CLKOFF), 1,
  504. Q6SS_CBCR_TIMEOUT_US);
  505. if (ret) {
  506. dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
  507. return -ETIMEDOUT;
  508. }
  509. /* Configure Q6 core CBCR to auto-enable after reset sequence */
  510. val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
  511. val |= Q6SS_CBCR_CLKEN;
  512. writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
  513. /* De-assert the Q6 stop core signal */
  514. writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
  515. /* Wait for 10 us for any staggering logic to settle */
  516. usleep_range(10, 20);
  517. /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
  518. writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
  519. /* Poll the MSS_STATUS for FSM completion */
  520. ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
  521. val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
  522. if (ret) {
  523. dev_err(qproc->dev, "Boot FSM failed to complete.\n");
  524. /* Reset the modem so that boot FSM is in reset state */
  525. q6v5_reset_deassert(qproc);
  526. return ret;
  527. }
  528. goto pbl_wait;
  529. } else if (qproc->version == MSS_MSM8996 ||
  530. qproc->version == MSS_MSM8998) {
  531. int mem_pwr_ctl;
  532. /* Override the ACC value if required */
  533. writel(QDSP6SS_ACC_OVERRIDE_VAL,
  534. qproc->reg_base + QDSP6SS_STRAP_ACC);
  535. /* Assert resets, stop core */
  536. val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
  537. val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
  538. writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
  539. /* BHS require xo cbcr to be enabled */
  540. val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
  541. val |= Q6SS_CBCR_CLKEN;
  542. writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
  543. /* Read CLKOFF bit to go low indicating CLK is enabled */
  544. ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
  545. val, !(val & Q6SS_CBCR_CLKOFF), 1,
  546. Q6SS_CBCR_TIMEOUT_US);
  547. if (ret) {
  548. dev_err(qproc->dev,
  549. "xo cbcr enabling timed out (rc:%d)\n", ret);
  550. return ret;
  551. }
  552. /* Enable power block headswitch and wait for it to stabilize */
  553. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  554. val |= QDSP6v56_BHS_ON;
  555. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  556. val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  557. udelay(1);
  558. /* Put LDO in bypass mode */
  559. val |= QDSP6v56_LDO_BYP;
  560. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  561. /* Deassert QDSP6 compiler memory clamp */
  562. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  563. val &= ~QDSP6v56_CLAMP_QMC_MEM;
  564. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  565. /* Deassert memory peripheral sleep and L2 memory standby */
  566. val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
  567. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  568. /* Turn on L1, L2, ETB and JU memories 1 at a time */
  569. if (qproc->version == MSS_MSM8996) {
  570. mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
  571. i = 19;
  572. } else {
  573. /* MSS_MSM8998 */
  574. mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
  575. i = 28;
  576. }
  577. val = readl(qproc->reg_base + mem_pwr_ctl);
  578. for (; i >= 0; i--) {
  579. val |= BIT(i);
  580. writel(val, qproc->reg_base + mem_pwr_ctl);
  581. /*
  582. * Read back value to ensure the write is done then
  583. * wait for 1us for both memory peripheral and data
  584. * array to turn on.
  585. */
  586. val |= readl(qproc->reg_base + mem_pwr_ctl);
  587. udelay(1);
  588. }
  589. /* Remove word line clamp */
  590. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  591. val &= ~QDSP6v56_CLAMP_WL;
  592. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  593. } else {
  594. /* Assert resets, stop core */
  595. val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
  596. val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
  597. writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
  598. /* Enable power block headswitch and wait for it to stabilize */
  599. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  600. val |= QDSS_BHS_ON | QDSS_LDO_BYP;
  601. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  602. val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  603. udelay(1);
  604. /*
  605. * Turn on memories. L2 banks should be done individually
  606. * to minimize inrush current.
  607. */
  608. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  609. val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
  610. Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
  611. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  612. val |= Q6SS_L2DATA_SLP_NRET_N_2;
  613. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  614. val |= Q6SS_L2DATA_SLP_NRET_N_1;
  615. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  616. val |= Q6SS_L2DATA_SLP_NRET_N_0;
  617. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  618. }
  619. /* Remove IO clamp */
  620. val &= ~Q6SS_CLAMP_IO;
  621. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  622. /* Bring core out of reset */
  623. val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
  624. val &= ~Q6SS_CORE_ARES;
  625. writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
  626. /* Turn on core clock */
  627. val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
  628. val |= Q6SS_CLK_ENABLE;
  629. writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
  630. /* Start core execution */
  631. val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
  632. val &= ~Q6SS_STOP_CORE;
  633. writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
  634. pbl_wait:
  635. /* Wait for PBL status */
  636. ret = q6v5_rmb_pbl_wait(qproc, 1000);
  637. if (ret == -ETIMEDOUT) {
  638. dev_err(qproc->dev, "PBL boot timed out\n");
  639. } else if (ret != RMB_PBL_SUCCESS) {
  640. dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
  641. ret = -EINVAL;
  642. } else {
  643. ret = 0;
  644. }
  645. return ret;
  646. }
  647. static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
  648. struct regmap *halt_map,
  649. u32 offset)
  650. {
  651. unsigned int val;
  652. int ret;
  653. /* Check if we're already idle */
  654. ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
  655. if (!ret && val)
  656. return;
  657. /* Assert halt request */
  658. regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
  659. /* Wait for halt */
  660. regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
  661. val, 1000, HALT_ACK_TIMEOUT_US);
  662. ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
  663. if (ret || !val)
  664. dev_err(qproc->dev, "port failed halt\n");
  665. /* Clear halt request (port will remain halted until reset) */
  666. regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
  667. }
  668. static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
  669. {
  670. unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
  671. dma_addr_t phys;
  672. void *metadata;
  673. int mdata_perm;
  674. int xferop_ret;
  675. size_t size;
  676. void *ptr;
  677. int ret;
  678. metadata = qcom_mdt_read_metadata(fw, &size);
  679. if (IS_ERR(metadata))
  680. return PTR_ERR(metadata);
  681. ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
  682. if (!ptr) {
  683. kfree(metadata);
  684. dev_err(qproc->dev, "failed to allocate mdt buffer\n");
  685. return -ENOMEM;
  686. }
  687. memcpy(ptr, metadata, size);
  688. /* Hypervisor mapping to access metadata by modem */
  689. mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
  690. ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
  691. phys, size);
  692. if (ret) {
  693. dev_err(qproc->dev,
  694. "assigning Q6 access to metadata failed: %d\n", ret);
  695. ret = -EAGAIN;
  696. goto free_dma_attrs;
  697. }
  698. writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
  699. writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
  700. ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
  701. if (ret == -ETIMEDOUT)
  702. dev_err(qproc->dev, "MPSS header authentication timed out\n");
  703. else if (ret < 0)
  704. dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
  705. /* Metadata authentication done, remove modem access */
  706. xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
  707. phys, size);
  708. if (xferop_ret)
  709. dev_warn(qproc->dev,
  710. "mdt buffer not reclaimed system may become unstable\n");
  711. free_dma_attrs:
  712. dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
  713. kfree(metadata);
  714. return ret < 0 ? ret : 0;
  715. }
  716. static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
  717. {
  718. if (phdr->p_type != PT_LOAD)
  719. return false;
  720. if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
  721. return false;
  722. if (!phdr->p_memsz)
  723. return false;
  724. return true;
  725. }
  726. static int q6v5_mba_load(struct q6v5 *qproc)
  727. {
  728. int ret;
  729. int xfermemop_ret;
  730. bool mba_load_err = false;
  731. qcom_q6v5_prepare(&qproc->q6v5);
  732. ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
  733. if (ret < 0) {
  734. dev_err(qproc->dev, "failed to enable active power domains\n");
  735. goto disable_irqs;
  736. }
  737. ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
  738. if (ret < 0) {
  739. dev_err(qproc->dev, "failed to enable proxy power domains\n");
  740. goto disable_active_pds;
  741. }
  742. ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
  743. qproc->proxy_reg_count);
  744. if (ret) {
  745. dev_err(qproc->dev, "failed to enable proxy supplies\n");
  746. goto disable_proxy_pds;
  747. }
  748. ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
  749. qproc->proxy_clk_count);
  750. if (ret) {
  751. dev_err(qproc->dev, "failed to enable proxy clocks\n");
  752. goto disable_proxy_reg;
  753. }
  754. ret = q6v5_regulator_enable(qproc, qproc->active_regs,
  755. qproc->active_reg_count);
  756. if (ret) {
  757. dev_err(qproc->dev, "failed to enable supplies\n");
  758. goto disable_proxy_clk;
  759. }
  760. ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
  761. qproc->reset_clk_count);
  762. if (ret) {
  763. dev_err(qproc->dev, "failed to enable reset clocks\n");
  764. goto disable_vdd;
  765. }
  766. ret = q6v5_reset_deassert(qproc);
  767. if (ret) {
  768. dev_err(qproc->dev, "failed to deassert mss restart\n");
  769. goto disable_reset_clks;
  770. }
  771. ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
  772. qproc->active_clk_count);
  773. if (ret) {
  774. dev_err(qproc->dev, "failed to enable clocks\n");
  775. goto assert_reset;
  776. }
  777. /*
  778. * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
  779. * the Q6 access to this region.
  780. */
  781. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
  782. qproc->mpss_phys, qproc->mpss_size);
  783. if (ret) {
  784. dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
  785. goto disable_active_clks;
  786. }
  787. /* Assign MBA image access in DDR to q6 */
  788. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
  789. qproc->mba_phys, qproc->mba_size);
  790. if (ret) {
  791. dev_err(qproc->dev,
  792. "assigning Q6 access to mba memory failed: %d\n", ret);
  793. goto disable_active_clks;
  794. }
  795. writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
  796. if (qproc->dp_size) {
  797. writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
  798. writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
  799. }
  800. ret = q6v5proc_reset(qproc);
  801. if (ret)
  802. goto reclaim_mba;
  803. ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
  804. if (ret == -ETIMEDOUT) {
  805. dev_err(qproc->dev, "MBA boot timed out\n");
  806. goto halt_axi_ports;
  807. } else if (ret != RMB_MBA_XPU_UNLOCKED &&
  808. ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
  809. dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
  810. ret = -EINVAL;
  811. goto halt_axi_ports;
  812. }
  813. qproc->dump_mba_loaded = true;
  814. return 0;
  815. halt_axi_ports:
  816. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
  817. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
  818. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
  819. mba_load_err = true;
  820. reclaim_mba:
  821. xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
  822. false, qproc->mba_phys,
  823. qproc->mba_size);
  824. if (xfermemop_ret) {
  825. dev_err(qproc->dev,
  826. "Failed to reclaim mba buffer, system may become unstable\n");
  827. } else if (mba_load_err) {
  828. q6v5_dump_mba_logs(qproc);
  829. }
  830. disable_active_clks:
  831. q6v5_clk_disable(qproc->dev, qproc->active_clks,
  832. qproc->active_clk_count);
  833. assert_reset:
  834. q6v5_reset_assert(qproc);
  835. disable_reset_clks:
  836. q6v5_clk_disable(qproc->dev, qproc->reset_clks,
  837. qproc->reset_clk_count);
  838. disable_vdd:
  839. q6v5_regulator_disable(qproc, qproc->active_regs,
  840. qproc->active_reg_count);
  841. disable_proxy_clk:
  842. q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
  843. qproc->proxy_clk_count);
  844. disable_proxy_reg:
  845. q6v5_regulator_disable(qproc, qproc->proxy_regs,
  846. qproc->proxy_reg_count);
  847. disable_proxy_pds:
  848. q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
  849. disable_active_pds:
  850. q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
  851. disable_irqs:
  852. qcom_q6v5_unprepare(&qproc->q6v5);
  853. return ret;
  854. }
  855. static void q6v5_mba_reclaim(struct q6v5 *qproc)
  856. {
  857. int ret;
  858. u32 val;
  859. qproc->dump_mba_loaded = false;
  860. qproc->dp_size = 0;
  861. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
  862. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
  863. q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
  864. if (qproc->version == MSS_MSM8996) {
  865. /*
  866. * To avoid high MX current during LPASS/MSS restart.
  867. */
  868. val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  869. val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
  870. QDSP6v56_CLAMP_QMC_MEM;
  871. writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
  872. }
  873. q6v5_reset_assert(qproc);
  874. q6v5_clk_disable(qproc->dev, qproc->reset_clks,
  875. qproc->reset_clk_count);
  876. q6v5_clk_disable(qproc->dev, qproc->active_clks,
  877. qproc->active_clk_count);
  878. q6v5_regulator_disable(qproc, qproc->active_regs,
  879. qproc->active_reg_count);
  880. q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
  881. /* In case of failure or coredump scenario where reclaiming MBA memory
  882. * could not happen reclaim it here.
  883. */
  884. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
  885. qproc->mba_phys,
  886. qproc->mba_size);
  887. WARN_ON(ret);
  888. ret = qcom_q6v5_unprepare(&qproc->q6v5);
  889. if (ret) {
  890. q6v5_pds_disable(qproc, qproc->proxy_pds,
  891. qproc->proxy_pd_count);
  892. q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
  893. qproc->proxy_clk_count);
  894. q6v5_regulator_disable(qproc, qproc->proxy_regs,
  895. qproc->proxy_reg_count);
  896. }
  897. }
  898. static int q6v5_reload_mba(struct rproc *rproc)
  899. {
  900. struct q6v5 *qproc = rproc->priv;
  901. const struct firmware *fw;
  902. int ret;
  903. ret = request_firmware(&fw, rproc->firmware, qproc->dev);
  904. if (ret < 0)
  905. return ret;
  906. q6v5_load(rproc, fw);
  907. ret = q6v5_mba_load(qproc);
  908. release_firmware(fw);
  909. return ret;
  910. }
  911. static int q6v5_mpss_load(struct q6v5 *qproc)
  912. {
  913. const struct elf32_phdr *phdrs;
  914. const struct elf32_phdr *phdr;
  915. const struct firmware *seg_fw;
  916. const struct firmware *fw;
  917. struct elf32_hdr *ehdr;
  918. phys_addr_t mpss_reloc;
  919. phys_addr_t boot_addr;
  920. phys_addr_t min_addr = PHYS_ADDR_MAX;
  921. phys_addr_t max_addr = 0;
  922. u32 code_length;
  923. bool relocate = false;
  924. char *fw_name;
  925. size_t fw_name_len;
  926. ssize_t offset;
  927. size_t size = 0;
  928. void *ptr;
  929. int ret;
  930. int i;
  931. fw_name_len = strlen(qproc->hexagon_mdt_image);
  932. if (fw_name_len <= 4)
  933. return -EINVAL;
  934. fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
  935. if (!fw_name)
  936. return -ENOMEM;
  937. ret = request_firmware(&fw, fw_name, qproc->dev);
  938. if (ret < 0) {
  939. dev_err(qproc->dev, "unable to load %s\n", fw_name);
  940. goto out;
  941. }
  942. /* Initialize the RMB validator */
  943. writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
  944. ret = q6v5_mpss_init_image(qproc, fw);
  945. if (ret)
  946. goto release_firmware;
  947. ehdr = (struct elf32_hdr *)fw->data;
  948. phdrs = (struct elf32_phdr *)(ehdr + 1);
  949. for (i = 0; i < ehdr->e_phnum; i++) {
  950. phdr = &phdrs[i];
  951. if (!q6v5_phdr_valid(phdr))
  952. continue;
  953. if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
  954. relocate = true;
  955. if (phdr->p_paddr < min_addr)
  956. min_addr = phdr->p_paddr;
  957. if (phdr->p_paddr + phdr->p_memsz > max_addr)
  958. max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
  959. }
  960. /*
  961. * In case of a modem subsystem restart on secure devices, the modem
  962. * memory can be reclaimed only after MBA is loaded.
  963. */
  964. q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
  965. qproc->mpss_phys, qproc->mpss_size);
  966. /* Share ownership between Linux and MSS, during segment loading */
  967. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
  968. qproc->mpss_phys, qproc->mpss_size);
  969. if (ret) {
  970. dev_err(qproc->dev,
  971. "assigning Q6 access to mpss memory failed: %d\n", ret);
  972. ret = -EAGAIN;
  973. goto release_firmware;
  974. }
  975. mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
  976. qproc->mpss_reloc = mpss_reloc;
  977. /* Load firmware segments */
  978. for (i = 0; i < ehdr->e_phnum; i++) {
  979. phdr = &phdrs[i];
  980. if (!q6v5_phdr_valid(phdr))
  981. continue;
  982. offset = phdr->p_paddr - mpss_reloc;
  983. if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
  984. dev_err(qproc->dev, "segment outside memory range\n");
  985. ret = -EINVAL;
  986. goto release_firmware;
  987. }
  988. if (phdr->p_filesz > phdr->p_memsz) {
  989. dev_err(qproc->dev,
  990. "refusing to load segment %d with p_filesz > p_memsz\n",
  991. i);
  992. ret = -EINVAL;
  993. goto release_firmware;
  994. }
  995. ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
  996. if (!ptr) {
  997. dev_err(qproc->dev,
  998. "unable to map memory region: %pa+%zx-%x\n",
  999. &qproc->mpss_phys, offset, phdr->p_memsz);
  1000. goto release_firmware;
  1001. }
  1002. if (phdr->p_filesz && phdr->p_offset < fw->size) {
  1003. /* Firmware is large enough to be non-split */
  1004. if (phdr->p_offset + phdr->p_filesz > fw->size) {
  1005. dev_err(qproc->dev,
  1006. "failed to load segment %d from truncated file %s\n",
  1007. i, fw_name);
  1008. ret = -EINVAL;
  1009. memunmap(ptr);
  1010. goto release_firmware;
  1011. }
  1012. memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
  1013. } else if (phdr->p_filesz) {
  1014. /* Replace "xxx.xxx" with "xxx.bxx" */
  1015. sprintf(fw_name + fw_name_len - 3, "b%02d", i);
  1016. ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
  1017. ptr, phdr->p_filesz);
  1018. if (ret) {
  1019. dev_err(qproc->dev, "failed to load %s\n", fw_name);
  1020. memunmap(ptr);
  1021. goto release_firmware;
  1022. }
  1023. if (seg_fw->size != phdr->p_filesz) {
  1024. dev_err(qproc->dev,
  1025. "failed to load segment %d from truncated file %s\n",
  1026. i, fw_name);
  1027. ret = -EINVAL;
  1028. release_firmware(seg_fw);
  1029. memunmap(ptr);
  1030. goto release_firmware;
  1031. }
  1032. release_firmware(seg_fw);
  1033. }
  1034. if (phdr->p_memsz > phdr->p_filesz) {
  1035. memset(ptr + phdr->p_filesz, 0,
  1036. phdr->p_memsz - phdr->p_filesz);
  1037. }
  1038. memunmap(ptr);
  1039. size += phdr->p_memsz;
  1040. code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
  1041. if (!code_length) {
  1042. boot_addr = relocate ? qproc->mpss_phys : min_addr;
  1043. writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
  1044. writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
  1045. }
  1046. writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
  1047. ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
  1048. if (ret < 0) {
  1049. dev_err(qproc->dev, "MPSS authentication failed: %d\n",
  1050. ret);
  1051. goto release_firmware;
  1052. }
  1053. }
  1054. /* Transfer ownership of modem ddr region to q6 */
  1055. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
  1056. qproc->mpss_phys, qproc->mpss_size);
  1057. if (ret) {
  1058. dev_err(qproc->dev,
  1059. "assigning Q6 access to mpss memory failed: %d\n", ret);
  1060. ret = -EAGAIN;
  1061. goto release_firmware;
  1062. }
  1063. ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
  1064. if (ret == -ETIMEDOUT)
  1065. dev_err(qproc->dev, "MPSS authentication timed out\n");
  1066. else if (ret < 0)
  1067. dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
  1068. qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
  1069. release_firmware:
  1070. release_firmware(fw);
  1071. out:
  1072. kfree(fw_name);
  1073. return ret < 0 ? ret : 0;
  1074. }
  1075. static void qcom_q6v5_dump_segment(struct rproc *rproc,
  1076. struct rproc_dump_segment *segment,
  1077. void *dest, size_t cp_offset, size_t size)
  1078. {
  1079. int ret = 0;
  1080. struct q6v5 *qproc = rproc->priv;
  1081. int offset = segment->da - qproc->mpss_reloc;
  1082. void *ptr = NULL;
  1083. /* Unlock mba before copying segments */
  1084. if (!qproc->dump_mba_loaded) {
  1085. ret = q6v5_reload_mba(rproc);
  1086. if (!ret) {
  1087. /* Reset ownership back to Linux to copy segments */
  1088. ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
  1089. true, false,
  1090. qproc->mpss_phys,
  1091. qproc->mpss_size);
  1092. }
  1093. }
  1094. if (!ret)
  1095. ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
  1096. if (ptr) {
  1097. memcpy(dest, ptr, size);
  1098. memunmap(ptr);
  1099. } else {
  1100. memset(dest, 0xff, size);
  1101. }
  1102. qproc->current_dump_size += size;
  1103. /* Reclaim mba after copying segments */
  1104. if (qproc->current_dump_size == qproc->total_dump_size) {
  1105. if (qproc->dump_mba_loaded) {
  1106. /* Try to reset ownership back to Q6 */
  1107. q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
  1108. false, true,
  1109. qproc->mpss_phys,
  1110. qproc->mpss_size);
  1111. q6v5_mba_reclaim(qproc);
  1112. }
  1113. }
  1114. }
  1115. static int q6v5_start(struct rproc *rproc)
  1116. {
  1117. struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
  1118. int xfermemop_ret;
  1119. int ret;
  1120. ret = q6v5_mba_load(qproc);
  1121. if (ret)
  1122. return ret;
  1123. dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
  1124. qproc->dp_size ? "" : "out");
  1125. ret = q6v5_mpss_load(qproc);
  1126. if (ret)
  1127. goto reclaim_mpss;
  1128. ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
  1129. if (ret == -ETIMEDOUT) {
  1130. dev_err(qproc->dev, "start timed out\n");
  1131. goto reclaim_mpss;
  1132. }
  1133. xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
  1134. false, qproc->mba_phys,
  1135. qproc->mba_size);
  1136. if (xfermemop_ret)
  1137. dev_err(qproc->dev,
  1138. "Failed to reclaim mba buffer system may become unstable\n");
  1139. /* Reset Dump Segment Mask */
  1140. qproc->current_dump_size = 0;
  1141. return 0;
  1142. reclaim_mpss:
  1143. q6v5_mba_reclaim(qproc);
  1144. q6v5_dump_mba_logs(qproc);
  1145. return ret;
  1146. }
  1147. static int q6v5_stop(struct rproc *rproc)
  1148. {
  1149. struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
  1150. int ret;
  1151. ret = qcom_q6v5_request_stop(&qproc->q6v5);
  1152. if (ret == -ETIMEDOUT)
  1153. dev_err(qproc->dev, "timed out on wait\n");
  1154. q6v5_mba_reclaim(qproc);
  1155. return 0;
  1156. }
  1157. static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
  1158. const struct firmware *mba_fw)
  1159. {
  1160. const struct firmware *fw;
  1161. const struct elf32_phdr *phdrs;
  1162. const struct elf32_phdr *phdr;
  1163. const struct elf32_hdr *ehdr;
  1164. struct q6v5 *qproc = rproc->priv;
  1165. unsigned long i;
  1166. int ret;
  1167. ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
  1168. if (ret < 0) {
  1169. dev_err(qproc->dev, "unable to load %s\n",
  1170. qproc->hexagon_mdt_image);
  1171. return ret;
  1172. }
  1173. rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
  1174. ehdr = (struct elf32_hdr *)fw->data;
  1175. phdrs = (struct elf32_phdr *)(ehdr + 1);
  1176. qproc->total_dump_size = 0;
  1177. for (i = 0; i < ehdr->e_phnum; i++) {
  1178. phdr = &phdrs[i];
  1179. if (!q6v5_phdr_valid(phdr))
  1180. continue;
  1181. ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
  1182. phdr->p_memsz,
  1183. qcom_q6v5_dump_segment,
  1184. NULL);
  1185. if (ret)
  1186. break;
  1187. qproc->total_dump_size += phdr->p_memsz;
  1188. }
  1189. release_firmware(fw);
  1190. return ret;
  1191. }
  1192. static const struct rproc_ops q6v5_ops = {
  1193. .start = q6v5_start,
  1194. .stop = q6v5_stop,
  1195. .parse_fw = qcom_q6v5_register_dump_segments,
  1196. .load = q6v5_load,
  1197. };
  1198. static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
  1199. {
  1200. struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
  1201. q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
  1202. qproc->proxy_clk_count);
  1203. q6v5_regulator_disable(qproc, qproc->proxy_regs,
  1204. qproc->proxy_reg_count);
  1205. q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
  1206. }
  1207. static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
  1208. {
  1209. struct of_phandle_args args;
  1210. struct resource *res;
  1211. int ret;
  1212. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
  1213. qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
  1214. if (IS_ERR(qproc->reg_base))
  1215. return PTR_ERR(qproc->reg_base);
  1216. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
  1217. qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
  1218. if (IS_ERR(qproc->rmb_base))
  1219. return PTR_ERR(qproc->rmb_base);
  1220. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  1221. "qcom,halt-regs", 3, 0, &args);
  1222. if (ret < 0) {
  1223. dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
  1224. return -EINVAL;
  1225. }
  1226. qproc->halt_map = syscon_node_to_regmap(args.np);
  1227. of_node_put(args.np);
  1228. if (IS_ERR(qproc->halt_map))
  1229. return PTR_ERR(qproc->halt_map);
  1230. qproc->halt_q6 = args.args[0];
  1231. qproc->halt_modem = args.args[1];
  1232. qproc->halt_nc = args.args[2];
  1233. if (qproc->has_spare_reg) {
  1234. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  1235. "qcom,spare-regs",
  1236. 1, 0, &args);
  1237. if (ret < 0) {
  1238. dev_err(&pdev->dev, "failed to parse spare-regs\n");
  1239. return -EINVAL;
  1240. }
  1241. qproc->conn_map = syscon_node_to_regmap(args.np);
  1242. of_node_put(args.np);
  1243. if (IS_ERR(qproc->conn_map))
  1244. return PTR_ERR(qproc->conn_map);
  1245. qproc->conn_box = args.args[0];
  1246. }
  1247. return 0;
  1248. }
  1249. static int q6v5_init_clocks(struct device *dev, struct clk **clks,
  1250. char **clk_names)
  1251. {
  1252. int i;
  1253. if (!clk_names)
  1254. return 0;
  1255. for (i = 0; clk_names[i]; i++) {
  1256. clks[i] = devm_clk_get(dev, clk_names[i]);
  1257. if (IS_ERR(clks[i])) {
  1258. int rc = PTR_ERR(clks[i]);
  1259. if (rc != -EPROBE_DEFER)
  1260. dev_err(dev, "Failed to get %s clock\n",
  1261. clk_names[i]);
  1262. return rc;
  1263. }
  1264. }
  1265. return i;
  1266. }
  1267. static int q6v5_pds_attach(struct device *dev, struct device **devs,
  1268. char **pd_names)
  1269. {
  1270. size_t num_pds = 0;
  1271. int ret;
  1272. int i;
  1273. if (!pd_names)
  1274. return 0;
  1275. while (pd_names[num_pds])
  1276. num_pds++;
  1277. for (i = 0; i < num_pds; i++) {
  1278. devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
  1279. if (IS_ERR_OR_NULL(devs[i])) {
  1280. ret = PTR_ERR(devs[i]) ? : -ENODATA;
  1281. goto unroll_attach;
  1282. }
  1283. }
  1284. return num_pds;
  1285. unroll_attach:
  1286. for (i--; i >= 0; i--)
  1287. dev_pm_domain_detach(devs[i], false);
  1288. return ret;
  1289. }
  1290. static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
  1291. size_t pd_count)
  1292. {
  1293. int i;
  1294. for (i = 0; i < pd_count; i++)
  1295. dev_pm_domain_detach(pds[i], false);
  1296. }
  1297. static int q6v5_init_reset(struct q6v5 *qproc)
  1298. {
  1299. qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
  1300. "mss_restart");
  1301. if (IS_ERR(qproc->mss_restart)) {
  1302. dev_err(qproc->dev, "failed to acquire mss restart\n");
  1303. return PTR_ERR(qproc->mss_restart);
  1304. }
  1305. if (qproc->has_alt_reset || qproc->has_spare_reg) {
  1306. qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
  1307. "pdc_reset");
  1308. if (IS_ERR(qproc->pdc_reset)) {
  1309. dev_err(qproc->dev, "failed to acquire pdc reset\n");
  1310. return PTR_ERR(qproc->pdc_reset);
  1311. }
  1312. }
  1313. return 0;
  1314. }
  1315. static int q6v5_alloc_memory_region(struct q6v5 *qproc)
  1316. {
  1317. struct device_node *child;
  1318. struct device_node *node;
  1319. struct resource r;
  1320. int ret;
  1321. /*
  1322. * In the absence of mba/mpss sub-child, extract the mba and mpss
  1323. * reserved memory regions from device's memory-region property.
  1324. */
  1325. child = of_get_child_by_name(qproc->dev->of_node, "mba");
  1326. if (!child) {
  1327. node = of_parse_phandle(qproc->dev->of_node,
  1328. "memory-region", 0);
  1329. } else {
  1330. node = of_parse_phandle(child, "memory-region", 0);
  1331. of_node_put(child);
  1332. }
  1333. ret = of_address_to_resource(node, 0, &r);
  1334. of_node_put(node);
  1335. if (ret) {
  1336. dev_err(qproc->dev, "unable to resolve mba region\n");
  1337. return ret;
  1338. }
  1339. qproc->mba_phys = r.start;
  1340. qproc->mba_size = resource_size(&r);
  1341. qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
  1342. if (!qproc->mba_region) {
  1343. dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
  1344. &r.start, qproc->mba_size);
  1345. return -EBUSY;
  1346. }
  1347. if (!child) {
  1348. node = of_parse_phandle(qproc->dev->of_node,
  1349. "memory-region", 1);
  1350. } else {
  1351. child = of_get_child_by_name(qproc->dev->of_node, "mpss");
  1352. node = of_parse_phandle(child, "memory-region", 0);
  1353. of_node_put(child);
  1354. }
  1355. ret = of_address_to_resource(node, 0, &r);
  1356. of_node_put(node);
  1357. if (ret) {
  1358. dev_err(qproc->dev, "unable to resolve mpss region\n");
  1359. return ret;
  1360. }
  1361. qproc->mpss_phys = qproc->mpss_reloc = r.start;
  1362. qproc->mpss_size = resource_size(&r);
  1363. return 0;
  1364. }
  1365. static int q6v5_probe(struct platform_device *pdev)
  1366. {
  1367. const struct rproc_hexagon_res *desc;
  1368. struct q6v5 *qproc;
  1369. struct rproc *rproc;
  1370. const char *mba_image;
  1371. int ret;
  1372. desc = of_device_get_match_data(&pdev->dev);
  1373. if (!desc)
  1374. return -EINVAL;
  1375. if (desc->need_mem_protection && !qcom_scm_is_available())
  1376. return -EPROBE_DEFER;
  1377. mba_image = desc->hexagon_mba_image;
  1378. ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
  1379. 0, &mba_image);
  1380. if (ret < 0 && ret != -EINVAL)
  1381. return ret;
  1382. rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
  1383. mba_image, sizeof(*qproc));
  1384. if (!rproc) {
  1385. dev_err(&pdev->dev, "failed to allocate rproc\n");
  1386. return -ENOMEM;
  1387. }
  1388. rproc->auto_boot = false;
  1389. rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
  1390. qproc = (struct q6v5 *)rproc->priv;
  1391. qproc->dev = &pdev->dev;
  1392. qproc->rproc = rproc;
  1393. qproc->hexagon_mdt_image = "modem.mdt";
  1394. ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
  1395. 1, &qproc->hexagon_mdt_image);
  1396. if (ret < 0 && ret != -EINVAL)
  1397. goto free_rproc;
  1398. platform_set_drvdata(pdev, qproc);
  1399. qproc->has_spare_reg = desc->has_spare_reg;
  1400. ret = q6v5_init_mem(qproc, pdev);
  1401. if (ret)
  1402. goto free_rproc;
  1403. ret = q6v5_alloc_memory_region(qproc);
  1404. if (ret)
  1405. goto free_rproc;
  1406. ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
  1407. desc->proxy_clk_names);
  1408. if (ret < 0) {
  1409. dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
  1410. goto free_rproc;
  1411. }
  1412. qproc->proxy_clk_count = ret;
  1413. ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
  1414. desc->reset_clk_names);
  1415. if (ret < 0) {
  1416. dev_err(&pdev->dev, "Failed to get reset clocks.\n");
  1417. goto free_rproc;
  1418. }
  1419. qproc->reset_clk_count = ret;
  1420. ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
  1421. desc->active_clk_names);
  1422. if (ret < 0) {
  1423. dev_err(&pdev->dev, "Failed to get active clocks.\n");
  1424. goto free_rproc;
  1425. }
  1426. qproc->active_clk_count = ret;
  1427. ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
  1428. desc->proxy_supply);
  1429. if (ret < 0) {
  1430. dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
  1431. goto free_rproc;
  1432. }
  1433. qproc->proxy_reg_count = ret;
  1434. ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
  1435. desc->active_supply);
  1436. if (ret < 0) {
  1437. dev_err(&pdev->dev, "Failed to get active regulators.\n");
  1438. goto free_rproc;
  1439. }
  1440. qproc->active_reg_count = ret;
  1441. ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
  1442. desc->active_pd_names);
  1443. if (ret < 0) {
  1444. dev_err(&pdev->dev, "Failed to attach active power domains\n");
  1445. goto free_rproc;
  1446. }
  1447. qproc->active_pd_count = ret;
  1448. ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
  1449. desc->proxy_pd_names);
  1450. if (ret < 0) {
  1451. dev_err(&pdev->dev, "Failed to init power domains\n");
  1452. goto detach_active_pds;
  1453. }
  1454. qproc->proxy_pd_count = ret;
  1455. qproc->has_alt_reset = desc->has_alt_reset;
  1456. ret = q6v5_init_reset(qproc);
  1457. if (ret)
  1458. goto detach_proxy_pds;
  1459. qproc->version = desc->version;
  1460. qproc->need_mem_protection = desc->need_mem_protection;
  1461. qproc->has_mba_logs = desc->has_mba_logs;
  1462. ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
  1463. qcom_msa_handover);
  1464. if (ret)
  1465. goto detach_proxy_pds;
  1466. qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
  1467. qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
  1468. qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
  1469. qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
  1470. qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
  1471. qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
  1472. if (IS_ERR(qproc->sysmon)) {
  1473. ret = PTR_ERR(qproc->sysmon);
  1474. goto remove_subdevs;
  1475. }
  1476. ret = rproc_add(rproc);
  1477. if (ret)
  1478. goto remove_sysmon_subdev;
  1479. return 0;
  1480. remove_sysmon_subdev:
  1481. qcom_remove_sysmon_subdev(qproc->sysmon);
  1482. remove_subdevs:
  1483. qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
  1484. qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
  1485. qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
  1486. detach_proxy_pds:
  1487. q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
  1488. detach_active_pds:
  1489. q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
  1490. free_rproc:
  1491. rproc_free(rproc);
  1492. return ret;
  1493. }
  1494. static int q6v5_remove(struct platform_device *pdev)
  1495. {
  1496. struct q6v5 *qproc = platform_get_drvdata(pdev);
  1497. struct rproc *rproc = qproc->rproc;
  1498. rproc_del(rproc);
  1499. qcom_remove_sysmon_subdev(qproc->sysmon);
  1500. qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
  1501. qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
  1502. qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
  1503. q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
  1504. q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
  1505. rproc_free(rproc);
  1506. return 0;
  1507. }
  1508. static const struct rproc_hexagon_res sc7180_mss = {
  1509. .hexagon_mba_image = "mba.mbn",
  1510. .proxy_clk_names = (char*[]){
  1511. "xo",
  1512. NULL
  1513. },
  1514. .reset_clk_names = (char*[]){
  1515. "iface",
  1516. "bus",
  1517. "snoc_axi",
  1518. NULL
  1519. },
  1520. .active_clk_names = (char*[]){
  1521. "mnoc_axi",
  1522. "nav",
  1523. NULL
  1524. },
  1525. .active_pd_names = (char*[]){
  1526. "load_state",
  1527. NULL
  1528. },
  1529. .proxy_pd_names = (char*[]){
  1530. "cx",
  1531. "mx",
  1532. "mss",
  1533. NULL
  1534. },
  1535. .need_mem_protection = true,
  1536. .has_alt_reset = false,
  1537. .has_mba_logs = true,
  1538. .has_spare_reg = true,
  1539. .version = MSS_SC7180,
  1540. };
  1541. static const struct rproc_hexagon_res sdm845_mss = {
  1542. .hexagon_mba_image = "mba.mbn",
  1543. .proxy_clk_names = (char*[]){
  1544. "xo",
  1545. "prng",
  1546. NULL
  1547. },
  1548. .reset_clk_names = (char*[]){
  1549. "iface",
  1550. "snoc_axi",
  1551. NULL
  1552. },
  1553. .active_clk_names = (char*[]){
  1554. "bus",
  1555. "mem",
  1556. "gpll0_mss",
  1557. "mnoc_axi",
  1558. NULL
  1559. },
  1560. .active_pd_names = (char*[]){
  1561. "load_state",
  1562. NULL
  1563. },
  1564. .proxy_pd_names = (char*[]){
  1565. "cx",
  1566. "mx",
  1567. "mss",
  1568. NULL
  1569. },
  1570. .need_mem_protection = true,
  1571. .has_alt_reset = true,
  1572. .has_mba_logs = false,
  1573. .has_spare_reg = false,
  1574. .version = MSS_SDM845,
  1575. };
  1576. static const struct rproc_hexagon_res msm8998_mss = {
  1577. .hexagon_mba_image = "mba.mbn",
  1578. .proxy_clk_names = (char*[]){
  1579. "xo",
  1580. "qdss",
  1581. "mem",
  1582. NULL
  1583. },
  1584. .active_clk_names = (char*[]){
  1585. "iface",
  1586. "bus",
  1587. "gpll0_mss",
  1588. "mnoc_axi",
  1589. "snoc_axi",
  1590. NULL
  1591. },
  1592. .proxy_pd_names = (char*[]){
  1593. "cx",
  1594. "mx",
  1595. NULL
  1596. },
  1597. .need_mem_protection = true,
  1598. .has_alt_reset = false,
  1599. .has_mba_logs = false,
  1600. .has_spare_reg = false,
  1601. .version = MSS_MSM8998,
  1602. };
  1603. static const struct rproc_hexagon_res msm8996_mss = {
  1604. .hexagon_mba_image = "mba.mbn",
  1605. .proxy_supply = (struct qcom_mss_reg_res[]) {
  1606. {
  1607. .supply = "pll",
  1608. .uA = 100000,
  1609. },
  1610. {}
  1611. },
  1612. .proxy_clk_names = (char*[]){
  1613. "xo",
  1614. "pnoc",
  1615. "qdss",
  1616. NULL
  1617. },
  1618. .active_clk_names = (char*[]){
  1619. "iface",
  1620. "bus",
  1621. "mem",
  1622. "gpll0_mss",
  1623. "snoc_axi",
  1624. "mnoc_axi",
  1625. NULL
  1626. },
  1627. .need_mem_protection = true,
  1628. .has_alt_reset = false,
  1629. .has_mba_logs = false,
  1630. .has_spare_reg = false,
  1631. .version = MSS_MSM8996,
  1632. };
  1633. static const struct rproc_hexagon_res msm8916_mss = {
  1634. .hexagon_mba_image = "mba.mbn",
  1635. .proxy_supply = (struct qcom_mss_reg_res[]) {
  1636. {
  1637. .supply = "mx",
  1638. .uV = 1050000,
  1639. },
  1640. {
  1641. .supply = "cx",
  1642. .uA = 100000,
  1643. },
  1644. {
  1645. .supply = "pll",
  1646. .uA = 100000,
  1647. },
  1648. {}
  1649. },
  1650. .proxy_clk_names = (char*[]){
  1651. "xo",
  1652. NULL
  1653. },
  1654. .active_clk_names = (char*[]){
  1655. "iface",
  1656. "bus",
  1657. "mem",
  1658. NULL
  1659. },
  1660. .need_mem_protection = false,
  1661. .has_alt_reset = false,
  1662. .has_mba_logs = false,
  1663. .has_spare_reg = false,
  1664. .version = MSS_MSM8916,
  1665. };
  1666. static const struct rproc_hexagon_res msm8974_mss = {
  1667. .hexagon_mba_image = "mba.b00",
  1668. .proxy_supply = (struct qcom_mss_reg_res[]) {
  1669. {
  1670. .supply = "mx",
  1671. .uV = 1050000,
  1672. },
  1673. {
  1674. .supply = "cx",
  1675. .uA = 100000,
  1676. },
  1677. {
  1678. .supply = "pll",
  1679. .uA = 100000,
  1680. },
  1681. {}
  1682. },
  1683. .active_supply = (struct qcom_mss_reg_res[]) {
  1684. {
  1685. .supply = "mss",
  1686. .uV = 1050000,
  1687. .uA = 100000,
  1688. },
  1689. {}
  1690. },
  1691. .proxy_clk_names = (char*[]){
  1692. "xo",
  1693. NULL
  1694. },
  1695. .active_clk_names = (char*[]){
  1696. "iface",
  1697. "bus",
  1698. "mem",
  1699. NULL
  1700. },
  1701. .need_mem_protection = false,
  1702. .has_alt_reset = false,
  1703. .has_mba_logs = false,
  1704. .has_spare_reg = false,
  1705. .version = MSS_MSM8974,
  1706. };
  1707. static const struct of_device_id q6v5_of_match[] = {
  1708. { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
  1709. { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
  1710. { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
  1711. { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
  1712. { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
  1713. { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
  1714. { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
  1715. { },
  1716. };
  1717. MODULE_DEVICE_TABLE(of, q6v5_of_match);
  1718. static struct platform_driver q6v5_driver = {
  1719. .probe = q6v5_probe,
  1720. .remove = q6v5_remove,
  1721. .driver = {
  1722. .name = "qcom-q6v5-mss",
  1723. .of_match_table = q6v5_of_match,
  1724. },
  1725. };
  1726. module_platform_driver(q6v5_driver);
  1727. MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
  1728. MODULE_LICENSE("GPL v2");