qcom_q6v5_adsp.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
  4. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/firmware.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_domain.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regmap.h>
  21. #include <linux/remoteproc.h>
  22. #include <linux/reset.h>
  23. #include <linux/soc/qcom/mdt_loader.h>
  24. #include <linux/soc/qcom/smem.h>
  25. #include <linux/soc/qcom/smem_state.h>
  26. #include "qcom_common.h"
  27. #include "qcom_pil_info.h"
  28. #include "qcom_q6v5.h"
  29. #include "remoteproc_internal.h"
  30. /* time out value */
  31. #define ACK_TIMEOUT 1000
  32. #define BOOT_FSM_TIMEOUT 10000
  33. /* mask values */
  34. #define EVB_MASK GENMASK(27, 4)
  35. /*QDSP6SS register offsets*/
  36. #define RST_EVB_REG 0x10
  37. #define CORE_START_REG 0x400
  38. #define BOOT_CMD_REG 0x404
  39. #define BOOT_STATUS_REG 0x408
  40. #define RET_CFG_REG 0x1C
  41. /*TCSR register offsets*/
  42. #define LPASS_MASTER_IDLE_REG 0x8
  43. #define LPASS_HALTACK_REG 0x4
  44. #define LPASS_PWR_ON_REG 0x10
  45. #define LPASS_HALTREQ_REG 0x0
  46. #define QDSP6SS_XO_CBCR 0x38
  47. #define QDSP6SS_CORE_CBCR 0x20
  48. #define QDSP6SS_SLEEP_CBCR 0x3c
  49. struct adsp_pil_data {
  50. int crash_reason_smem;
  51. const char *firmware_name;
  52. const char *ssr_name;
  53. const char *sysmon_name;
  54. int ssctl_id;
  55. const char **clk_ids;
  56. int num_clks;
  57. };
  58. struct qcom_adsp {
  59. struct device *dev;
  60. struct rproc *rproc;
  61. struct qcom_q6v5 q6v5;
  62. struct clk *xo;
  63. int num_clks;
  64. struct clk_bulk_data *clks;
  65. void __iomem *qdsp6ss_base;
  66. struct reset_control *pdc_sync_reset;
  67. struct reset_control *restart;
  68. struct regmap *halt_map;
  69. unsigned int halt_lpass;
  70. int crash_reason_smem;
  71. const char *info_name;
  72. struct completion start_done;
  73. struct completion stop_done;
  74. phys_addr_t mem_phys;
  75. phys_addr_t mem_reloc;
  76. void *mem_region;
  77. size_t mem_size;
  78. struct qcom_rproc_glink glink_subdev;
  79. struct qcom_rproc_ssr ssr_subdev;
  80. struct qcom_sysmon *sysmon;
  81. };
  82. static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
  83. {
  84. unsigned long timeout;
  85. unsigned int val;
  86. int ret;
  87. /* Reset the retention logic */
  88. val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
  89. val |= 0x1;
  90. writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
  91. clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
  92. /* QDSP6 master port needs to be explicitly halted */
  93. ret = regmap_read(adsp->halt_map,
  94. adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
  95. if (ret || !val)
  96. goto reset;
  97. ret = regmap_read(adsp->halt_map,
  98. adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
  99. &val);
  100. if (ret || val)
  101. goto reset;
  102. regmap_write(adsp->halt_map,
  103. adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
  104. /* Wait for halt ACK from QDSP6 */
  105. timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
  106. for (;;) {
  107. ret = regmap_read(adsp->halt_map,
  108. adsp->halt_lpass + LPASS_HALTACK_REG, &val);
  109. if (ret || val || time_after(jiffies, timeout))
  110. break;
  111. usleep_range(1000, 1100);
  112. }
  113. ret = regmap_read(adsp->halt_map,
  114. adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
  115. if (ret || !val)
  116. dev_err(adsp->dev, "port failed halt\n");
  117. reset:
  118. /* Assert the LPASS PDC Reset */
  119. reset_control_assert(adsp->pdc_sync_reset);
  120. /* Place the LPASS processor into reset */
  121. reset_control_assert(adsp->restart);
  122. /* wait after asserting subsystem restart from AOSS */
  123. usleep_range(200, 300);
  124. /* Clear the halt request for the AXIM and AHBM for Q6 */
  125. regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
  126. /* De-assert the LPASS PDC Reset */
  127. reset_control_deassert(adsp->pdc_sync_reset);
  128. /* Remove the LPASS reset */
  129. reset_control_deassert(adsp->restart);
  130. /* wait after de-asserting subsystem restart from AOSS */
  131. usleep_range(200, 300);
  132. return 0;
  133. }
  134. static int adsp_load(struct rproc *rproc, const struct firmware *fw)
  135. {
  136. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  137. int ret;
  138. ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
  139. adsp->mem_region, adsp->mem_phys,
  140. adsp->mem_size, &adsp->mem_reloc);
  141. if (ret)
  142. return ret;
  143. qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
  144. return 0;
  145. }
  146. static int adsp_start(struct rproc *rproc)
  147. {
  148. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  149. int ret;
  150. unsigned int val;
  151. qcom_q6v5_prepare(&adsp->q6v5);
  152. ret = clk_prepare_enable(adsp->xo);
  153. if (ret)
  154. goto disable_irqs;
  155. dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
  156. ret = pm_runtime_get_sync(adsp->dev);
  157. if (ret) {
  158. pm_runtime_put_noidle(adsp->dev);
  159. goto disable_xo_clk;
  160. }
  161. ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
  162. if (ret) {
  163. dev_err(adsp->dev, "adsp clk_enable failed\n");
  164. goto disable_power_domain;
  165. }
  166. /* Enable the XO clock */
  167. writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
  168. /* Enable the QDSP6SS sleep clock */
  169. writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
  170. /* Enable the QDSP6 core clock */
  171. writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
  172. /* Program boot address */
  173. writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
  174. /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
  175. writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
  176. /* Trigger boot FSM to start QDSP6 */
  177. writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
  178. /* Wait for core to come out of reset */
  179. ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
  180. val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
  181. if (ret) {
  182. dev_err(adsp->dev, "failed to bootup adsp\n");
  183. goto disable_adsp_clks;
  184. }
  185. ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
  186. if (ret == -ETIMEDOUT) {
  187. dev_err(adsp->dev, "start timed out\n");
  188. goto disable_adsp_clks;
  189. }
  190. return 0;
  191. disable_adsp_clks:
  192. clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
  193. disable_power_domain:
  194. dev_pm_genpd_set_performance_state(adsp->dev, 0);
  195. pm_runtime_put(adsp->dev);
  196. disable_xo_clk:
  197. clk_disable_unprepare(adsp->xo);
  198. disable_irqs:
  199. qcom_q6v5_unprepare(&adsp->q6v5);
  200. return ret;
  201. }
  202. static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
  203. {
  204. struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
  205. clk_disable_unprepare(adsp->xo);
  206. dev_pm_genpd_set_performance_state(adsp->dev, 0);
  207. pm_runtime_put(adsp->dev);
  208. }
  209. static int adsp_stop(struct rproc *rproc)
  210. {
  211. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  212. int handover;
  213. int ret;
  214. ret = qcom_q6v5_request_stop(&adsp->q6v5);
  215. if (ret == -ETIMEDOUT)
  216. dev_err(adsp->dev, "timed out on wait\n");
  217. ret = qcom_adsp_shutdown(adsp);
  218. if (ret)
  219. dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
  220. handover = qcom_q6v5_unprepare(&adsp->q6v5);
  221. if (handover)
  222. qcom_adsp_pil_handover(&adsp->q6v5);
  223. return ret;
  224. }
  225. static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  226. {
  227. struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
  228. int offset;
  229. offset = da - adsp->mem_reloc;
  230. if (offset < 0 || offset + len > adsp->mem_size)
  231. return NULL;
  232. return adsp->mem_region + offset;
  233. }
  234. static unsigned long adsp_panic(struct rproc *rproc)
  235. {
  236. struct qcom_adsp *adsp = rproc->priv;
  237. return qcom_q6v5_panic(&adsp->q6v5);
  238. }
  239. static const struct rproc_ops adsp_ops = {
  240. .start = adsp_start,
  241. .stop = adsp_stop,
  242. .da_to_va = adsp_da_to_va,
  243. .parse_fw = qcom_register_dump_segments,
  244. .load = adsp_load,
  245. .panic = adsp_panic,
  246. };
  247. static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
  248. {
  249. int num_clks = 0;
  250. int i, ret;
  251. adsp->xo = devm_clk_get(adsp->dev, "xo");
  252. if (IS_ERR(adsp->xo)) {
  253. ret = PTR_ERR(adsp->xo);
  254. if (ret != -EPROBE_DEFER)
  255. dev_err(adsp->dev, "failed to get xo clock");
  256. return ret;
  257. }
  258. for (i = 0; clk_ids[i]; i++)
  259. num_clks++;
  260. adsp->num_clks = num_clks;
  261. adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
  262. sizeof(*adsp->clks), GFP_KERNEL);
  263. if (!adsp->clks)
  264. return -ENOMEM;
  265. for (i = 0; i < adsp->num_clks; i++)
  266. adsp->clks[i].id = clk_ids[i];
  267. return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
  268. }
  269. static int adsp_init_reset(struct qcom_adsp *adsp)
  270. {
  271. adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
  272. "pdc_sync");
  273. if (IS_ERR(adsp->pdc_sync_reset)) {
  274. dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
  275. return PTR_ERR(adsp->pdc_sync_reset);
  276. }
  277. adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
  278. /* Fall back to the old "cc_lpass" if "restart" is absent */
  279. if (!adsp->restart)
  280. adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
  281. if (IS_ERR(adsp->restart)) {
  282. dev_err(adsp->dev, "failed to acquire restart\n");
  283. return PTR_ERR(adsp->restart);
  284. }
  285. return 0;
  286. }
  287. static int adsp_init_mmio(struct qcom_adsp *adsp,
  288. struct platform_device *pdev)
  289. {
  290. struct device_node *syscon;
  291. int ret;
  292. adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
  293. if (IS_ERR(adsp->qdsp6ss_base)) {
  294. dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
  295. return PTR_ERR(adsp->qdsp6ss_base);
  296. }
  297. syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
  298. if (!syscon) {
  299. dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
  300. return -EINVAL;
  301. }
  302. adsp->halt_map = syscon_node_to_regmap(syscon);
  303. of_node_put(syscon);
  304. if (IS_ERR(adsp->halt_map))
  305. return PTR_ERR(adsp->halt_map);
  306. ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
  307. 1, &adsp->halt_lpass);
  308. if (ret < 0) {
  309. dev_err(&pdev->dev, "no offset in syscon\n");
  310. return ret;
  311. }
  312. return 0;
  313. }
  314. static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
  315. {
  316. struct device_node *node;
  317. struct resource r;
  318. int ret;
  319. node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
  320. if (!node) {
  321. dev_err(adsp->dev, "no memory-region specified\n");
  322. return -EINVAL;
  323. }
  324. ret = of_address_to_resource(node, 0, &r);
  325. of_node_put(node);
  326. if (ret)
  327. return ret;
  328. adsp->mem_phys = adsp->mem_reloc = r.start;
  329. adsp->mem_size = resource_size(&r);
  330. adsp->mem_region = devm_ioremap_wc(adsp->dev,
  331. adsp->mem_phys, adsp->mem_size);
  332. if (!adsp->mem_region) {
  333. dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
  334. &r.start, adsp->mem_size);
  335. return -EBUSY;
  336. }
  337. return 0;
  338. }
  339. static int adsp_probe(struct platform_device *pdev)
  340. {
  341. const struct adsp_pil_data *desc;
  342. struct qcom_adsp *adsp;
  343. struct rproc *rproc;
  344. int ret;
  345. desc = of_device_get_match_data(&pdev->dev);
  346. if (!desc)
  347. return -EINVAL;
  348. rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
  349. desc->firmware_name, sizeof(*adsp));
  350. if (!rproc) {
  351. dev_err(&pdev->dev, "unable to allocate remoteproc\n");
  352. return -ENOMEM;
  353. }
  354. rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
  355. adsp = (struct qcom_adsp *)rproc->priv;
  356. adsp->dev = &pdev->dev;
  357. adsp->rproc = rproc;
  358. adsp->info_name = desc->sysmon_name;
  359. platform_set_drvdata(pdev, adsp);
  360. ret = adsp_alloc_memory_region(adsp);
  361. if (ret)
  362. goto free_rproc;
  363. ret = adsp_init_clock(adsp, desc->clk_ids);
  364. if (ret)
  365. goto free_rproc;
  366. pm_runtime_enable(adsp->dev);
  367. ret = adsp_init_reset(adsp);
  368. if (ret)
  369. goto disable_pm;
  370. ret = adsp_init_mmio(adsp, pdev);
  371. if (ret)
  372. goto disable_pm;
  373. ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
  374. qcom_adsp_pil_handover);
  375. if (ret)
  376. goto disable_pm;
  377. qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
  378. qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
  379. adsp->sysmon = qcom_add_sysmon_subdev(rproc,
  380. desc->sysmon_name,
  381. desc->ssctl_id);
  382. if (IS_ERR(adsp->sysmon)) {
  383. ret = PTR_ERR(adsp->sysmon);
  384. goto disable_pm;
  385. }
  386. ret = rproc_add(rproc);
  387. if (ret)
  388. goto disable_pm;
  389. return 0;
  390. disable_pm:
  391. pm_runtime_disable(adsp->dev);
  392. free_rproc:
  393. rproc_free(rproc);
  394. return ret;
  395. }
  396. static int adsp_remove(struct platform_device *pdev)
  397. {
  398. struct qcom_adsp *adsp = platform_get_drvdata(pdev);
  399. rproc_del(adsp->rproc);
  400. qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
  401. qcom_remove_sysmon_subdev(adsp->sysmon);
  402. qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
  403. pm_runtime_disable(adsp->dev);
  404. rproc_free(adsp->rproc);
  405. return 0;
  406. }
  407. static const struct adsp_pil_data adsp_resource_init = {
  408. .crash_reason_smem = 423,
  409. .firmware_name = "adsp.mdt",
  410. .ssr_name = "lpass",
  411. .sysmon_name = "adsp",
  412. .ssctl_id = 0x14,
  413. .clk_ids = (const char*[]) {
  414. "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
  415. "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
  416. },
  417. .num_clks = 7,
  418. };
  419. static const struct adsp_pil_data cdsp_resource_init = {
  420. .crash_reason_smem = 601,
  421. .firmware_name = "cdsp.mdt",
  422. .ssr_name = "cdsp",
  423. .sysmon_name = "cdsp",
  424. .ssctl_id = 0x17,
  425. .clk_ids = (const char*[]) {
  426. "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
  427. "q6_axim", NULL
  428. },
  429. .num_clks = 7,
  430. };
  431. static const struct of_device_id adsp_of_match[] = {
  432. { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
  433. { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
  434. { },
  435. };
  436. MODULE_DEVICE_TABLE(of, adsp_of_match);
  437. static struct platform_driver adsp_pil_driver = {
  438. .probe = adsp_probe,
  439. .remove = adsp_remove,
  440. .driver = {
  441. .name = "qcom_q6v5_adsp",
  442. .of_match_table = adsp_of_match,
  443. },
  444. };
  445. module_platform_driver(adsp_pil_driver);
  446. MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
  447. MODULE_LICENSE("GPL v2");