qcom_spmi-regulator.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/kernel.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/bitops.h>
  11. #include <linux/slab.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/ktime.h>
  16. #include <linux/regulator/driver.h>
  17. #include <linux/regmap.h>
  18. #include <linux/list.h>
  19. #include <linux/mfd/syscon.h>
  20. #include <linux/io.h>
  21. /* Pin control enable input pins. */
  22. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
  23. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
  24. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
  25. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
  26. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
  27. #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
  28. /* Pin control high power mode input pins. */
  29. #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
  30. #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
  31. #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
  32. #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
  33. #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
  34. #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
  35. #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
  36. /*
  37. * Used with enable parameters to specify that hardware default register values
  38. * should be left unaltered.
  39. */
  40. #define SPMI_REGULATOR_USE_HW_DEFAULT 2
  41. /* Soft start strength of a voltage switch type regulator */
  42. enum spmi_vs_soft_start_str {
  43. SPMI_VS_SOFT_START_STR_0P05_UA = 0,
  44. SPMI_VS_SOFT_START_STR_0P25_UA,
  45. SPMI_VS_SOFT_START_STR_0P55_UA,
  46. SPMI_VS_SOFT_START_STR_0P75_UA,
  47. SPMI_VS_SOFT_START_STR_HW_DEFAULT,
  48. };
  49. /**
  50. * struct spmi_regulator_init_data - spmi-regulator initialization data
  51. * @pin_ctrl_enable: Bit mask specifying which hardware pins should be
  52. * used to enable the regulator, if any
  53. * Value should be an ORing of
  54. * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If
  55. * the bit specified by
  56. * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
  57. * set, then pin control enable hardware registers
  58. * will not be modified.
  59. * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
  60. * used to force the regulator into high power
  61. * mode, if any
  62. * Value should be an ORing of
  63. * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If
  64. * the bit specified by
  65. * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
  66. * set, then pin control mode hardware registers
  67. * will not be modified.
  68. * @vs_soft_start_strength: This parameter sets the soft start strength for
  69. * voltage switch type regulators. Its value
  70. * should be one of SPMI_VS_SOFT_START_STR_*. If
  71. * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
  72. * then the soft start strength will be left at its
  73. * default hardware value.
  74. */
  75. struct spmi_regulator_init_data {
  76. unsigned pin_ctrl_enable;
  77. unsigned pin_ctrl_hpm;
  78. enum spmi_vs_soft_start_str vs_soft_start_strength;
  79. };
  80. /* These types correspond to unique register layouts. */
  81. enum spmi_regulator_logical_type {
  82. SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
  83. SPMI_REGULATOR_LOGICAL_TYPE_LDO,
  84. SPMI_REGULATOR_LOGICAL_TYPE_VS,
  85. SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
  86. SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
  87. SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
  88. SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
  89. SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
  90. SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
  91. SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
  92. SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426,
  93. SPMI_REGULATOR_LOGICAL_TYPE_HFS430,
  94. };
  95. enum spmi_regulator_type {
  96. SPMI_REGULATOR_TYPE_BUCK = 0x03,
  97. SPMI_REGULATOR_TYPE_LDO = 0x04,
  98. SPMI_REGULATOR_TYPE_VS = 0x05,
  99. SPMI_REGULATOR_TYPE_BOOST = 0x1b,
  100. SPMI_REGULATOR_TYPE_FTS = 0x1c,
  101. SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
  102. SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
  103. SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
  104. };
  105. enum spmi_regulator_subtype {
  106. SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
  107. SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
  108. SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
  109. SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
  110. SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
  111. SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
  112. SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
  113. SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
  114. SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
  115. SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
  116. SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
  117. SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
  118. SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
  119. SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
  120. SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
  121. SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
  122. SPMI_REGULATOR_SUBTYPE_LN = 0x10,
  123. SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
  124. SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
  125. SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
  126. SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
  127. SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
  128. SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
  129. SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30,
  130. SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31,
  131. SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32,
  132. SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b,
  133. SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c,
  134. SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42,
  135. SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43,
  136. SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46,
  137. SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47,
  138. SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49,
  139. SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d,
  140. SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f,
  141. SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
  142. SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
  143. SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
  144. SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
  145. SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
  146. SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
  147. SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
  148. SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
  149. SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
  150. SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a,
  151. SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
  152. SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
  153. SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
  154. SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
  155. SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
  156. SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
  157. };
  158. enum spmi_common_regulator_registers {
  159. SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
  160. SPMI_COMMON_REG_TYPE = 0x04,
  161. SPMI_COMMON_REG_SUBTYPE = 0x05,
  162. SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
  163. SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
  164. SPMI_COMMON_REG_MODE = 0x45,
  165. SPMI_COMMON_REG_ENABLE = 0x46,
  166. SPMI_COMMON_REG_PULL_DOWN = 0x48,
  167. SPMI_COMMON_REG_SOFT_START = 0x4c,
  168. SPMI_COMMON_REG_STEP_CTRL = 0x61,
  169. };
  170. /*
  171. * Second common register layout used by newer devices starting with ftsmps426
  172. * Note that some of the registers from the first common layout remain
  173. * unchanged and their definition is not duplicated.
  174. */
  175. enum spmi_ftsmps426_regulator_registers {
  176. SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40,
  177. SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41,
  178. SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68,
  179. SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69,
  180. };
  181. enum spmi_vs_registers {
  182. SPMI_VS_REG_OCP = 0x4a,
  183. SPMI_VS_REG_SOFT_START = 0x4c,
  184. };
  185. enum spmi_boost_registers {
  186. SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
  187. };
  188. enum spmi_boost_byp_registers {
  189. SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
  190. };
  191. enum spmi_saw3_registers {
  192. SAW3_SECURE = 0x00,
  193. SAW3_ID = 0x04,
  194. SAW3_SPM_STS = 0x0C,
  195. SAW3_AVS_STS = 0x10,
  196. SAW3_PMIC_STS = 0x14,
  197. SAW3_RST = 0x18,
  198. SAW3_VCTL = 0x1C,
  199. SAW3_AVS_CTL = 0x20,
  200. SAW3_AVS_LIMIT = 0x24,
  201. SAW3_AVS_DLY = 0x28,
  202. SAW3_AVS_HYSTERESIS = 0x2C,
  203. SAW3_SPM_STS2 = 0x38,
  204. SAW3_SPM_PMIC_DATA_3 = 0x4C,
  205. SAW3_VERSION = 0xFD0,
  206. };
  207. /* Used for indexing into ctrl_reg. These are offets from 0x40 */
  208. enum spmi_common_control_register_index {
  209. SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
  210. SPMI_COMMON_IDX_VOLTAGE_SET = 1,
  211. SPMI_COMMON_IDX_MODE = 5,
  212. SPMI_COMMON_IDX_ENABLE = 6,
  213. };
  214. /* Common regulator control register layout */
  215. #define SPMI_COMMON_ENABLE_MASK 0x80
  216. #define SPMI_COMMON_ENABLE 0x80
  217. #define SPMI_COMMON_DISABLE 0x00
  218. #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
  219. #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
  220. #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
  221. #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
  222. #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
  223. /* Common regulator mode register layout */
  224. #define SPMI_COMMON_MODE_HPM_MASK 0x80
  225. #define SPMI_COMMON_MODE_AUTO_MASK 0x40
  226. #define SPMI_COMMON_MODE_BYPASS_MASK 0x20
  227. #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
  228. #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
  229. #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
  230. #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
  231. #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
  232. #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
  233. #define SPMI_FTSMPS426_MODE_BYPASS_MASK 3
  234. #define SPMI_FTSMPS426_MODE_RETENTION_MASK 4
  235. #define SPMI_FTSMPS426_MODE_LPM_MASK 5
  236. #define SPMI_FTSMPS426_MODE_AUTO_MASK 6
  237. #define SPMI_FTSMPS426_MODE_HPM_MASK 7
  238. #define SPMI_FTSMPS426_MODE_MASK 0x07
  239. /* Common regulator pull down control register layout */
  240. #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
  241. /* LDO regulator current limit control register layout */
  242. #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
  243. /* LDO regulator soft start control register layout */
  244. #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
  245. /* VS regulator over current protection control register layout */
  246. #define SPMI_VS_OCP_OVERRIDE 0x01
  247. #define SPMI_VS_OCP_NO_OVERRIDE 0x00
  248. /* VS regulator soft start control register layout */
  249. #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
  250. #define SPMI_VS_SOFT_START_SEL_MASK 0x03
  251. /* Boost regulator current limit control register layout */
  252. #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
  253. #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
  254. #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10
  255. #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30
  256. #define SPMI_VS_OCP_FALL_DELAY_US 90
  257. #define SPMI_VS_OCP_FAULT_DELAY_US 20000
  258. #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
  259. #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3
  260. #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
  261. #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
  262. /* Clock rate in kHz of the FTSMPS regulator reference clock. */
  263. #define SPMI_FTSMPS_CLOCK_RATE 19200
  264. /* Minimum voltage stepper delay for each step. */
  265. #define SPMI_FTSMPS_STEP_DELAY 8
  266. #define SPMI_DEFAULT_STEP_DELAY 20
  267. /*
  268. * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to
  269. * adjust the step rate in order to account for oscillator variance.
  270. */
  271. #define SPMI_FTSMPS_STEP_MARGIN_NUM 4
  272. #define SPMI_FTSMPS_STEP_MARGIN_DEN 5
  273. #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03
  274. #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0
  275. /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */
  276. #define SPMI_FTSMPS426_CLOCK_RATE 4800
  277. #define SPMI_HFS430_CLOCK_RATE 1600
  278. /* Minimum voltage stepper delay for each step. */
  279. #define SPMI_FTSMPS426_STEP_DELAY 2
  280. /*
  281. * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is
  282. * used to adjust the step rate in order to account for oscillator variance.
  283. */
  284. #define SPMI_FTSMPS426_STEP_MARGIN_NUM 10
  285. #define SPMI_FTSMPS426_STEP_MARGIN_DEN 11
  286. /* VSET value to decide the range of ULT SMPS */
  287. #define ULT_SMPS_RANGE_SPLIT 0x60
  288. /**
  289. * struct spmi_voltage_range - regulator set point voltage mapping description
  290. * @min_uV: Minimum programmable output voltage resulting from
  291. * set point register value 0x00
  292. * @max_uV: Maximum programmable output voltage
  293. * @step_uV: Output voltage increase resulting from the set point
  294. * register value increasing by 1
  295. * @set_point_min_uV: Minimum allowed voltage
  296. * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order
  297. * to pick which range should be used in the case of
  298. * overlapping set points.
  299. * @n_voltages: Number of preferred voltage set points present in this
  300. * range
  301. * @range_sel: Voltage range register value corresponding to this range
  302. *
  303. * The following relationships must be true for the values used in this struct:
  304. * (max_uV - min_uV) % step_uV == 0
  305. * (set_point_min_uV - min_uV) % step_uV == 0*
  306. * (set_point_max_uV - min_uV) % step_uV == 0*
  307. * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
  308. *
  309. * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
  310. * specify that the voltage range has meaning, but is not preferred.
  311. */
  312. struct spmi_voltage_range {
  313. int min_uV;
  314. int max_uV;
  315. int step_uV;
  316. int set_point_min_uV;
  317. int set_point_max_uV;
  318. unsigned n_voltages;
  319. u8 range_sel;
  320. };
  321. /*
  322. * The ranges specified in the spmi_voltage_set_points struct must be listed
  323. * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV.
  324. */
  325. struct spmi_voltage_set_points {
  326. struct spmi_voltage_range *range;
  327. int count;
  328. unsigned n_voltages;
  329. };
  330. struct spmi_regulator {
  331. struct regulator_desc desc;
  332. struct device *dev;
  333. struct delayed_work ocp_work;
  334. struct regmap *regmap;
  335. struct spmi_voltage_set_points *set_points;
  336. enum spmi_regulator_logical_type logical_type;
  337. int ocp_irq;
  338. int ocp_count;
  339. int ocp_max_retries;
  340. int ocp_retry_delay_ms;
  341. int hpm_min_load;
  342. int slew_rate;
  343. ktime_t vs_enable_time;
  344. u16 base;
  345. struct list_head node;
  346. };
  347. struct spmi_regulator_mapping {
  348. enum spmi_regulator_type type;
  349. enum spmi_regulator_subtype subtype;
  350. enum spmi_regulator_logical_type logical_type;
  351. u32 revision_min;
  352. u32 revision_max;
  353. const struct regulator_ops *ops;
  354. struct spmi_voltage_set_points *set_points;
  355. int hpm_min_load;
  356. };
  357. struct spmi_regulator_data {
  358. const char *name;
  359. u16 base;
  360. const char *supply;
  361. const char *ocp;
  362. u16 force_type;
  363. };
  364. #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \
  365. _logical_type, _ops_val, _set_points_val, _hpm_min_load) \
  366. { \
  367. .type = SPMI_REGULATOR_TYPE_##_type, \
  368. .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
  369. .revision_min = _dig_major_min, \
  370. .revision_max = _dig_major_max, \
  371. .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \
  372. .ops = &spmi_##_ops_val##_ops, \
  373. .set_points = &_set_points_val##_set_points, \
  374. .hpm_min_load = _hpm_min_load, \
  375. }
  376. #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \
  377. { \
  378. .type = SPMI_REGULATOR_TYPE_VS, \
  379. .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
  380. .revision_min = _dig_major_min, \
  381. .revision_max = _dig_major_max, \
  382. .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \
  383. .ops = &spmi_vs_ops, \
  384. }
  385. #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \
  386. _set_point_max_uV, _max_uV, _step_uV) \
  387. { \
  388. .min_uV = _min_uV, \
  389. .max_uV = _max_uV, \
  390. .set_point_min_uV = _set_point_min_uV, \
  391. .set_point_max_uV = _set_point_max_uV, \
  392. .step_uV = _step_uV, \
  393. .range_sel = _range_sel, \
  394. }
  395. #define DEFINE_SPMI_SET_POINTS(name) \
  396. struct spmi_voltage_set_points name##_set_points = { \
  397. .range = name##_ranges, \
  398. .count = ARRAY_SIZE(name##_ranges), \
  399. }
  400. /*
  401. * These tables contain the physically available PMIC regulator voltage setpoint
  402. * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed
  403. * to ensure that the setpoints available to software are monotonically
  404. * increasing and unique. The set_voltage callback functions expect these
  405. * properties to hold.
  406. */
  407. static struct spmi_voltage_range pldo_ranges[] = {
  408. SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
  409. SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000),
  410. SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000),
  411. };
  412. static struct spmi_voltage_range nldo1_ranges[] = {
  413. SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
  414. };
  415. static struct spmi_voltage_range nldo2_ranges[] = {
  416. SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
  417. SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250),
  418. SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500),
  419. };
  420. static struct spmi_voltage_range nldo3_ranges[] = {
  421. SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
  422. SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
  423. SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
  424. };
  425. static struct spmi_voltage_range ln_ldo_ranges[] = {
  426. SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000),
  427. SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
  428. };
  429. static struct spmi_voltage_range smps_ranges[] = {
  430. SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
  431. SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
  432. };
  433. static struct spmi_voltage_range ftsmps_ranges[] = {
  434. SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
  435. SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
  436. };
  437. static struct spmi_voltage_range ftsmps2p5_ranges[] = {
  438. SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
  439. SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000),
  440. };
  441. static struct spmi_voltage_range ftsmps426_ranges[] = {
  442. SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
  443. };
  444. static struct spmi_voltage_range boost_ranges[] = {
  445. SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
  446. };
  447. static struct spmi_voltage_range boost_byp_ranges[] = {
  448. SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
  449. };
  450. static struct spmi_voltage_range ult_lo_smps_ranges[] = {
  451. SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
  452. SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
  453. };
  454. static struct spmi_voltage_range ult_ho_smps_ranges[] = {
  455. SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
  456. };
  457. static struct spmi_voltage_range ult_nldo_ranges[] = {
  458. SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
  459. };
  460. static struct spmi_voltage_range ult_pldo_ranges[] = {
  461. SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
  462. };
  463. static struct spmi_voltage_range pldo660_ranges[] = {
  464. SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
  465. };
  466. static struct spmi_voltage_range nldo660_ranges[] = {
  467. SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
  468. };
  469. static struct spmi_voltage_range ht_lvpldo_ranges[] = {
  470. SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
  471. };
  472. static struct spmi_voltage_range ht_nldo_ranges[] = {
  473. SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000),
  474. };
  475. static struct spmi_voltage_range hfs430_ranges[] = {
  476. SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
  477. };
  478. static DEFINE_SPMI_SET_POINTS(pldo);
  479. static DEFINE_SPMI_SET_POINTS(nldo1);
  480. static DEFINE_SPMI_SET_POINTS(nldo2);
  481. static DEFINE_SPMI_SET_POINTS(nldo3);
  482. static DEFINE_SPMI_SET_POINTS(ln_ldo);
  483. static DEFINE_SPMI_SET_POINTS(smps);
  484. static DEFINE_SPMI_SET_POINTS(ftsmps);
  485. static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
  486. static DEFINE_SPMI_SET_POINTS(ftsmps426);
  487. static DEFINE_SPMI_SET_POINTS(boost);
  488. static DEFINE_SPMI_SET_POINTS(boost_byp);
  489. static DEFINE_SPMI_SET_POINTS(ult_lo_smps);
  490. static DEFINE_SPMI_SET_POINTS(ult_ho_smps);
  491. static DEFINE_SPMI_SET_POINTS(ult_nldo);
  492. static DEFINE_SPMI_SET_POINTS(ult_pldo);
  493. static DEFINE_SPMI_SET_POINTS(pldo660);
  494. static DEFINE_SPMI_SET_POINTS(nldo660);
  495. static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
  496. static DEFINE_SPMI_SET_POINTS(ht_nldo);
  497. static DEFINE_SPMI_SET_POINTS(hfs430);
  498. static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
  499. int len)
  500. {
  501. return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len);
  502. }
  503. static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr,
  504. u8 *buf, int len)
  505. {
  506. return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len);
  507. }
  508. static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val,
  509. u8 mask)
  510. {
  511. return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val);
  512. }
  513. static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
  514. {
  515. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  516. if (vreg->ocp_irq) {
  517. vreg->ocp_count = 0;
  518. vreg->vs_enable_time = ktime_get();
  519. }
  520. return regulator_enable_regmap(rdev);
  521. }
  522. static int spmi_regulator_vs_ocp(struct regulator_dev *rdev)
  523. {
  524. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  525. u8 reg = SPMI_VS_OCP_OVERRIDE;
  526. return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, &reg, 1);
  527. }
  528. static int spmi_regulator_select_voltage(struct spmi_regulator *vreg,
  529. int min_uV, int max_uV)
  530. {
  531. const struct spmi_voltage_range *range;
  532. int uV = min_uV;
  533. int lim_min_uV, lim_max_uV, i, range_id, range_max_uV;
  534. int selector, voltage_sel;
  535. /* Check if request voltage is outside of physically settable range. */
  536. lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
  537. lim_max_uV =
  538. vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV;
  539. if (uV < lim_min_uV && max_uV >= lim_min_uV)
  540. uV = lim_min_uV;
  541. if (uV < lim_min_uV || uV > lim_max_uV) {
  542. dev_err(vreg->dev,
  543. "request v=[%d, %d] is outside possible v=[%d, %d]\n",
  544. min_uV, max_uV, lim_min_uV, lim_max_uV);
  545. return -EINVAL;
  546. }
  547. /* Find the range which uV is inside of. */
  548. for (i = vreg->set_points->count - 1; i > 0; i--) {
  549. range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV;
  550. if (uV > range_max_uV && range_max_uV > 0)
  551. break;
  552. }
  553. range_id = i;
  554. range = &vreg->set_points->range[range_id];
  555. /*
  556. * Force uV to be an allowed set point by applying a ceiling function to
  557. * the uV value.
  558. */
  559. voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
  560. uV = voltage_sel * range->step_uV + range->min_uV;
  561. if (uV > max_uV) {
  562. dev_err(vreg->dev,
  563. "request v=[%d, %d] cannot be met by any set point; "
  564. "next set point: %d\n",
  565. min_uV, max_uV, uV);
  566. return -EINVAL;
  567. }
  568. selector = 0;
  569. for (i = 0; i < range_id; i++)
  570. selector += vreg->set_points->range[i].n_voltages;
  571. selector += (uV - range->set_point_min_uV) / range->step_uV;
  572. return selector;
  573. }
  574. static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
  575. unsigned selector, u8 *range_sel,
  576. u8 *voltage_sel)
  577. {
  578. const struct spmi_voltage_range *range, *end;
  579. unsigned offset;
  580. range = vreg->set_points->range;
  581. end = range + vreg->set_points->count;
  582. for (; range < end; range++) {
  583. if (selector < range->n_voltages) {
  584. /*
  585. * hardware selectors between set point min and real
  586. * min are invalid so we ignore them
  587. */
  588. offset = range->set_point_min_uV - range->min_uV;
  589. offset /= range->step_uV;
  590. *voltage_sel = selector + offset;
  591. *range_sel = range->range_sel;
  592. return 0;
  593. }
  594. selector -= range->n_voltages;
  595. }
  596. return -EINVAL;
  597. }
  598. static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
  599. const struct spmi_voltage_range *range)
  600. {
  601. unsigned sw_sel = 0;
  602. unsigned offset, max_hw_sel;
  603. const struct spmi_voltage_range *r = vreg->set_points->range;
  604. const struct spmi_voltage_range *end = r + vreg->set_points->count;
  605. for (; r < end; r++) {
  606. if (r == range && range->n_voltages) {
  607. /*
  608. * hardware selectors between set point min and real
  609. * min and between set point max and real max are
  610. * invalid so we return an error if they're
  611. * programmed into the hardware
  612. */
  613. offset = range->set_point_min_uV - range->min_uV;
  614. offset /= range->step_uV;
  615. if (hw_sel < offset)
  616. return -EINVAL;
  617. max_hw_sel = range->set_point_max_uV - range->min_uV;
  618. max_hw_sel /= range->step_uV;
  619. if (hw_sel > max_hw_sel)
  620. return -EINVAL;
  621. return sw_sel + hw_sel - offset;
  622. }
  623. sw_sel += r->n_voltages;
  624. }
  625. return -EINVAL;
  626. }
  627. static const struct spmi_voltage_range *
  628. spmi_regulator_find_range(struct spmi_regulator *vreg)
  629. {
  630. u8 range_sel;
  631. const struct spmi_voltage_range *range, *end;
  632. range = vreg->set_points->range;
  633. end = range + vreg->set_points->count;
  634. spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1);
  635. for (; range < end; range++)
  636. if (range->range_sel == range_sel)
  637. return range;
  638. return NULL;
  639. }
  640. static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
  641. int min_uV, int max_uV)
  642. {
  643. const struct spmi_voltage_range *range;
  644. int uV = min_uV;
  645. int i, selector;
  646. range = spmi_regulator_find_range(vreg);
  647. if (!range)
  648. goto different_range;
  649. if (uV < range->min_uV && max_uV >= range->min_uV)
  650. uV = range->min_uV;
  651. if (uV < range->min_uV || uV > range->max_uV) {
  652. /* Current range doesn't support the requested voltage. */
  653. goto different_range;
  654. }
  655. /*
  656. * Force uV to be an allowed set point by applying a ceiling function to
  657. * the uV value.
  658. */
  659. uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
  660. uV = uV * range->step_uV + range->min_uV;
  661. if (uV > max_uV) {
  662. /*
  663. * No set point in the current voltage range is within the
  664. * requested min_uV to max_uV range.
  665. */
  666. goto different_range;
  667. }
  668. selector = 0;
  669. for (i = 0; i < vreg->set_points->count; i++) {
  670. if (uV >= vreg->set_points->range[i].set_point_min_uV
  671. && uV <= vreg->set_points->range[i].set_point_max_uV) {
  672. selector +=
  673. (uV - vreg->set_points->range[i].set_point_min_uV)
  674. / vreg->set_points->range[i].step_uV;
  675. break;
  676. }
  677. selector += vreg->set_points->range[i].n_voltages;
  678. }
  679. if (selector >= vreg->set_points->n_voltages)
  680. goto different_range;
  681. return selector;
  682. different_range:
  683. return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
  684. }
  685. static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev,
  686. int min_uV, int max_uV)
  687. {
  688. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  689. /*
  690. * Favor staying in the current voltage range if possible. This avoids
  691. * voltage spikes that occur when changing the voltage range.
  692. */
  693. return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV);
  694. }
  695. static int
  696. spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector)
  697. {
  698. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  699. int ret;
  700. u8 buf[2];
  701. u8 range_sel, voltage_sel;
  702. ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
  703. if (ret)
  704. return ret;
  705. buf[0] = range_sel;
  706. buf[1] = voltage_sel;
  707. return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2);
  708. }
  709. static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
  710. unsigned selector);
  711. static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev,
  712. unsigned selector)
  713. {
  714. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  715. u8 buf[2];
  716. int mV;
  717. mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000;
  718. buf[0] = mV & 0xff;
  719. buf[1] = mV >> 8;
  720. return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
  721. }
  722. static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
  723. unsigned int old_selector, unsigned int new_selector)
  724. {
  725. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  726. int diff_uV;
  727. diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) -
  728. spmi_regulator_common_list_voltage(rdev, old_selector));
  729. return DIV_ROUND_UP(diff_uV, vreg->slew_rate);
  730. }
  731. static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev)
  732. {
  733. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  734. const struct spmi_voltage_range *range;
  735. u8 voltage_sel;
  736. spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
  737. range = spmi_regulator_find_range(vreg);
  738. if (!range)
  739. return -EINVAL;
  740. return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
  741. }
  742. static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev)
  743. {
  744. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  745. const struct spmi_voltage_range *range;
  746. u8 buf[2];
  747. int uV;
  748. spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
  749. uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000;
  750. range = vreg->set_points->range;
  751. return (uV - range->set_point_min_uV) / range->step_uV;
  752. }
  753. static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev,
  754. int min_uV, int max_uV)
  755. {
  756. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  757. return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
  758. }
  759. static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev,
  760. unsigned selector)
  761. {
  762. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  763. u8 sel = selector;
  764. /*
  765. * Certain types of regulators do not have a range select register so
  766. * only voltage set register needs to be written.
  767. */
  768. return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1);
  769. }
  770. static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev)
  771. {
  772. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  773. u8 selector;
  774. int ret;
  775. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1);
  776. if (ret)
  777. return ret;
  778. return selector;
  779. }
  780. static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev,
  781. unsigned selector)
  782. {
  783. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  784. int ret;
  785. u8 range_sel, voltage_sel;
  786. ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
  787. if (ret)
  788. return ret;
  789. /*
  790. * Calculate VSET based on range
  791. * In case of range 0: voltage_sel is a 7 bit value, can be written
  792. * witout any modification.
  793. * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to
  794. * [011].
  795. */
  796. if (range_sel == 1)
  797. voltage_sel |= ULT_SMPS_RANGE_SPLIT;
  798. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET,
  799. voltage_sel, 0xff);
  800. }
  801. static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev)
  802. {
  803. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  804. const struct spmi_voltage_range *range;
  805. u8 voltage_sel;
  806. spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
  807. range = spmi_regulator_find_range(vreg);
  808. if (!range)
  809. return -EINVAL;
  810. if (range->range_sel == 1)
  811. voltage_sel &= ~ULT_SMPS_RANGE_SPLIT;
  812. return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
  813. }
  814. static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
  815. unsigned selector)
  816. {
  817. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  818. int uV = 0;
  819. int i;
  820. if (selector >= vreg->set_points->n_voltages)
  821. return 0;
  822. for (i = 0; i < vreg->set_points->count; i++) {
  823. if (selector < vreg->set_points->range[i].n_voltages) {
  824. uV = selector * vreg->set_points->range[i].step_uV
  825. + vreg->set_points->range[i].set_point_min_uV;
  826. break;
  827. }
  828. selector -= vreg->set_points->range[i].n_voltages;
  829. }
  830. return uV;
  831. }
  832. static int
  833. spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable)
  834. {
  835. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  836. u8 mask = SPMI_COMMON_MODE_BYPASS_MASK;
  837. u8 val = 0;
  838. if (enable)
  839. val = mask;
  840. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
  841. }
  842. static int
  843. spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable)
  844. {
  845. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  846. u8 val;
  847. int ret;
  848. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1);
  849. *enable = val & SPMI_COMMON_MODE_BYPASS_MASK;
  850. return ret;
  851. }
  852. static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
  853. {
  854. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  855. u8 reg;
  856. spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
  857. reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
  858. switch (reg) {
  859. case SPMI_COMMON_MODE_HPM_MASK:
  860. return REGULATOR_MODE_NORMAL;
  861. case SPMI_COMMON_MODE_AUTO_MASK:
  862. return REGULATOR_MODE_FAST;
  863. default:
  864. return REGULATOR_MODE_IDLE;
  865. }
  866. }
  867. static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev)
  868. {
  869. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  870. u8 reg;
  871. spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
  872. switch (reg) {
  873. case SPMI_FTSMPS426_MODE_HPM_MASK:
  874. return REGULATOR_MODE_NORMAL;
  875. case SPMI_FTSMPS426_MODE_AUTO_MASK:
  876. return REGULATOR_MODE_FAST;
  877. default:
  878. return REGULATOR_MODE_IDLE;
  879. }
  880. }
  881. static int
  882. spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
  883. {
  884. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  885. u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
  886. u8 val;
  887. switch (mode) {
  888. case REGULATOR_MODE_NORMAL:
  889. val = SPMI_COMMON_MODE_HPM_MASK;
  890. break;
  891. case REGULATOR_MODE_FAST:
  892. val = SPMI_COMMON_MODE_AUTO_MASK;
  893. break;
  894. default:
  895. val = 0;
  896. break;
  897. }
  898. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
  899. }
  900. static int
  901. spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode)
  902. {
  903. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  904. u8 mask = SPMI_FTSMPS426_MODE_MASK;
  905. u8 val;
  906. switch (mode) {
  907. case REGULATOR_MODE_NORMAL:
  908. val = SPMI_FTSMPS426_MODE_HPM_MASK;
  909. break;
  910. case REGULATOR_MODE_FAST:
  911. val = SPMI_FTSMPS426_MODE_AUTO_MASK;
  912. break;
  913. case REGULATOR_MODE_IDLE:
  914. val = SPMI_FTSMPS426_MODE_LPM_MASK;
  915. break;
  916. default:
  917. return -EINVAL;
  918. }
  919. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
  920. }
  921. static int
  922. spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA)
  923. {
  924. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  925. unsigned int mode;
  926. if (load_uA >= vreg->hpm_min_load)
  927. mode = REGULATOR_MODE_NORMAL;
  928. else
  929. mode = REGULATOR_MODE_IDLE;
  930. return spmi_regulator_common_set_mode(rdev, mode);
  931. }
  932. static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev)
  933. {
  934. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  935. unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
  936. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN,
  937. mask, mask);
  938. }
  939. static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev)
  940. {
  941. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  942. unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK;
  943. return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START,
  944. mask, mask);
  945. }
  946. static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA)
  947. {
  948. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  949. enum spmi_regulator_logical_type type = vreg->logical_type;
  950. unsigned int current_reg;
  951. u8 reg;
  952. u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK |
  953. SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
  954. int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500;
  955. if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST)
  956. current_reg = SPMI_BOOST_REG_CURRENT_LIMIT;
  957. else
  958. current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT;
  959. if (ilim_uA > max || ilim_uA <= 0)
  960. return -EINVAL;
  961. reg = (ilim_uA - 1) / 500;
  962. reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
  963. return spmi_vreg_update_bits(vreg, current_reg, reg, mask);
  964. }
  965. static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg)
  966. {
  967. int ret;
  968. ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
  969. SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
  970. vreg->vs_enable_time = ktime_get();
  971. ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
  972. SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
  973. return ret;
  974. }
  975. static void spmi_regulator_vs_ocp_work(struct work_struct *work)
  976. {
  977. struct delayed_work *dwork = to_delayed_work(work);
  978. struct spmi_regulator *vreg
  979. = container_of(dwork, struct spmi_regulator, ocp_work);
  980. spmi_regulator_vs_clear_ocp(vreg);
  981. }
  982. static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)
  983. {
  984. struct spmi_regulator *vreg = data;
  985. ktime_t ocp_irq_time;
  986. s64 ocp_trigger_delay_us;
  987. ocp_irq_time = ktime_get();
  988. ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time,
  989. vreg->vs_enable_time);
  990. /*
  991. * Reset the OCP count if there is a large delay between switch enable
  992. * and when OCP triggers. This is indicative of a hotplug event as
  993. * opposed to a fault.
  994. */
  995. if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US)
  996. vreg->ocp_count = 0;
  997. /* Wait for switch output to settle back to 0 V after OCP triggered. */
  998. udelay(SPMI_VS_OCP_FALL_DELAY_US);
  999. vreg->ocp_count++;
  1000. if (vreg->ocp_count == 1) {
  1001. /* Immediately clear the over current condition. */
  1002. spmi_regulator_vs_clear_ocp(vreg);
  1003. } else if (vreg->ocp_count <= vreg->ocp_max_retries) {
  1004. /* Schedule the over current clear task to run later. */
  1005. schedule_delayed_work(&vreg->ocp_work,
  1006. msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1);
  1007. } else {
  1008. dev_err(vreg->dev,
  1009. "OCP triggered %d times; no further retries\n",
  1010. vreg->ocp_count);
  1011. }
  1012. return IRQ_HANDLED;
  1013. }
  1014. #define SAW3_VCTL_DATA_MASK 0xFF
  1015. #define SAW3_VCTL_CLEAR_MASK 0x700FF
  1016. #define SAW3_AVS_CTL_EN_MASK 0x1
  1017. #define SAW3_AVS_CTL_TGGL_MASK 0x8000000
  1018. #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00
  1019. static struct regmap *saw_regmap;
  1020. static void spmi_saw_set_vdd(void *data)
  1021. {
  1022. u32 vctl, data3, avs_ctl, pmic_sts;
  1023. bool avs_enabled = false;
  1024. unsigned long timeout;
  1025. u8 voltage_sel = *(u8 *)data;
  1026. regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl);
  1027. regmap_read(saw_regmap, SAW3_VCTL, &vctl);
  1028. regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3);
  1029. /* select the band */
  1030. vctl &= ~SAW3_VCTL_CLEAR_MASK;
  1031. vctl |= (u32)voltage_sel;
  1032. data3 &= ~SAW3_VCTL_CLEAR_MASK;
  1033. data3 |= (u32)voltage_sel;
  1034. /* If AVS is enabled, switch it off during the voltage change */
  1035. avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl;
  1036. if (avs_enabled) {
  1037. avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK;
  1038. regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
  1039. }
  1040. regmap_write(saw_regmap, SAW3_RST, 1);
  1041. regmap_write(saw_regmap, SAW3_VCTL, vctl);
  1042. regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3);
  1043. timeout = jiffies + usecs_to_jiffies(100);
  1044. do {
  1045. regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts);
  1046. pmic_sts &= SAW3_VCTL_DATA_MASK;
  1047. if (pmic_sts == (u32)voltage_sel)
  1048. break;
  1049. cpu_relax();
  1050. } while (time_before(jiffies, timeout));
  1051. /* After successful voltage change, switch the AVS back on */
  1052. if (avs_enabled) {
  1053. pmic_sts &= 0x3f;
  1054. avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK;
  1055. avs_ctl |= ((pmic_sts - 4) << 10);
  1056. avs_ctl |= (pmic_sts << 17);
  1057. avs_ctl |= SAW3_AVS_CTL_TGGL_MASK;
  1058. regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
  1059. }
  1060. }
  1061. static int
  1062. spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector)
  1063. {
  1064. struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
  1065. int ret;
  1066. u8 range_sel, voltage_sel;
  1067. ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
  1068. if (ret)
  1069. return ret;
  1070. if (0 != range_sel) {
  1071. dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \
  1072. range_sel, voltage_sel);
  1073. return -EINVAL;
  1074. }
  1075. /* Always do the SAW register writes on the first CPU */
  1076. return smp_call_function_single(0, spmi_saw_set_vdd, \
  1077. &voltage_sel, true);
  1078. }
  1079. static struct regulator_ops spmi_saw_ops = {};
  1080. static const struct regulator_ops spmi_smps_ops = {
  1081. .enable = regulator_enable_regmap,
  1082. .disable = regulator_disable_regmap,
  1083. .is_enabled = regulator_is_enabled_regmap,
  1084. .set_voltage_sel = spmi_regulator_common_set_voltage,
  1085. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1086. .get_voltage_sel = spmi_regulator_common_get_voltage,
  1087. .map_voltage = spmi_regulator_common_map_voltage,
  1088. .list_voltage = spmi_regulator_common_list_voltage,
  1089. .set_mode = spmi_regulator_common_set_mode,
  1090. .get_mode = spmi_regulator_common_get_mode,
  1091. .set_load = spmi_regulator_common_set_load,
  1092. .set_pull_down = spmi_regulator_common_set_pull_down,
  1093. };
  1094. static const struct regulator_ops spmi_ldo_ops = {
  1095. .enable = regulator_enable_regmap,
  1096. .disable = regulator_disable_regmap,
  1097. .is_enabled = regulator_is_enabled_regmap,
  1098. .set_voltage_sel = spmi_regulator_common_set_voltage,
  1099. .get_voltage_sel = spmi_regulator_common_get_voltage,
  1100. .map_voltage = spmi_regulator_common_map_voltage,
  1101. .list_voltage = spmi_regulator_common_list_voltage,
  1102. .set_mode = spmi_regulator_common_set_mode,
  1103. .get_mode = spmi_regulator_common_get_mode,
  1104. .set_load = spmi_regulator_common_set_load,
  1105. .set_bypass = spmi_regulator_common_set_bypass,
  1106. .get_bypass = spmi_regulator_common_get_bypass,
  1107. .set_pull_down = spmi_regulator_common_set_pull_down,
  1108. .set_soft_start = spmi_regulator_common_set_soft_start,
  1109. };
  1110. static const struct regulator_ops spmi_ln_ldo_ops = {
  1111. .enable = regulator_enable_regmap,
  1112. .disable = regulator_disable_regmap,
  1113. .is_enabled = regulator_is_enabled_regmap,
  1114. .set_voltage_sel = spmi_regulator_common_set_voltage,
  1115. .get_voltage_sel = spmi_regulator_common_get_voltage,
  1116. .map_voltage = spmi_regulator_common_map_voltage,
  1117. .list_voltage = spmi_regulator_common_list_voltage,
  1118. .set_bypass = spmi_regulator_common_set_bypass,
  1119. .get_bypass = spmi_regulator_common_get_bypass,
  1120. };
  1121. static const struct regulator_ops spmi_vs_ops = {
  1122. .enable = spmi_regulator_vs_enable,
  1123. .disable = regulator_disable_regmap,
  1124. .is_enabled = regulator_is_enabled_regmap,
  1125. .set_pull_down = spmi_regulator_common_set_pull_down,
  1126. .set_soft_start = spmi_regulator_common_set_soft_start,
  1127. .set_over_current_protection = spmi_regulator_vs_ocp,
  1128. .set_mode = spmi_regulator_common_set_mode,
  1129. .get_mode = spmi_regulator_common_get_mode,
  1130. };
  1131. static const struct regulator_ops spmi_boost_ops = {
  1132. .enable = regulator_enable_regmap,
  1133. .disable = regulator_disable_regmap,
  1134. .is_enabled = regulator_is_enabled_regmap,
  1135. .set_voltage_sel = spmi_regulator_single_range_set_voltage,
  1136. .get_voltage_sel = spmi_regulator_single_range_get_voltage,
  1137. .map_voltage = spmi_regulator_single_map_voltage,
  1138. .list_voltage = spmi_regulator_common_list_voltage,
  1139. .set_input_current_limit = spmi_regulator_set_ilim,
  1140. };
  1141. static const struct regulator_ops spmi_ftsmps_ops = {
  1142. .enable = regulator_enable_regmap,
  1143. .disable = regulator_disable_regmap,
  1144. .is_enabled = regulator_is_enabled_regmap,
  1145. .set_voltage_sel = spmi_regulator_common_set_voltage,
  1146. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1147. .get_voltage_sel = spmi_regulator_common_get_voltage,
  1148. .map_voltage = spmi_regulator_common_map_voltage,
  1149. .list_voltage = spmi_regulator_common_list_voltage,
  1150. .set_mode = spmi_regulator_common_set_mode,
  1151. .get_mode = spmi_regulator_common_get_mode,
  1152. .set_load = spmi_regulator_common_set_load,
  1153. .set_pull_down = spmi_regulator_common_set_pull_down,
  1154. };
  1155. static const struct regulator_ops spmi_ult_lo_smps_ops = {
  1156. .enable = regulator_enable_regmap,
  1157. .disable = regulator_disable_regmap,
  1158. .is_enabled = regulator_is_enabled_regmap,
  1159. .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage,
  1160. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1161. .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage,
  1162. .list_voltage = spmi_regulator_common_list_voltage,
  1163. .set_mode = spmi_regulator_common_set_mode,
  1164. .get_mode = spmi_regulator_common_get_mode,
  1165. .set_load = spmi_regulator_common_set_load,
  1166. .set_pull_down = spmi_regulator_common_set_pull_down,
  1167. };
  1168. static const struct regulator_ops spmi_ult_ho_smps_ops = {
  1169. .enable = regulator_enable_regmap,
  1170. .disable = regulator_disable_regmap,
  1171. .is_enabled = regulator_is_enabled_regmap,
  1172. .set_voltage_sel = spmi_regulator_single_range_set_voltage,
  1173. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1174. .get_voltage_sel = spmi_regulator_single_range_get_voltage,
  1175. .map_voltage = spmi_regulator_single_map_voltage,
  1176. .list_voltage = spmi_regulator_common_list_voltage,
  1177. .set_mode = spmi_regulator_common_set_mode,
  1178. .get_mode = spmi_regulator_common_get_mode,
  1179. .set_load = spmi_regulator_common_set_load,
  1180. .set_pull_down = spmi_regulator_common_set_pull_down,
  1181. };
  1182. static const struct regulator_ops spmi_ult_ldo_ops = {
  1183. .enable = regulator_enable_regmap,
  1184. .disable = regulator_disable_regmap,
  1185. .is_enabled = regulator_is_enabled_regmap,
  1186. .set_voltage_sel = spmi_regulator_single_range_set_voltage,
  1187. .get_voltage_sel = spmi_regulator_single_range_get_voltage,
  1188. .map_voltage = spmi_regulator_single_map_voltage,
  1189. .list_voltage = spmi_regulator_common_list_voltage,
  1190. .set_mode = spmi_regulator_common_set_mode,
  1191. .get_mode = spmi_regulator_common_get_mode,
  1192. .set_load = spmi_regulator_common_set_load,
  1193. .set_bypass = spmi_regulator_common_set_bypass,
  1194. .get_bypass = spmi_regulator_common_get_bypass,
  1195. .set_pull_down = spmi_regulator_common_set_pull_down,
  1196. .set_soft_start = spmi_regulator_common_set_soft_start,
  1197. };
  1198. static const struct regulator_ops spmi_ftsmps426_ops = {
  1199. .enable = regulator_enable_regmap,
  1200. .disable = regulator_disable_regmap,
  1201. .is_enabled = regulator_is_enabled_regmap,
  1202. .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
  1203. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1204. .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
  1205. .map_voltage = spmi_regulator_single_map_voltage,
  1206. .list_voltage = spmi_regulator_common_list_voltage,
  1207. .set_mode = spmi_regulator_ftsmps426_set_mode,
  1208. .get_mode = spmi_regulator_ftsmps426_get_mode,
  1209. .set_load = spmi_regulator_common_set_load,
  1210. .set_pull_down = spmi_regulator_common_set_pull_down,
  1211. };
  1212. static const struct regulator_ops spmi_hfs430_ops = {
  1213. .enable = regulator_enable_regmap,
  1214. .disable = regulator_disable_regmap,
  1215. .is_enabled = regulator_is_enabled_regmap,
  1216. .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
  1217. .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
  1218. .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
  1219. .map_voltage = spmi_regulator_single_map_voltage,
  1220. .list_voltage = spmi_regulator_common_list_voltage,
  1221. .set_mode = spmi_regulator_ftsmps426_set_mode,
  1222. .get_mode = spmi_regulator_ftsmps426_get_mode,
  1223. };
  1224. /* Maximum possible digital major revision value */
  1225. #define INF 0xFF
  1226. static const struct spmi_regulator_mapping supported_regulators[] = {
  1227. /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
  1228. SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
  1229. SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
  1230. SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
  1231. SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
  1232. SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
  1233. SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000),
  1234. SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000),
  1235. SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
  1236. SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
  1237. SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000),
  1238. SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000),
  1239. SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
  1240. SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
  1241. SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
  1242. SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
  1243. SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
  1244. SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
  1245. SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
  1246. SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
  1247. SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
  1248. SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
  1249. SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
  1250. SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426,
  1251. ht_nldo, 30000),
  1252. SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426,
  1253. ht_nldo, 30000),
  1254. SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426,
  1255. ht_nldo, 30000),
  1256. SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426,
  1257. ht_lvpldo, 10000),
  1258. SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426,
  1259. ht_lvpldo, 10000),
  1260. SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
  1261. nldo660, 10000),
  1262. SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
  1263. nldo660, 10000),
  1264. SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426,
  1265. pldo660, 10000),
  1266. SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426,
  1267. pldo660, 10000),
  1268. SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426,
  1269. pldo660, 10000),
  1270. SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426,
  1271. ht_lvpldo, 10000),
  1272. SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426,
  1273. ht_lvpldo, 10000),
  1274. SPMI_VREG_VS(LV100, 0, INF),
  1275. SPMI_VREG_VS(LV300, 0, INF),
  1276. SPMI_VREG_VS(MV300, 0, INF),
  1277. SPMI_VREG_VS(MV500, 0, INF),
  1278. SPMI_VREG_VS(HDMI, 0, INF),
  1279. SPMI_VREG_VS(OTG, 0, INF),
  1280. SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
  1281. SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
  1282. SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
  1283. SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
  1284. SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
  1285. SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
  1286. ult_lo_smps, 100000),
  1287. SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
  1288. ult_lo_smps, 100000),
  1289. SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
  1290. ult_lo_smps, 100000),
  1291. SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
  1292. ult_ho_smps, 100000),
  1293. SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
  1294. SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
  1295. SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
  1296. SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
  1297. SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
  1298. SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
  1299. SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
  1300. SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
  1301. SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
  1302. SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
  1303. };
  1304. static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points)
  1305. {
  1306. unsigned int n;
  1307. struct spmi_voltage_range *range = points->range;
  1308. for (; range < points->range + points->count; range++) {
  1309. n = 0;
  1310. if (range->set_point_max_uV) {
  1311. n = range->set_point_max_uV - range->set_point_min_uV;
  1312. n = (n / range->step_uV) + 1;
  1313. }
  1314. range->n_voltages = n;
  1315. points->n_voltages += n;
  1316. }
  1317. }
  1318. static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type)
  1319. {
  1320. const struct spmi_regulator_mapping *mapping;
  1321. int ret, i;
  1322. u32 dig_major_rev;
  1323. u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1];
  1324. u8 type, subtype;
  1325. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version,
  1326. ARRAY_SIZE(version));
  1327. if (ret) {
  1328. dev_dbg(vreg->dev, "could not read version registers\n");
  1329. return ret;
  1330. }
  1331. dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV
  1332. - SPMI_COMMON_REG_DIG_MAJOR_REV];
  1333. if (!force_type) {
  1334. type = version[SPMI_COMMON_REG_TYPE -
  1335. SPMI_COMMON_REG_DIG_MAJOR_REV];
  1336. subtype = version[SPMI_COMMON_REG_SUBTYPE -
  1337. SPMI_COMMON_REG_DIG_MAJOR_REV];
  1338. } else {
  1339. type = force_type >> 8;
  1340. subtype = force_type;
  1341. }
  1342. for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) {
  1343. mapping = &supported_regulators[i];
  1344. if (mapping->type == type && mapping->subtype == subtype
  1345. && mapping->revision_min <= dig_major_rev
  1346. && mapping->revision_max >= dig_major_rev)
  1347. goto found;
  1348. }
  1349. dev_err(vreg->dev,
  1350. "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n",
  1351. vreg->desc.name, type, subtype, dig_major_rev);
  1352. return -ENODEV;
  1353. found:
  1354. vreg->logical_type = mapping->logical_type;
  1355. vreg->set_points = mapping->set_points;
  1356. vreg->hpm_min_load = mapping->hpm_min_load;
  1357. vreg->desc.ops = mapping->ops;
  1358. if (mapping->set_points) {
  1359. if (!mapping->set_points->n_voltages)
  1360. spmi_calculate_num_voltages(mapping->set_points);
  1361. vreg->desc.n_voltages = mapping->set_points->n_voltages;
  1362. }
  1363. return 0;
  1364. }
  1365. static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg)
  1366. {
  1367. int ret;
  1368. u8 reg = 0;
  1369. int step, delay, slew_rate, step_delay;
  1370. const struct spmi_voltage_range *range;
  1371. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
  1372. if (ret) {
  1373. dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
  1374. return ret;
  1375. }
  1376. range = spmi_regulator_find_range(vreg);
  1377. if (!range)
  1378. return -EINVAL;
  1379. switch (vreg->logical_type) {
  1380. case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
  1381. step_delay = SPMI_FTSMPS_STEP_DELAY;
  1382. break;
  1383. default:
  1384. step_delay = SPMI_DEFAULT_STEP_DELAY;
  1385. break;
  1386. }
  1387. step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK;
  1388. step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT;
  1389. delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK;
  1390. delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT;
  1391. /* slew_rate has units of uV/us */
  1392. slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step);
  1393. slew_rate /= 1000 * (step_delay << delay);
  1394. slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM;
  1395. slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN;
  1396. /* Ensure that the slew rate is greater than 0 */
  1397. vreg->slew_rate = max(slew_rate, 1);
  1398. return ret;
  1399. }
  1400. static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg,
  1401. int clock_rate)
  1402. {
  1403. int ret;
  1404. u8 reg = 0;
  1405. int delay, slew_rate;
  1406. const struct spmi_voltage_range *range = &vreg->set_points->range[0];
  1407. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
  1408. if (ret) {
  1409. dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
  1410. return ret;
  1411. }
  1412. delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
  1413. delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
  1414. /* slew_rate has units of uV/us */
  1415. slew_rate = clock_rate * range->step_uV;
  1416. slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay);
  1417. slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM;
  1418. slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN;
  1419. /* Ensure that the slew rate is greater than 0 */
  1420. vreg->slew_rate = max(slew_rate, 1);
  1421. return ret;
  1422. }
  1423. static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
  1424. const struct spmi_regulator_init_data *data)
  1425. {
  1426. int ret;
  1427. enum spmi_regulator_logical_type type;
  1428. u8 ctrl_reg[8], reg, mask;
  1429. type = vreg->logical_type;
  1430. ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
  1431. if (ret)
  1432. return ret;
  1433. /* Set up enable pin control. */
  1434. if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
  1435. switch (type) {
  1436. case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
  1437. case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
  1438. case SPMI_REGULATOR_LOGICAL_TYPE_VS:
  1439. ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
  1440. ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
  1441. ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
  1442. data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
  1443. break;
  1444. default:
  1445. break;
  1446. }
  1447. }
  1448. /* Set up mode pin control. */
  1449. if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
  1450. switch (type) {
  1451. case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
  1452. case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
  1453. ctrl_reg[SPMI_COMMON_IDX_MODE] &=
  1454. ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
  1455. ctrl_reg[SPMI_COMMON_IDX_MODE] |=
  1456. data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
  1457. break;
  1458. case SPMI_REGULATOR_LOGICAL_TYPE_VS:
  1459. case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
  1460. case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
  1461. case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO:
  1462. ctrl_reg[SPMI_COMMON_IDX_MODE] &=
  1463. ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
  1464. ctrl_reg[SPMI_COMMON_IDX_MODE] |=
  1465. data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
  1466. break;
  1467. default:
  1468. break;
  1469. }
  1470. }
  1471. /* Write back any control register values that were modified. */
  1472. ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
  1473. if (ret)
  1474. return ret;
  1475. /* Set soft start strength and over current protection for VS. */
  1476. if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
  1477. if (data->vs_soft_start_strength
  1478. != SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
  1479. reg = data->vs_soft_start_strength
  1480. & SPMI_VS_SOFT_START_SEL_MASK;
  1481. mask = SPMI_VS_SOFT_START_SEL_MASK;
  1482. return spmi_vreg_update_bits(vreg,
  1483. SPMI_VS_REG_SOFT_START,
  1484. reg, mask);
  1485. }
  1486. }
  1487. return 0;
  1488. }
  1489. static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
  1490. struct device_node *node, struct spmi_regulator_init_data *data)
  1491. {
  1492. /*
  1493. * Initialize configuration parameters to use hardware default in case
  1494. * no value is specified via device tree.
  1495. */
  1496. data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
  1497. data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
  1498. data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT;
  1499. /* These bindings are optional, so it is okay if they aren't found. */
  1500. of_property_read_u32(node, "qcom,ocp-max-retries",
  1501. &vreg->ocp_max_retries);
  1502. of_property_read_u32(node, "qcom,ocp-retry-delay",
  1503. &vreg->ocp_retry_delay_ms);
  1504. of_property_read_u32(node, "qcom,pin-ctrl-enable",
  1505. &data->pin_ctrl_enable);
  1506. of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
  1507. of_property_read_u32(node, "qcom,vs-soft-start-strength",
  1508. &data->vs_soft_start_strength);
  1509. }
  1510. static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
  1511. {
  1512. if (mode == 1)
  1513. return REGULATOR_MODE_NORMAL;
  1514. if (mode == 2)
  1515. return REGULATOR_MODE_FAST;
  1516. return REGULATOR_MODE_IDLE;
  1517. }
  1518. static int spmi_regulator_of_parse(struct device_node *node,
  1519. const struct regulator_desc *desc,
  1520. struct regulator_config *config)
  1521. {
  1522. struct spmi_regulator_init_data data = { };
  1523. struct spmi_regulator *vreg = config->driver_data;
  1524. struct device *dev = config->dev;
  1525. int ret;
  1526. spmi_regulator_get_dt_config(vreg, node, &data);
  1527. if (!vreg->ocp_max_retries)
  1528. vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
  1529. if (!vreg->ocp_retry_delay_ms)
  1530. vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
  1531. ret = spmi_regulator_init_registers(vreg, &data);
  1532. if (ret) {
  1533. dev_err(dev, "common initialization failed, ret=%d\n", ret);
  1534. return ret;
  1535. }
  1536. switch (vreg->logical_type) {
  1537. case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
  1538. case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
  1539. case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
  1540. case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
  1541. ret = spmi_regulator_init_slew_rate(vreg);
  1542. if (ret)
  1543. return ret;
  1544. break;
  1545. case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426:
  1546. ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
  1547. SPMI_FTSMPS426_CLOCK_RATE);
  1548. if (ret)
  1549. return ret;
  1550. break;
  1551. case SPMI_REGULATOR_LOGICAL_TYPE_HFS430:
  1552. ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
  1553. SPMI_HFS430_CLOCK_RATE);
  1554. if (ret)
  1555. return ret;
  1556. break;
  1557. default:
  1558. break;
  1559. }
  1560. if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS)
  1561. vreg->ocp_irq = 0;
  1562. if (vreg->ocp_irq) {
  1563. ret = devm_request_irq(dev, vreg->ocp_irq,
  1564. spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp",
  1565. vreg);
  1566. if (ret < 0) {
  1567. dev_err(dev, "failed to request irq %d, ret=%d\n",
  1568. vreg->ocp_irq, ret);
  1569. return ret;
  1570. }
  1571. INIT_DELAYED_WORK(&vreg->ocp_work, spmi_regulator_vs_ocp_work);
  1572. }
  1573. return 0;
  1574. }
  1575. static const struct spmi_regulator_data pm8941_regulators[] = {
  1576. { "s1", 0x1400, "vdd_s1", },
  1577. { "s2", 0x1700, "vdd_s2", },
  1578. { "s3", 0x1a00, "vdd_s3", },
  1579. { "s4", 0xa000, },
  1580. { "l1", 0x4000, "vdd_l1_l3", },
  1581. { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
  1582. { "l3", 0x4200, "vdd_l1_l3", },
  1583. { "l4", 0x4300, "vdd_l4_l11", },
  1584. { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
  1585. { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
  1586. { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
  1587. { "l8", 0x4700, "vdd_l8_l16_l18_19", },
  1588. { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
  1589. { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
  1590. { "l11", 0x4a00, "vdd_l4_l11", },
  1591. { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
  1592. { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
  1593. { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
  1594. { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
  1595. { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
  1596. { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
  1597. { "l18", 0x5100, "vdd_l8_l16_l18_19", },
  1598. { "l19", 0x5200, "vdd_l8_l16_l18_19", },
  1599. { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
  1600. { "l21", 0x5400, "vdd_l21", },
  1601. { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
  1602. { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
  1603. { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
  1604. { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
  1605. { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
  1606. { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
  1607. { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
  1608. { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
  1609. { }
  1610. };
  1611. static const struct spmi_regulator_data pm8841_regulators[] = {
  1612. { "s1", 0x1400, "vdd_s1", },
  1613. { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
  1614. { "s3", 0x1a00, "vdd_s3", },
  1615. { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
  1616. { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
  1617. { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
  1618. { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
  1619. { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
  1620. { }
  1621. };
  1622. static const struct spmi_regulator_data pm8916_regulators[] = {
  1623. { "s1", 0x1400, "vdd_s1", },
  1624. { "s2", 0x1700, "vdd_s2", },
  1625. { "s3", 0x1a00, "vdd_s3", },
  1626. { "s4", 0x1d00, "vdd_s4", },
  1627. { "l1", 0x4000, "vdd_l1_l3", },
  1628. { "l2", 0x4100, "vdd_l2", },
  1629. { "l3", 0x4200, "vdd_l1_l3", },
  1630. { "l4", 0x4300, "vdd_l4_l5_l6", },
  1631. { "l5", 0x4400, "vdd_l4_l5_l6", },
  1632. { "l6", 0x4500, "vdd_l4_l5_l6", },
  1633. { "l7", 0x4600, "vdd_l7", },
  1634. { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
  1635. { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
  1636. { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
  1637. { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
  1638. { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
  1639. { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
  1640. { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
  1641. { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
  1642. { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
  1643. { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
  1644. { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
  1645. { }
  1646. };
  1647. static const struct spmi_regulator_data pm8950_regulators[] = {
  1648. { "s1", 0x1400, "vdd_s1", },
  1649. { "s2", 0x1700, "vdd_s2", },
  1650. { "s3", 0x1a00, "vdd_s3", },
  1651. { "s4", 0x1d00, "vdd_s4", },
  1652. { "s5", 0x2000, "vdd_s5", },
  1653. { "s6", 0x2300, "vdd_s6", },
  1654. { "l1", 0x4000, "vdd_l1_l19", },
  1655. { "l2", 0x4100, "vdd_l2_l23", },
  1656. { "l3", 0x4200, "vdd_l3", },
  1657. { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
  1658. { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
  1659. { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
  1660. { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
  1661. { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
  1662. { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
  1663. { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
  1664. { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
  1665. { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
  1666. { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
  1667. { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
  1668. { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
  1669. { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
  1670. { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
  1671. { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
  1672. { "l19", 0x5200, "vdd_l1_l19", },
  1673. { "l20", 0x5300, "vdd_l20", },
  1674. { "l21", 0x5400, "vdd_l21", },
  1675. { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
  1676. { "l23", 0x5600, "vdd_l2_l23", },
  1677. { }
  1678. };
  1679. static const struct spmi_regulator_data pm8994_regulators[] = {
  1680. { "s1", 0x1400, "vdd_s1", },
  1681. { "s2", 0x1700, "vdd_s2", },
  1682. { "s3", 0x1a00, "vdd_s3", },
  1683. { "s4", 0x1d00, "vdd_s4", },
  1684. { "s5", 0x2000, "vdd_s5", },
  1685. { "s6", 0x2300, "vdd_s6", },
  1686. { "s7", 0x2600, "vdd_s7", },
  1687. { "s8", 0x2900, "vdd_s8", },
  1688. { "s9", 0x2c00, "vdd_s9", },
  1689. { "s10", 0x2f00, "vdd_s10", },
  1690. { "s11", 0x3200, "vdd_s11", },
  1691. { "s12", 0x3500, "vdd_s12", },
  1692. { "l1", 0x4000, "vdd_l1", },
  1693. { "l2", 0x4100, "vdd_l2_l26_l28", },
  1694. { "l3", 0x4200, "vdd_l3_l11", },
  1695. { "l4", 0x4300, "vdd_l4_l27_l31", },
  1696. { "l5", 0x4400, "vdd_l5_l7", },
  1697. { "l6", 0x4500, "vdd_l6_l12_l32", },
  1698. { "l7", 0x4600, "vdd_l5_l7", },
  1699. { "l8", 0x4700, "vdd_l8_l16_l30", },
  1700. { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
  1701. { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
  1702. { "l11", 0x4a00, "vdd_l3_l11", },
  1703. { "l12", 0x4b00, "vdd_l6_l12_l32", },
  1704. { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
  1705. { "l14", 0x4d00, "vdd_l14_l15", },
  1706. { "l15", 0x4e00, "vdd_l14_l15", },
  1707. { "l16", 0x4f00, "vdd_l8_l16_l30", },
  1708. { "l17", 0x5000, "vdd_l17_l29", },
  1709. { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
  1710. { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
  1711. { "l20", 0x5300, "vdd_l20_l21", },
  1712. { "l21", 0x5400, "vdd_l20_l21", },
  1713. { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
  1714. { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
  1715. { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
  1716. { "l25", 0x5800, "vdd_l25", },
  1717. { "l26", 0x5900, "vdd_l2_l26_l28", },
  1718. { "l27", 0x5a00, "vdd_l4_l27_l31", },
  1719. { "l28", 0x5b00, "vdd_l2_l26_l28", },
  1720. { "l29", 0x5c00, "vdd_l17_l29", },
  1721. { "l30", 0x5d00, "vdd_l8_l16_l30", },
  1722. { "l31", 0x5e00, "vdd_l4_l27_l31", },
  1723. { "l32", 0x5f00, "vdd_l6_l12_l32", },
  1724. { "lvs1", 0x8000, "vdd_lvs_1_2", },
  1725. { "lvs2", 0x8100, "vdd_lvs_1_2", },
  1726. { }
  1727. };
  1728. static const struct spmi_regulator_data pmi8994_regulators[] = {
  1729. { "s1", 0x1400, "vdd_s1", },
  1730. { "s2", 0x1700, "vdd_s2", },
  1731. { "s3", 0x1a00, "vdd_s3", },
  1732. { "l1", 0x4000, "vdd_l1", },
  1733. { }
  1734. };
  1735. static const struct spmi_regulator_data pm660_regulators[] = {
  1736. { "s1", 0x1400, "vdd_s1", },
  1737. { "s2", 0x1700, "vdd_s2", },
  1738. { "s3", 0x1a00, "vdd_s3", },
  1739. { "s4", 0x1d00, "vdd_s3", },
  1740. { "s5", 0x2000, "vdd_s5", },
  1741. { "s6", 0x2300, "vdd_s6", },
  1742. { "l1", 0x4000, "vdd_l1_l6_l7", },
  1743. { "l2", 0x4100, "vdd_l2_l3", },
  1744. { "l3", 0x4200, "vdd_l2_l3", },
  1745. /* l4 is unaccessible on PM660 */
  1746. { "l5", 0x4400, "vdd_l5", },
  1747. { "l6", 0x4500, "vdd_l1_l6_l7", },
  1748. { "l7", 0x4600, "vdd_l1_l6_l7", },
  1749. { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1750. { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1751. { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1752. { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1753. { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1754. { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1755. { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
  1756. { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
  1757. { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
  1758. { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
  1759. { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
  1760. { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
  1761. { }
  1762. };
  1763. static const struct spmi_regulator_data pm660l_regulators[] = {
  1764. { "s1", 0x1400, "vdd_s1", },
  1765. { "s2", 0x1700, "vdd_s2", },
  1766. { "s3", 0x1a00, "vdd_s3", },
  1767. { "s4", 0x1d00, "vdd_s4", },
  1768. { "s5", 0x2000, "vdd_s5", },
  1769. { "l1", 0x4000, "vdd_l1_l9_l10", },
  1770. { "l2", 0x4100, "vdd_l2", },
  1771. { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
  1772. { "l4", 0x4300, "vdd_l4_l6", },
  1773. { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
  1774. { "l6", 0x4500, "vdd_l4_l6", },
  1775. { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
  1776. { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
  1777. { "l9", 0x4800, "vdd_l1_l9_l10", },
  1778. { "l10", 0x4900, "vdd_l1_l9_l10", },
  1779. { }
  1780. };
  1781. static const struct spmi_regulator_data pm8004_regulators[] = {
  1782. { "s2", 0x1700, "vdd_s2", },
  1783. { "s5", 0x2000, "vdd_s5", },
  1784. { }
  1785. };
  1786. static const struct spmi_regulator_data pm8005_regulators[] = {
  1787. { "s1", 0x1400, "vdd_s1", },
  1788. { "s2", 0x1700, "vdd_s2", },
  1789. { "s3", 0x1a00, "vdd_s3", },
  1790. { "s4", 0x1d00, "vdd_s4", },
  1791. { }
  1792. };
  1793. static const struct spmi_regulator_data pms405_regulators[] = {
  1794. { "s3", 0x1a00, "vdd_s3"},
  1795. { }
  1796. };
  1797. static const struct of_device_id qcom_spmi_regulator_match[] = {
  1798. { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
  1799. { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
  1800. { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators },
  1801. { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators },
  1802. { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators },
  1803. { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators },
  1804. { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
  1805. { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
  1806. { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
  1807. { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
  1808. { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
  1809. { }
  1810. };
  1811. MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);
  1812. static int qcom_spmi_regulator_probe(struct platform_device *pdev)
  1813. {
  1814. const struct spmi_regulator_data *reg;
  1815. const struct spmi_voltage_range *range;
  1816. const struct of_device_id *match;
  1817. struct regulator_config config = { };
  1818. struct regulator_dev *rdev;
  1819. struct spmi_regulator *vreg;
  1820. struct regmap *regmap;
  1821. const char *name;
  1822. struct device *dev = &pdev->dev;
  1823. struct device_node *node = pdev->dev.of_node;
  1824. struct device_node *syscon, *reg_node;
  1825. struct property *reg_prop;
  1826. int ret, lenp;
  1827. struct list_head *vreg_list;
  1828. vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL);
  1829. if (!vreg_list)
  1830. return -ENOMEM;
  1831. INIT_LIST_HEAD(vreg_list);
  1832. platform_set_drvdata(pdev, vreg_list);
  1833. regmap = dev_get_regmap(dev->parent, NULL);
  1834. if (!regmap)
  1835. return -ENODEV;
  1836. match = of_match_device(qcom_spmi_regulator_match, &pdev->dev);
  1837. if (!match)
  1838. return -ENODEV;
  1839. if (of_find_property(node, "qcom,saw-reg", &lenp)) {
  1840. syscon = of_parse_phandle(node, "qcom,saw-reg", 0);
  1841. saw_regmap = syscon_node_to_regmap(syscon);
  1842. of_node_put(syscon);
  1843. if (IS_ERR(saw_regmap))
  1844. dev_err(dev, "ERROR reading SAW regmap\n");
  1845. }
  1846. for (reg = match->data; reg->name; reg++) {
  1847. if (saw_regmap) {
  1848. reg_node = of_get_child_by_name(node, reg->name);
  1849. reg_prop = of_find_property(reg_node, "qcom,saw-slave",
  1850. &lenp);
  1851. of_node_put(reg_node);
  1852. if (reg_prop)
  1853. continue;
  1854. }
  1855. vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
  1856. if (!vreg)
  1857. return -ENOMEM;
  1858. vreg->dev = dev;
  1859. vreg->base = reg->base;
  1860. vreg->regmap = regmap;
  1861. if (reg->ocp) {
  1862. vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp);
  1863. if (vreg->ocp_irq < 0) {
  1864. ret = vreg->ocp_irq;
  1865. goto err;
  1866. }
  1867. }
  1868. vreg->desc.id = -1;
  1869. vreg->desc.owner = THIS_MODULE;
  1870. vreg->desc.type = REGULATOR_VOLTAGE;
  1871. vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE;
  1872. vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK;
  1873. vreg->desc.enable_val = SPMI_COMMON_ENABLE;
  1874. vreg->desc.name = name = reg->name;
  1875. vreg->desc.supply_name = reg->supply;
  1876. vreg->desc.of_match = reg->name;
  1877. vreg->desc.of_parse_cb = spmi_regulator_of_parse;
  1878. vreg->desc.of_map_mode = spmi_regulator_of_map_mode;
  1879. ret = spmi_regulator_match(vreg, reg->force_type);
  1880. if (ret)
  1881. continue;
  1882. if (saw_regmap) {
  1883. reg_node = of_get_child_by_name(node, reg->name);
  1884. reg_prop = of_find_property(reg_node, "qcom,saw-leader",
  1885. &lenp);
  1886. of_node_put(reg_node);
  1887. if (reg_prop) {
  1888. spmi_saw_ops = *(vreg->desc.ops);
  1889. spmi_saw_ops.set_voltage_sel =
  1890. spmi_regulator_saw_set_voltage;
  1891. vreg->desc.ops = &spmi_saw_ops;
  1892. }
  1893. }
  1894. if (vreg->set_points && vreg->set_points->count == 1) {
  1895. /* since there is only one range */
  1896. range = vreg->set_points->range;
  1897. vreg->desc.uV_step = range->step_uV;
  1898. }
  1899. config.dev = dev;
  1900. config.driver_data = vreg;
  1901. config.regmap = regmap;
  1902. rdev = devm_regulator_register(dev, &vreg->desc, &config);
  1903. if (IS_ERR(rdev)) {
  1904. dev_err(dev, "failed to register %s\n", name);
  1905. ret = PTR_ERR(rdev);
  1906. goto err;
  1907. }
  1908. INIT_LIST_HEAD(&vreg->node);
  1909. list_add(&vreg->node, vreg_list);
  1910. }
  1911. return 0;
  1912. err:
  1913. list_for_each_entry(vreg, vreg_list, node)
  1914. if (vreg->ocp_irq)
  1915. cancel_delayed_work_sync(&vreg->ocp_work);
  1916. return ret;
  1917. }
  1918. static int qcom_spmi_regulator_remove(struct platform_device *pdev)
  1919. {
  1920. struct spmi_regulator *vreg;
  1921. struct list_head *vreg_list = platform_get_drvdata(pdev);
  1922. list_for_each_entry(vreg, vreg_list, node)
  1923. if (vreg->ocp_irq)
  1924. cancel_delayed_work_sync(&vreg->ocp_work);
  1925. return 0;
  1926. }
  1927. static struct platform_driver qcom_spmi_regulator_driver = {
  1928. .driver = {
  1929. .name = "qcom-spmi-regulator",
  1930. .of_match_table = qcom_spmi_regulator_match,
  1931. },
  1932. .probe = qcom_spmi_regulator_probe,
  1933. .remove = qcom_spmi_regulator_remove,
  1934. };
  1935. module_platform_driver(qcom_spmi_regulator_driver);
  1936. MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver");
  1937. MODULE_LICENSE("GPL v2");
  1938. MODULE_ALIAS("platform:qcom-spmi-regulator");