ab8500.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
  6. * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
  7. * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
  8. *
  9. * AB8500 peripheral regulators
  10. *
  11. * AB8500 supports the following regulators:
  12. * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
  13. *
  14. * AB8505 supports the following regulators:
  15. * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/err.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/mfd/abx500.h>
  23. #include <linux/mfd/abx500/ab8500.h>
  24. #include <linux/of.h>
  25. #include <linux/regulator/of_regulator.h>
  26. #include <linux/regulator/driver.h>
  27. #include <linux/regulator/machine.h>
  28. #include <linux/regulator/ab8500.h>
  29. #include <linux/slab.h>
  30. /**
  31. * struct ab8500_shared_mode - is used when mode is shared between
  32. * two regulators.
  33. * @shared_regulator: pointer to the other sharing regulator
  34. * @lp_mode_req: low power mode requested by this regulator
  35. */
  36. struct ab8500_shared_mode {
  37. struct ab8500_regulator_info *shared_regulator;
  38. bool lp_mode_req;
  39. };
  40. /**
  41. * struct ab8500_regulator_info - ab8500 regulator information
  42. * @dev: device pointer
  43. * @desc: regulator description
  44. * @shared_mode: used when mode is shared between two regulators
  45. * @load_lp_uA: maximum load in idle (low power) mode
  46. * @update_bank: bank to control on/off
  47. * @update_reg: register to control on/off
  48. * @update_mask: mask to enable/disable and set mode of regulator
  49. * @update_val: bits holding the regulator current mode
  50. * @update_val_idle: bits to enable the regulator in idle (low power) mode
  51. * @update_val_normal: bits to enable the regulator in normal (high power) mode
  52. * @mode_bank: bank with location of mode register
  53. * @mode_reg: mode register
  54. * @mode_mask: mask for setting mode
  55. * @mode_val_idle: mode setting for low power
  56. * @mode_val_normal: mode setting for normal power
  57. * @voltage_bank: bank to control regulator voltage
  58. * @voltage_reg: register to control regulator voltage
  59. * @voltage_mask: mask to control regulator voltage
  60. * @expand_register:
  61. */
  62. struct ab8500_regulator_info {
  63. struct device *dev;
  64. struct regulator_desc desc;
  65. struct ab8500_shared_mode *shared_mode;
  66. int load_lp_uA;
  67. u8 update_bank;
  68. u8 update_reg;
  69. u8 update_mask;
  70. u8 update_val;
  71. u8 update_val_idle;
  72. u8 update_val_normal;
  73. u8 mode_bank;
  74. u8 mode_reg;
  75. u8 mode_mask;
  76. u8 mode_val_idle;
  77. u8 mode_val_normal;
  78. u8 voltage_bank;
  79. u8 voltage_reg;
  80. u8 voltage_mask;
  81. };
  82. /* voltage tables for the vauxn/vintcore supplies */
  83. static const unsigned int ldo_vauxn_voltages[] = {
  84. 1100000,
  85. 1200000,
  86. 1300000,
  87. 1400000,
  88. 1500000,
  89. 1800000,
  90. 1850000,
  91. 1900000,
  92. 2500000,
  93. 2650000,
  94. 2700000,
  95. 2750000,
  96. 2800000,
  97. 2900000,
  98. 3000000,
  99. 3300000,
  100. };
  101. static const unsigned int ldo_vaux3_voltages[] = {
  102. 1200000,
  103. 1500000,
  104. 1800000,
  105. 2100000,
  106. 2500000,
  107. 2750000,
  108. 2790000,
  109. 2910000,
  110. };
  111. static const unsigned int ldo_vaux56_voltages[] = {
  112. 1800000,
  113. 1050000,
  114. 1100000,
  115. 1200000,
  116. 1500000,
  117. 2200000,
  118. 2500000,
  119. 2790000,
  120. };
  121. static const unsigned int ldo_vintcore_voltages[] = {
  122. 1200000,
  123. 1225000,
  124. 1250000,
  125. 1275000,
  126. 1300000,
  127. 1325000,
  128. 1350000,
  129. };
  130. static const unsigned int fixed_1200000_voltage[] = {
  131. 1200000,
  132. };
  133. static const unsigned int fixed_1800000_voltage[] = {
  134. 1800000,
  135. };
  136. static const unsigned int fixed_2000000_voltage[] = {
  137. 2000000,
  138. };
  139. static const unsigned int fixed_2050000_voltage[] = {
  140. 2050000,
  141. };
  142. static const unsigned int ldo_vana_voltages[] = {
  143. 1050000,
  144. 1075000,
  145. 1100000,
  146. 1125000,
  147. 1150000,
  148. 1175000,
  149. 1200000,
  150. 1225000,
  151. };
  152. static const unsigned int ldo_vaudio_voltages[] = {
  153. 2000000,
  154. 2100000,
  155. 2200000,
  156. 2300000,
  157. 2400000,
  158. 2500000,
  159. 2600000,
  160. 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
  161. };
  162. static DEFINE_MUTEX(shared_mode_mutex);
  163. static struct ab8500_shared_mode ldo_anamic1_shared;
  164. static struct ab8500_shared_mode ldo_anamic2_shared;
  165. static int ab8500_regulator_enable(struct regulator_dev *rdev)
  166. {
  167. int ret;
  168. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  169. if (info == NULL) {
  170. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  171. return -EINVAL;
  172. }
  173. ret = abx500_mask_and_set_register_interruptible(info->dev,
  174. info->update_bank, info->update_reg,
  175. info->update_mask, info->update_val);
  176. if (ret < 0) {
  177. dev_err(rdev_get_dev(rdev),
  178. "couldn't set enable bits for regulator\n");
  179. return ret;
  180. }
  181. dev_vdbg(rdev_get_dev(rdev),
  182. "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
  183. info->desc.name, info->update_bank, info->update_reg,
  184. info->update_mask, info->update_val);
  185. return ret;
  186. }
  187. static int ab8500_regulator_disable(struct regulator_dev *rdev)
  188. {
  189. int ret;
  190. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  191. if (info == NULL) {
  192. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  193. return -EINVAL;
  194. }
  195. ret = abx500_mask_and_set_register_interruptible(info->dev,
  196. info->update_bank, info->update_reg,
  197. info->update_mask, 0x0);
  198. if (ret < 0) {
  199. dev_err(rdev_get_dev(rdev),
  200. "couldn't set disable bits for regulator\n");
  201. return ret;
  202. }
  203. dev_vdbg(rdev_get_dev(rdev),
  204. "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
  205. info->desc.name, info->update_bank, info->update_reg,
  206. info->update_mask, 0x0);
  207. return ret;
  208. }
  209. static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
  210. {
  211. int ret;
  212. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  213. u8 regval;
  214. if (info == NULL) {
  215. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  216. return -EINVAL;
  217. }
  218. ret = abx500_get_register_interruptible(info->dev,
  219. info->update_bank, info->update_reg, &regval);
  220. if (ret < 0) {
  221. dev_err(rdev_get_dev(rdev),
  222. "couldn't read 0x%x register\n", info->update_reg);
  223. return ret;
  224. }
  225. dev_vdbg(rdev_get_dev(rdev),
  226. "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
  227. " 0x%x\n",
  228. info->desc.name, info->update_bank, info->update_reg,
  229. info->update_mask, regval);
  230. if (regval & info->update_mask)
  231. return 1;
  232. else
  233. return 0;
  234. }
  235. static unsigned int ab8500_regulator_get_optimum_mode(
  236. struct regulator_dev *rdev, int input_uV,
  237. int output_uV, int load_uA)
  238. {
  239. unsigned int mode;
  240. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  241. if (info == NULL) {
  242. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  243. return -EINVAL;
  244. }
  245. if (load_uA <= info->load_lp_uA)
  246. mode = REGULATOR_MODE_IDLE;
  247. else
  248. mode = REGULATOR_MODE_NORMAL;
  249. return mode;
  250. }
  251. static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
  252. unsigned int mode)
  253. {
  254. int ret = 0;
  255. u8 bank, reg, mask, val;
  256. bool lp_mode_req = false;
  257. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  258. if (info == NULL) {
  259. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  260. return -EINVAL;
  261. }
  262. if (info->mode_mask) {
  263. bank = info->mode_bank;
  264. reg = info->mode_reg;
  265. mask = info->mode_mask;
  266. } else {
  267. bank = info->update_bank;
  268. reg = info->update_reg;
  269. mask = info->update_mask;
  270. }
  271. if (info->shared_mode)
  272. mutex_lock(&shared_mode_mutex);
  273. switch (mode) {
  274. case REGULATOR_MODE_NORMAL:
  275. if (info->shared_mode)
  276. lp_mode_req = false;
  277. if (info->mode_mask)
  278. val = info->mode_val_normal;
  279. else
  280. val = info->update_val_normal;
  281. break;
  282. case REGULATOR_MODE_IDLE:
  283. if (info->shared_mode) {
  284. struct ab8500_regulator_info *shared_regulator;
  285. shared_regulator = info->shared_mode->shared_regulator;
  286. if (!shared_regulator->shared_mode->lp_mode_req) {
  287. /* Other regulator prevent LP mode */
  288. info->shared_mode->lp_mode_req = true;
  289. goto out_unlock;
  290. }
  291. lp_mode_req = true;
  292. }
  293. if (info->mode_mask)
  294. val = info->mode_val_idle;
  295. else
  296. val = info->update_val_idle;
  297. break;
  298. default:
  299. ret = -EINVAL;
  300. goto out_unlock;
  301. }
  302. if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
  303. ret = abx500_mask_and_set_register_interruptible(info->dev,
  304. bank, reg, mask, val);
  305. if (ret < 0) {
  306. dev_err(rdev_get_dev(rdev),
  307. "couldn't set regulator mode\n");
  308. goto out_unlock;
  309. }
  310. dev_vdbg(rdev_get_dev(rdev),
  311. "%s-set_mode (bank, reg, mask, value): "
  312. "0x%x, 0x%x, 0x%x, 0x%x\n",
  313. info->desc.name, bank, reg,
  314. mask, val);
  315. }
  316. if (!info->mode_mask)
  317. info->update_val = val;
  318. if (info->shared_mode)
  319. info->shared_mode->lp_mode_req = lp_mode_req;
  320. out_unlock:
  321. if (info->shared_mode)
  322. mutex_unlock(&shared_mode_mutex);
  323. return ret;
  324. }
  325. static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
  326. {
  327. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  328. int ret;
  329. u8 val;
  330. u8 val_normal;
  331. u8 val_idle;
  332. if (info == NULL) {
  333. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  334. return -EINVAL;
  335. }
  336. /* Need special handling for shared mode */
  337. if (info->shared_mode) {
  338. if (info->shared_mode->lp_mode_req)
  339. return REGULATOR_MODE_IDLE;
  340. else
  341. return REGULATOR_MODE_NORMAL;
  342. }
  343. if (info->mode_mask) {
  344. /* Dedicated register for handling mode */
  345. ret = abx500_get_register_interruptible(info->dev,
  346. info->mode_bank, info->mode_reg, &val);
  347. val = val & info->mode_mask;
  348. val_normal = info->mode_val_normal;
  349. val_idle = info->mode_val_idle;
  350. } else {
  351. /* Mode register same as enable register */
  352. val = info->update_val;
  353. val_normal = info->update_val_normal;
  354. val_idle = info->update_val_idle;
  355. }
  356. if (val == val_normal)
  357. ret = REGULATOR_MODE_NORMAL;
  358. else if (val == val_idle)
  359. ret = REGULATOR_MODE_IDLE;
  360. else
  361. ret = -EINVAL;
  362. return ret;
  363. }
  364. static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
  365. {
  366. int ret, voltage_shift;
  367. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  368. u8 regval;
  369. if (info == NULL) {
  370. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  371. return -EINVAL;
  372. }
  373. voltage_shift = ffs(info->voltage_mask) - 1;
  374. ret = abx500_get_register_interruptible(info->dev,
  375. info->voltage_bank, info->voltage_reg, &regval);
  376. if (ret < 0) {
  377. dev_err(rdev_get_dev(rdev),
  378. "couldn't read voltage reg for regulator\n");
  379. return ret;
  380. }
  381. dev_vdbg(rdev_get_dev(rdev),
  382. "%s-get_voltage (bank, reg, mask, shift, value): "
  383. "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
  384. info->desc.name, info->voltage_bank,
  385. info->voltage_reg, info->voltage_mask,
  386. voltage_shift, regval);
  387. return (regval & info->voltage_mask) >> voltage_shift;
  388. }
  389. static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
  390. unsigned selector)
  391. {
  392. int ret, voltage_shift;
  393. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  394. u8 regval;
  395. if (info == NULL) {
  396. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  397. return -EINVAL;
  398. }
  399. voltage_shift = ffs(info->voltage_mask) - 1;
  400. /* set the registers for the request */
  401. regval = (u8)selector << voltage_shift;
  402. ret = abx500_mask_and_set_register_interruptible(info->dev,
  403. info->voltage_bank, info->voltage_reg,
  404. info->voltage_mask, regval);
  405. if (ret < 0)
  406. dev_err(rdev_get_dev(rdev),
  407. "couldn't set voltage reg for regulator\n");
  408. dev_vdbg(rdev_get_dev(rdev),
  409. "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
  410. " 0x%x\n",
  411. info->desc.name, info->voltage_bank, info->voltage_reg,
  412. info->voltage_mask, regval);
  413. return ret;
  414. }
  415. static const struct regulator_ops ab8500_regulator_volt_mode_ops = {
  416. .enable = ab8500_regulator_enable,
  417. .disable = ab8500_regulator_disable,
  418. .is_enabled = ab8500_regulator_is_enabled,
  419. .get_optimum_mode = ab8500_regulator_get_optimum_mode,
  420. .set_mode = ab8500_regulator_set_mode,
  421. .get_mode = ab8500_regulator_get_mode,
  422. .get_voltage_sel = ab8500_regulator_get_voltage_sel,
  423. .set_voltage_sel = ab8500_regulator_set_voltage_sel,
  424. .list_voltage = regulator_list_voltage_table,
  425. };
  426. static const struct regulator_ops ab8500_regulator_volt_ops = {
  427. .enable = ab8500_regulator_enable,
  428. .disable = ab8500_regulator_disable,
  429. .is_enabled = ab8500_regulator_is_enabled,
  430. .get_voltage_sel = ab8500_regulator_get_voltage_sel,
  431. .set_voltage_sel = ab8500_regulator_set_voltage_sel,
  432. .list_voltage = regulator_list_voltage_table,
  433. };
  434. static const struct regulator_ops ab8500_regulator_mode_ops = {
  435. .enable = ab8500_regulator_enable,
  436. .disable = ab8500_regulator_disable,
  437. .is_enabled = ab8500_regulator_is_enabled,
  438. .get_optimum_mode = ab8500_regulator_get_optimum_mode,
  439. .set_mode = ab8500_regulator_set_mode,
  440. .get_mode = ab8500_regulator_get_mode,
  441. .list_voltage = regulator_list_voltage_table,
  442. };
  443. static const struct regulator_ops ab8500_regulator_ops = {
  444. .enable = ab8500_regulator_enable,
  445. .disable = ab8500_regulator_disable,
  446. .is_enabled = ab8500_regulator_is_enabled,
  447. .list_voltage = regulator_list_voltage_table,
  448. };
  449. static const struct regulator_ops ab8500_regulator_anamic_mode_ops = {
  450. .enable = ab8500_regulator_enable,
  451. .disable = ab8500_regulator_disable,
  452. .is_enabled = ab8500_regulator_is_enabled,
  453. .set_mode = ab8500_regulator_set_mode,
  454. .get_mode = ab8500_regulator_get_mode,
  455. .list_voltage = regulator_list_voltage_table,
  456. };
  457. /* AB8500 regulator information */
  458. static struct ab8500_regulator_info
  459. ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
  460. /*
  461. * Variable Voltage Regulators
  462. * name, min mV, max mV,
  463. * update bank, reg, mask, enable val
  464. * volt bank, reg, mask
  465. */
  466. [AB8500_LDO_AUX1] = {
  467. .desc = {
  468. .name = "LDO-AUX1",
  469. .ops = &ab8500_regulator_volt_mode_ops,
  470. .type = REGULATOR_VOLTAGE,
  471. .id = AB8500_LDO_AUX1,
  472. .owner = THIS_MODULE,
  473. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  474. .volt_table = ldo_vauxn_voltages,
  475. .enable_time = 200,
  476. .supply_name = "vin",
  477. },
  478. .load_lp_uA = 5000,
  479. .update_bank = 0x04,
  480. .update_reg = 0x09,
  481. .update_mask = 0x03,
  482. .update_val = 0x01,
  483. .update_val_idle = 0x03,
  484. .update_val_normal = 0x01,
  485. .voltage_bank = 0x04,
  486. .voltage_reg = 0x1f,
  487. .voltage_mask = 0x0f,
  488. },
  489. [AB8500_LDO_AUX2] = {
  490. .desc = {
  491. .name = "LDO-AUX2",
  492. .ops = &ab8500_regulator_volt_mode_ops,
  493. .type = REGULATOR_VOLTAGE,
  494. .id = AB8500_LDO_AUX2,
  495. .owner = THIS_MODULE,
  496. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  497. .volt_table = ldo_vauxn_voltages,
  498. .enable_time = 200,
  499. .supply_name = "vin",
  500. },
  501. .load_lp_uA = 5000,
  502. .update_bank = 0x04,
  503. .update_reg = 0x09,
  504. .update_mask = 0x0c,
  505. .update_val = 0x04,
  506. .update_val_idle = 0x0c,
  507. .update_val_normal = 0x04,
  508. .voltage_bank = 0x04,
  509. .voltage_reg = 0x20,
  510. .voltage_mask = 0x0f,
  511. },
  512. [AB8500_LDO_AUX3] = {
  513. .desc = {
  514. .name = "LDO-AUX3",
  515. .ops = &ab8500_regulator_volt_mode_ops,
  516. .type = REGULATOR_VOLTAGE,
  517. .id = AB8500_LDO_AUX3,
  518. .owner = THIS_MODULE,
  519. .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
  520. .volt_table = ldo_vaux3_voltages,
  521. .enable_time = 450,
  522. .supply_name = "vin",
  523. },
  524. .load_lp_uA = 5000,
  525. .update_bank = 0x04,
  526. .update_reg = 0x0a,
  527. .update_mask = 0x03,
  528. .update_val = 0x01,
  529. .update_val_idle = 0x03,
  530. .update_val_normal = 0x01,
  531. .voltage_bank = 0x04,
  532. .voltage_reg = 0x21,
  533. .voltage_mask = 0x07,
  534. },
  535. [AB8500_LDO_INTCORE] = {
  536. .desc = {
  537. .name = "LDO-INTCORE",
  538. .ops = &ab8500_regulator_volt_mode_ops,
  539. .type = REGULATOR_VOLTAGE,
  540. .id = AB8500_LDO_INTCORE,
  541. .owner = THIS_MODULE,
  542. .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
  543. .volt_table = ldo_vintcore_voltages,
  544. .enable_time = 750,
  545. },
  546. .load_lp_uA = 5000,
  547. .update_bank = 0x03,
  548. .update_reg = 0x80,
  549. .update_mask = 0x44,
  550. .update_val = 0x44,
  551. .update_val_idle = 0x44,
  552. .update_val_normal = 0x04,
  553. .voltage_bank = 0x03,
  554. .voltage_reg = 0x80,
  555. .voltage_mask = 0x38,
  556. },
  557. /*
  558. * Fixed Voltage Regulators
  559. * name, fixed mV,
  560. * update bank, reg, mask, enable val
  561. */
  562. [AB8500_LDO_TVOUT] = {
  563. .desc = {
  564. .name = "LDO-TVOUT",
  565. .ops = &ab8500_regulator_mode_ops,
  566. .type = REGULATOR_VOLTAGE,
  567. .id = AB8500_LDO_TVOUT,
  568. .owner = THIS_MODULE,
  569. .n_voltages = 1,
  570. .volt_table = fixed_2000000_voltage,
  571. .enable_time = 500,
  572. },
  573. .load_lp_uA = 1000,
  574. .update_bank = 0x03,
  575. .update_reg = 0x80,
  576. .update_mask = 0x82,
  577. .update_val = 0x02,
  578. .update_val_idle = 0x82,
  579. .update_val_normal = 0x02,
  580. },
  581. [AB8500_LDO_AUDIO] = {
  582. .desc = {
  583. .name = "LDO-AUDIO",
  584. .ops = &ab8500_regulator_ops,
  585. .type = REGULATOR_VOLTAGE,
  586. .id = AB8500_LDO_AUDIO,
  587. .owner = THIS_MODULE,
  588. .n_voltages = 1,
  589. .enable_time = 140,
  590. .volt_table = fixed_2000000_voltage,
  591. },
  592. .update_bank = 0x03,
  593. .update_reg = 0x83,
  594. .update_mask = 0x02,
  595. .update_val = 0x02,
  596. },
  597. [AB8500_LDO_ANAMIC1] = {
  598. .desc = {
  599. .name = "LDO-ANAMIC1",
  600. .ops = &ab8500_regulator_ops,
  601. .type = REGULATOR_VOLTAGE,
  602. .id = AB8500_LDO_ANAMIC1,
  603. .owner = THIS_MODULE,
  604. .n_voltages = 1,
  605. .enable_time = 500,
  606. .volt_table = fixed_2050000_voltage,
  607. },
  608. .update_bank = 0x03,
  609. .update_reg = 0x83,
  610. .update_mask = 0x08,
  611. .update_val = 0x08,
  612. },
  613. [AB8500_LDO_ANAMIC2] = {
  614. .desc = {
  615. .name = "LDO-ANAMIC2",
  616. .ops = &ab8500_regulator_ops,
  617. .type = REGULATOR_VOLTAGE,
  618. .id = AB8500_LDO_ANAMIC2,
  619. .owner = THIS_MODULE,
  620. .n_voltages = 1,
  621. .enable_time = 500,
  622. .volt_table = fixed_2050000_voltage,
  623. },
  624. .update_bank = 0x03,
  625. .update_reg = 0x83,
  626. .update_mask = 0x10,
  627. .update_val = 0x10,
  628. },
  629. [AB8500_LDO_DMIC] = {
  630. .desc = {
  631. .name = "LDO-DMIC",
  632. .ops = &ab8500_regulator_ops,
  633. .type = REGULATOR_VOLTAGE,
  634. .id = AB8500_LDO_DMIC,
  635. .owner = THIS_MODULE,
  636. .n_voltages = 1,
  637. .enable_time = 420,
  638. .volt_table = fixed_1800000_voltage,
  639. },
  640. .update_bank = 0x03,
  641. .update_reg = 0x83,
  642. .update_mask = 0x04,
  643. .update_val = 0x04,
  644. },
  645. /*
  646. * Regulators with fixed voltage and normal/idle modes
  647. */
  648. [AB8500_LDO_ANA] = {
  649. .desc = {
  650. .name = "LDO-ANA",
  651. .ops = &ab8500_regulator_mode_ops,
  652. .type = REGULATOR_VOLTAGE,
  653. .id = AB8500_LDO_ANA,
  654. .owner = THIS_MODULE,
  655. .n_voltages = 1,
  656. .enable_time = 140,
  657. .volt_table = fixed_1200000_voltage,
  658. },
  659. .load_lp_uA = 1000,
  660. .update_bank = 0x04,
  661. .update_reg = 0x06,
  662. .update_mask = 0x0c,
  663. .update_val = 0x04,
  664. .update_val_idle = 0x0c,
  665. .update_val_normal = 0x04,
  666. },
  667. };
  668. /* AB8505 regulator information */
  669. static struct ab8500_regulator_info
  670. ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
  671. /*
  672. * Variable Voltage Regulators
  673. * name, min mV, max mV,
  674. * update bank, reg, mask, enable val
  675. * volt bank, reg, mask
  676. */
  677. [AB8505_LDO_AUX1] = {
  678. .desc = {
  679. .name = "LDO-AUX1",
  680. .ops = &ab8500_regulator_volt_mode_ops,
  681. .type = REGULATOR_VOLTAGE,
  682. .id = AB8505_LDO_AUX1,
  683. .owner = THIS_MODULE,
  684. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  685. .volt_table = ldo_vauxn_voltages,
  686. },
  687. .load_lp_uA = 5000,
  688. .update_bank = 0x04,
  689. .update_reg = 0x09,
  690. .update_mask = 0x03,
  691. .update_val = 0x01,
  692. .update_val_idle = 0x03,
  693. .update_val_normal = 0x01,
  694. .voltage_bank = 0x04,
  695. .voltage_reg = 0x1f,
  696. .voltage_mask = 0x0f,
  697. },
  698. [AB8505_LDO_AUX2] = {
  699. .desc = {
  700. .name = "LDO-AUX2",
  701. .ops = &ab8500_regulator_volt_mode_ops,
  702. .type = REGULATOR_VOLTAGE,
  703. .id = AB8505_LDO_AUX2,
  704. .owner = THIS_MODULE,
  705. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  706. .volt_table = ldo_vauxn_voltages,
  707. },
  708. .load_lp_uA = 5000,
  709. .update_bank = 0x04,
  710. .update_reg = 0x09,
  711. .update_mask = 0x0c,
  712. .update_val = 0x04,
  713. .update_val_idle = 0x0c,
  714. .update_val_normal = 0x04,
  715. .voltage_bank = 0x04,
  716. .voltage_reg = 0x20,
  717. .voltage_mask = 0x0f,
  718. },
  719. [AB8505_LDO_AUX3] = {
  720. .desc = {
  721. .name = "LDO-AUX3",
  722. .ops = &ab8500_regulator_volt_mode_ops,
  723. .type = REGULATOR_VOLTAGE,
  724. .id = AB8505_LDO_AUX3,
  725. .owner = THIS_MODULE,
  726. .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
  727. .volt_table = ldo_vaux3_voltages,
  728. },
  729. .load_lp_uA = 5000,
  730. .update_bank = 0x04,
  731. .update_reg = 0x0a,
  732. .update_mask = 0x03,
  733. .update_val = 0x01,
  734. .update_val_idle = 0x03,
  735. .update_val_normal = 0x01,
  736. .voltage_bank = 0x04,
  737. .voltage_reg = 0x21,
  738. .voltage_mask = 0x07,
  739. },
  740. [AB8505_LDO_AUX4] = {
  741. .desc = {
  742. .name = "LDO-AUX4",
  743. .ops = &ab8500_regulator_volt_mode_ops,
  744. .type = REGULATOR_VOLTAGE,
  745. .id = AB8505_LDO_AUX4,
  746. .owner = THIS_MODULE,
  747. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  748. .volt_table = ldo_vauxn_voltages,
  749. },
  750. .load_lp_uA = 5000,
  751. /* values for Vaux4Regu register */
  752. .update_bank = 0x04,
  753. .update_reg = 0x2e,
  754. .update_mask = 0x03,
  755. .update_val = 0x01,
  756. .update_val_idle = 0x03,
  757. .update_val_normal = 0x01,
  758. /* values for Vaux4SEL register */
  759. .voltage_bank = 0x04,
  760. .voltage_reg = 0x2f,
  761. .voltage_mask = 0x0f,
  762. },
  763. [AB8505_LDO_AUX5] = {
  764. .desc = {
  765. .name = "LDO-AUX5",
  766. .ops = &ab8500_regulator_volt_mode_ops,
  767. .type = REGULATOR_VOLTAGE,
  768. .id = AB8505_LDO_AUX5,
  769. .owner = THIS_MODULE,
  770. .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
  771. .volt_table = ldo_vaux56_voltages,
  772. },
  773. .load_lp_uA = 2000,
  774. /* values for CtrlVaux5 register */
  775. .update_bank = 0x01,
  776. .update_reg = 0x55,
  777. .update_mask = 0x18,
  778. .update_val = 0x10,
  779. .update_val_idle = 0x18,
  780. .update_val_normal = 0x10,
  781. .voltage_bank = 0x01,
  782. .voltage_reg = 0x55,
  783. .voltage_mask = 0x07,
  784. },
  785. [AB8505_LDO_AUX6] = {
  786. .desc = {
  787. .name = "LDO-AUX6",
  788. .ops = &ab8500_regulator_volt_mode_ops,
  789. .type = REGULATOR_VOLTAGE,
  790. .id = AB8505_LDO_AUX6,
  791. .owner = THIS_MODULE,
  792. .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
  793. .volt_table = ldo_vaux56_voltages,
  794. },
  795. .load_lp_uA = 2000,
  796. /* values for CtrlVaux6 register */
  797. .update_bank = 0x01,
  798. .update_reg = 0x56,
  799. .update_mask = 0x18,
  800. .update_val = 0x10,
  801. .update_val_idle = 0x18,
  802. .update_val_normal = 0x10,
  803. .voltage_bank = 0x01,
  804. .voltage_reg = 0x56,
  805. .voltage_mask = 0x07,
  806. },
  807. [AB8505_LDO_INTCORE] = {
  808. .desc = {
  809. .name = "LDO-INTCORE",
  810. .ops = &ab8500_regulator_volt_mode_ops,
  811. .type = REGULATOR_VOLTAGE,
  812. .id = AB8505_LDO_INTCORE,
  813. .owner = THIS_MODULE,
  814. .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
  815. .volt_table = ldo_vintcore_voltages,
  816. },
  817. .load_lp_uA = 5000,
  818. .update_bank = 0x03,
  819. .update_reg = 0x80,
  820. .update_mask = 0x44,
  821. .update_val = 0x04,
  822. .update_val_idle = 0x44,
  823. .update_val_normal = 0x04,
  824. .voltage_bank = 0x03,
  825. .voltage_reg = 0x80,
  826. .voltage_mask = 0x38,
  827. },
  828. /*
  829. * Fixed Voltage Regulators
  830. * name, fixed mV,
  831. * update bank, reg, mask, enable val
  832. */
  833. [AB8505_LDO_ADC] = {
  834. .desc = {
  835. .name = "LDO-ADC",
  836. .ops = &ab8500_regulator_mode_ops,
  837. .type = REGULATOR_VOLTAGE,
  838. .id = AB8505_LDO_ADC,
  839. .owner = THIS_MODULE,
  840. .n_voltages = 1,
  841. .volt_table = fixed_2000000_voltage,
  842. .enable_time = 10000,
  843. },
  844. .load_lp_uA = 1000,
  845. .update_bank = 0x03,
  846. .update_reg = 0x80,
  847. .update_mask = 0x82,
  848. .update_val = 0x02,
  849. .update_val_idle = 0x82,
  850. .update_val_normal = 0x02,
  851. },
  852. [AB8505_LDO_AUDIO] = {
  853. .desc = {
  854. .name = "LDO-AUDIO",
  855. .ops = &ab8500_regulator_volt_ops,
  856. .type = REGULATOR_VOLTAGE,
  857. .id = AB8505_LDO_AUDIO,
  858. .owner = THIS_MODULE,
  859. .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
  860. .volt_table = ldo_vaudio_voltages,
  861. },
  862. .update_bank = 0x03,
  863. .update_reg = 0x83,
  864. .update_mask = 0x02,
  865. .update_val = 0x02,
  866. .voltage_bank = 0x01,
  867. .voltage_reg = 0x57,
  868. .voltage_mask = 0x70,
  869. },
  870. [AB8505_LDO_ANAMIC1] = {
  871. .desc = {
  872. .name = "LDO-ANAMIC1",
  873. .ops = &ab8500_regulator_anamic_mode_ops,
  874. .type = REGULATOR_VOLTAGE,
  875. .id = AB8505_LDO_ANAMIC1,
  876. .owner = THIS_MODULE,
  877. .n_voltages = 1,
  878. .volt_table = fixed_2050000_voltage,
  879. },
  880. .shared_mode = &ldo_anamic1_shared,
  881. .update_bank = 0x03,
  882. .update_reg = 0x83,
  883. .update_mask = 0x08,
  884. .update_val = 0x08,
  885. .mode_bank = 0x01,
  886. .mode_reg = 0x54,
  887. .mode_mask = 0x04,
  888. .mode_val_idle = 0x04,
  889. .mode_val_normal = 0x00,
  890. },
  891. [AB8505_LDO_ANAMIC2] = {
  892. .desc = {
  893. .name = "LDO-ANAMIC2",
  894. .ops = &ab8500_regulator_anamic_mode_ops,
  895. .type = REGULATOR_VOLTAGE,
  896. .id = AB8505_LDO_ANAMIC2,
  897. .owner = THIS_MODULE,
  898. .n_voltages = 1,
  899. .volt_table = fixed_2050000_voltage,
  900. },
  901. .shared_mode = &ldo_anamic2_shared,
  902. .update_bank = 0x03,
  903. .update_reg = 0x83,
  904. .update_mask = 0x10,
  905. .update_val = 0x10,
  906. .mode_bank = 0x01,
  907. .mode_reg = 0x54,
  908. .mode_mask = 0x04,
  909. .mode_val_idle = 0x04,
  910. .mode_val_normal = 0x00,
  911. },
  912. [AB8505_LDO_AUX8] = {
  913. .desc = {
  914. .name = "LDO-AUX8",
  915. .ops = &ab8500_regulator_ops,
  916. .type = REGULATOR_VOLTAGE,
  917. .id = AB8505_LDO_AUX8,
  918. .owner = THIS_MODULE,
  919. .n_voltages = 1,
  920. .volt_table = fixed_1800000_voltage,
  921. },
  922. .update_bank = 0x03,
  923. .update_reg = 0x83,
  924. .update_mask = 0x04,
  925. .update_val = 0x04,
  926. },
  927. /*
  928. * Regulators with fixed voltage and normal/idle modes
  929. */
  930. [AB8505_LDO_ANA] = {
  931. .desc = {
  932. .name = "LDO-ANA",
  933. .ops = &ab8500_regulator_volt_mode_ops,
  934. .type = REGULATOR_VOLTAGE,
  935. .id = AB8505_LDO_ANA,
  936. .owner = THIS_MODULE,
  937. .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
  938. .volt_table = ldo_vana_voltages,
  939. },
  940. .load_lp_uA = 1000,
  941. .update_bank = 0x04,
  942. .update_reg = 0x06,
  943. .update_mask = 0x0c,
  944. .update_val = 0x04,
  945. .update_val_idle = 0x0c,
  946. .update_val_normal = 0x04,
  947. .voltage_bank = 0x04,
  948. .voltage_reg = 0x29,
  949. .voltage_mask = 0x7,
  950. },
  951. };
  952. static struct ab8500_shared_mode ldo_anamic1_shared = {
  953. .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
  954. };
  955. static struct ab8500_shared_mode ldo_anamic2_shared = {
  956. .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
  957. };
  958. struct ab8500_reg_init {
  959. u8 bank;
  960. u8 addr;
  961. u8 mask;
  962. };
  963. #define REG_INIT(_id, _bank, _addr, _mask) \
  964. [_id] = { \
  965. .bank = _bank, \
  966. .addr = _addr, \
  967. .mask = _mask, \
  968. }
  969. /* AB8500 register init */
  970. static struct ab8500_reg_init ab8500_reg_init[] = {
  971. /*
  972. * 0x30, VanaRequestCtrl
  973. * 0xc0, VextSupply1RequestCtrl
  974. */
  975. REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
  976. /*
  977. * 0x03, VextSupply2RequestCtrl
  978. * 0x0c, VextSupply3RequestCtrl
  979. * 0x30, Vaux1RequestCtrl
  980. * 0xc0, Vaux2RequestCtrl
  981. */
  982. REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
  983. /*
  984. * 0x03, Vaux3RequestCtrl
  985. * 0x04, SwHPReq
  986. */
  987. REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
  988. /*
  989. * 0x08, VanaSysClkReq1HPValid
  990. * 0x20, Vaux1SysClkReq1HPValid
  991. * 0x40, Vaux2SysClkReq1HPValid
  992. * 0x80, Vaux3SysClkReq1HPValid
  993. */
  994. REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
  995. /*
  996. * 0x10, VextSupply1SysClkReq1HPValid
  997. * 0x20, VextSupply2SysClkReq1HPValid
  998. * 0x40, VextSupply3SysClkReq1HPValid
  999. */
  1000. REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
  1001. /*
  1002. * 0x08, VanaHwHPReq1Valid
  1003. * 0x20, Vaux1HwHPReq1Valid
  1004. * 0x40, Vaux2HwHPReq1Valid
  1005. * 0x80, Vaux3HwHPReq1Valid
  1006. */
  1007. REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
  1008. /*
  1009. * 0x01, VextSupply1HwHPReq1Valid
  1010. * 0x02, VextSupply2HwHPReq1Valid
  1011. * 0x04, VextSupply3HwHPReq1Valid
  1012. */
  1013. REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
  1014. /*
  1015. * 0x08, VanaHwHPReq2Valid
  1016. * 0x20, Vaux1HwHPReq2Valid
  1017. * 0x40, Vaux2HwHPReq2Valid
  1018. * 0x80, Vaux3HwHPReq2Valid
  1019. */
  1020. REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
  1021. /*
  1022. * 0x01, VextSupply1HwHPReq2Valid
  1023. * 0x02, VextSupply2HwHPReq2Valid
  1024. * 0x04, VextSupply3HwHPReq2Valid
  1025. */
  1026. REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
  1027. /*
  1028. * 0x20, VanaSwHPReqValid
  1029. * 0x80, Vaux1SwHPReqValid
  1030. */
  1031. REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
  1032. /*
  1033. * 0x01, Vaux2SwHPReqValid
  1034. * 0x02, Vaux3SwHPReqValid
  1035. * 0x04, VextSupply1SwHPReqValid
  1036. * 0x08, VextSupply2SwHPReqValid
  1037. * 0x10, VextSupply3SwHPReqValid
  1038. */
  1039. REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
  1040. /*
  1041. * 0x02, SysClkReq2Valid1
  1042. * 0x04, SysClkReq3Valid1
  1043. * 0x08, SysClkReq4Valid1
  1044. * 0x10, SysClkReq5Valid1
  1045. * 0x20, SysClkReq6Valid1
  1046. * 0x40, SysClkReq7Valid1
  1047. * 0x80, SysClkReq8Valid1
  1048. */
  1049. REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
  1050. /*
  1051. * 0x02, SysClkReq2Valid2
  1052. * 0x04, SysClkReq3Valid2
  1053. * 0x08, SysClkReq4Valid2
  1054. * 0x10, SysClkReq5Valid2
  1055. * 0x20, SysClkReq6Valid2
  1056. * 0x40, SysClkReq7Valid2
  1057. * 0x80, SysClkReq8Valid2
  1058. */
  1059. REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
  1060. /*
  1061. * 0x02, VTVoutEna
  1062. * 0x04, Vintcore12Ena
  1063. * 0x38, Vintcore12Sel
  1064. * 0x40, Vintcore12LP
  1065. * 0x80, VTVoutLP
  1066. */
  1067. REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
  1068. /*
  1069. * 0x02, VaudioEna
  1070. * 0x04, VdmicEna
  1071. * 0x08, Vamic1Ena
  1072. * 0x10, Vamic2Ena
  1073. */
  1074. REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
  1075. /*
  1076. * 0x01, Vamic1_dzout
  1077. * 0x02, Vamic2_dzout
  1078. */
  1079. REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
  1080. /*
  1081. * 0x03, VpllRegu (NOTE! PRCMU register bits)
  1082. * 0x0c, VanaRegu
  1083. */
  1084. REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
  1085. /*
  1086. * 0x01, VrefDDREna
  1087. * 0x02, VrefDDRSleepMode
  1088. */
  1089. REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
  1090. /*
  1091. * 0x03, VextSupply1Regu
  1092. * 0x0c, VextSupply2Regu
  1093. * 0x30, VextSupply3Regu
  1094. * 0x40, ExtSupply2Bypass
  1095. * 0x80, ExtSupply3Bypass
  1096. */
  1097. REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
  1098. /*
  1099. * 0x03, Vaux1Regu
  1100. * 0x0c, Vaux2Regu
  1101. */
  1102. REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
  1103. /*
  1104. * 0x03, Vaux3Regu
  1105. */
  1106. REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
  1107. /*
  1108. * 0x0f, Vaux1Sel
  1109. */
  1110. REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
  1111. /*
  1112. * 0x0f, Vaux2Sel
  1113. */
  1114. REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
  1115. /*
  1116. * 0x07, Vaux3Sel
  1117. */
  1118. REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
  1119. /*
  1120. * 0x01, VextSupply12LP
  1121. */
  1122. REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
  1123. /*
  1124. * 0x04, Vaux1Disch
  1125. * 0x08, Vaux2Disch
  1126. * 0x10, Vaux3Disch
  1127. * 0x20, Vintcore12Disch
  1128. * 0x40, VTVoutDisch
  1129. * 0x80, VaudioDisch
  1130. */
  1131. REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
  1132. /*
  1133. * 0x02, VanaDisch
  1134. * 0x04, VdmicPullDownEna
  1135. * 0x10, VdmicDisch
  1136. */
  1137. REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
  1138. };
  1139. /* AB8505 register init */
  1140. static struct ab8500_reg_init ab8505_reg_init[] = {
  1141. /*
  1142. * 0x03, VarmRequestCtrl
  1143. * 0x0c, VsmpsCRequestCtrl
  1144. * 0x30, VsmpsARequestCtrl
  1145. * 0xc0, VsmpsBRequestCtrl
  1146. */
  1147. REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
  1148. /*
  1149. * 0x03, VsafeRequestCtrl
  1150. * 0x0c, VpllRequestCtrl
  1151. * 0x30, VanaRequestCtrl
  1152. */
  1153. REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
  1154. /*
  1155. * 0x30, Vaux1RequestCtrl
  1156. * 0xc0, Vaux2RequestCtrl
  1157. */
  1158. REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
  1159. /*
  1160. * 0x03, Vaux3RequestCtrl
  1161. * 0x04, SwHPReq
  1162. */
  1163. REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
  1164. /*
  1165. * 0x01, VsmpsASysClkReq1HPValid
  1166. * 0x02, VsmpsBSysClkReq1HPValid
  1167. * 0x04, VsafeSysClkReq1HPValid
  1168. * 0x08, VanaSysClkReq1HPValid
  1169. * 0x10, VpllSysClkReq1HPValid
  1170. * 0x20, Vaux1SysClkReq1HPValid
  1171. * 0x40, Vaux2SysClkReq1HPValid
  1172. * 0x80, Vaux3SysClkReq1HPValid
  1173. */
  1174. REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
  1175. /*
  1176. * 0x01, VsmpsCSysClkReq1HPValid
  1177. * 0x02, VarmSysClkReq1HPValid
  1178. * 0x04, VbbSysClkReq1HPValid
  1179. * 0x08, VsmpsMSysClkReq1HPValid
  1180. */
  1181. REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
  1182. /*
  1183. * 0x01, VsmpsAHwHPReq1Valid
  1184. * 0x02, VsmpsBHwHPReq1Valid
  1185. * 0x04, VsafeHwHPReq1Valid
  1186. * 0x08, VanaHwHPReq1Valid
  1187. * 0x10, VpllHwHPReq1Valid
  1188. * 0x20, Vaux1HwHPReq1Valid
  1189. * 0x40, Vaux2HwHPReq1Valid
  1190. * 0x80, Vaux3HwHPReq1Valid
  1191. */
  1192. REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
  1193. /*
  1194. * 0x08, VsmpsMHwHPReq1Valid
  1195. */
  1196. REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
  1197. /*
  1198. * 0x01, VsmpsAHwHPReq2Valid
  1199. * 0x02, VsmpsBHwHPReq2Valid
  1200. * 0x04, VsafeHwHPReq2Valid
  1201. * 0x08, VanaHwHPReq2Valid
  1202. * 0x10, VpllHwHPReq2Valid
  1203. * 0x20, Vaux1HwHPReq2Valid
  1204. * 0x40, Vaux2HwHPReq2Valid
  1205. * 0x80, Vaux3HwHPReq2Valid
  1206. */
  1207. REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
  1208. /*
  1209. * 0x08, VsmpsMHwHPReq2Valid
  1210. */
  1211. REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
  1212. /*
  1213. * 0x01, VsmpsCSwHPReqValid
  1214. * 0x02, VarmSwHPReqValid
  1215. * 0x04, VsmpsASwHPReqValid
  1216. * 0x08, VsmpsBSwHPReqValid
  1217. * 0x10, VsafeSwHPReqValid
  1218. * 0x20, VanaSwHPReqValid
  1219. * 0x40, VpllSwHPReqValid
  1220. * 0x80, Vaux1SwHPReqValid
  1221. */
  1222. REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
  1223. /*
  1224. * 0x01, Vaux2SwHPReqValid
  1225. * 0x02, Vaux3SwHPReqValid
  1226. * 0x20, VsmpsMSwHPReqValid
  1227. */
  1228. REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
  1229. /*
  1230. * 0x02, SysClkReq2Valid1
  1231. * 0x04, SysClkReq3Valid1
  1232. * 0x08, SysClkReq4Valid1
  1233. */
  1234. REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
  1235. /*
  1236. * 0x02, SysClkReq2Valid2
  1237. * 0x04, SysClkReq3Valid2
  1238. * 0x08, SysClkReq4Valid2
  1239. */
  1240. REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
  1241. /*
  1242. * 0x01, Vaux4SwHPReqValid
  1243. * 0x02, Vaux4HwHPReq2Valid
  1244. * 0x04, Vaux4HwHPReq1Valid
  1245. * 0x08, Vaux4SysClkReq1HPValid
  1246. */
  1247. REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
  1248. /*
  1249. * 0x02, VadcEna
  1250. * 0x04, VintCore12Ena
  1251. * 0x38, VintCore12Sel
  1252. * 0x40, VintCore12LP
  1253. * 0x80, VadcLP
  1254. */
  1255. REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
  1256. /*
  1257. * 0x02, VaudioEna
  1258. * 0x04, VdmicEna
  1259. * 0x08, Vamic1Ena
  1260. * 0x10, Vamic2Ena
  1261. */
  1262. REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
  1263. /*
  1264. * 0x01, Vamic1_dzout
  1265. * 0x02, Vamic2_dzout
  1266. */
  1267. REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
  1268. /*
  1269. * 0x03, VsmpsARegu
  1270. * 0x0c, VsmpsASelCtrl
  1271. * 0x10, VsmpsAAutoMode
  1272. * 0x20, VsmpsAPWMMode
  1273. */
  1274. REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
  1275. /*
  1276. * 0x03, VsmpsBRegu
  1277. * 0x0c, VsmpsBSelCtrl
  1278. * 0x10, VsmpsBAutoMode
  1279. * 0x20, VsmpsBPWMMode
  1280. */
  1281. REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
  1282. /*
  1283. * 0x03, VsafeRegu
  1284. * 0x0c, VsafeSelCtrl
  1285. * 0x10, VsafeAutoMode
  1286. * 0x20, VsafePWMMode
  1287. */
  1288. REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
  1289. /*
  1290. * 0x03, VpllRegu (NOTE! PRCMU register bits)
  1291. * 0x0c, VanaRegu
  1292. */
  1293. REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
  1294. /*
  1295. * 0x03, VextSupply1Regu
  1296. * 0x0c, VextSupply2Regu
  1297. * 0x30, VextSupply3Regu
  1298. * 0x40, ExtSupply2Bypass
  1299. * 0x80, ExtSupply3Bypass
  1300. */
  1301. REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
  1302. /*
  1303. * 0x03, Vaux1Regu
  1304. * 0x0c, Vaux2Regu
  1305. */
  1306. REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
  1307. /*
  1308. * 0x0f, Vaux3Regu
  1309. */
  1310. REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
  1311. /*
  1312. * 0x3f, VsmpsASel1
  1313. */
  1314. REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
  1315. /*
  1316. * 0x3f, VsmpsASel2
  1317. */
  1318. REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
  1319. /*
  1320. * 0x3f, VsmpsASel3
  1321. */
  1322. REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
  1323. /*
  1324. * 0x3f, VsmpsBSel1
  1325. */
  1326. REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
  1327. /*
  1328. * 0x3f, VsmpsBSel2
  1329. */
  1330. REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
  1331. /*
  1332. * 0x3f, VsmpsBSel3
  1333. */
  1334. REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
  1335. /*
  1336. * 0x7f, VsafeSel1
  1337. */
  1338. REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
  1339. /*
  1340. * 0x3f, VsafeSel2
  1341. */
  1342. REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
  1343. /*
  1344. * 0x3f, VsafeSel3
  1345. */
  1346. REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
  1347. /*
  1348. * 0x0f, Vaux1Sel
  1349. */
  1350. REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
  1351. /*
  1352. * 0x0f, Vaux2Sel
  1353. */
  1354. REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
  1355. /*
  1356. * 0x07, Vaux3Sel
  1357. * 0x30, VRF1Sel
  1358. */
  1359. REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
  1360. /*
  1361. * 0x03, Vaux4RequestCtrl
  1362. */
  1363. REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
  1364. /*
  1365. * 0x03, Vaux4Regu
  1366. */
  1367. REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
  1368. /*
  1369. * 0x0f, Vaux4Sel
  1370. */
  1371. REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
  1372. /*
  1373. * 0x04, Vaux1Disch
  1374. * 0x08, Vaux2Disch
  1375. * 0x10, Vaux3Disch
  1376. * 0x20, Vintcore12Disch
  1377. * 0x40, VTVoutDisch
  1378. * 0x80, VaudioDisch
  1379. */
  1380. REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
  1381. /*
  1382. * 0x02, VanaDisch
  1383. * 0x04, VdmicPullDownEna
  1384. * 0x10, VdmicDisch
  1385. */
  1386. REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
  1387. /*
  1388. * 0x01, Vaux4Disch
  1389. */
  1390. REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
  1391. /*
  1392. * 0x07, Vaux5Sel
  1393. * 0x08, Vaux5LP
  1394. * 0x10, Vaux5Ena
  1395. * 0x20, Vaux5Disch
  1396. * 0x40, Vaux5DisSfst
  1397. * 0x80, Vaux5DisPulld
  1398. */
  1399. REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
  1400. /*
  1401. * 0x07, Vaux6Sel
  1402. * 0x08, Vaux6LP
  1403. * 0x10, Vaux6Ena
  1404. * 0x80, Vaux6DisPulld
  1405. */
  1406. REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
  1407. };
  1408. static struct of_regulator_match ab8500_regulator_match[] = {
  1409. { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
  1410. { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
  1411. { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
  1412. { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
  1413. { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
  1414. { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
  1415. { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
  1416. { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
  1417. { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
  1418. { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
  1419. };
  1420. static struct of_regulator_match ab8505_regulator_match[] = {
  1421. { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
  1422. { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
  1423. { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
  1424. { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
  1425. { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
  1426. { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
  1427. { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
  1428. { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
  1429. { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
  1430. { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
  1431. { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
  1432. { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
  1433. { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
  1434. };
  1435. static struct {
  1436. struct ab8500_regulator_info *info;
  1437. int info_size;
  1438. struct ab8500_reg_init *init;
  1439. int init_size;
  1440. struct of_regulator_match *match;
  1441. int match_size;
  1442. } abx500_regulator;
  1443. static void abx500_get_regulator_info(struct ab8500 *ab8500)
  1444. {
  1445. if (is_ab8505(ab8500)) {
  1446. abx500_regulator.info = ab8505_regulator_info;
  1447. abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
  1448. abx500_regulator.init = ab8505_reg_init;
  1449. abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
  1450. abx500_regulator.match = ab8505_regulator_match;
  1451. abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
  1452. } else {
  1453. abx500_regulator.info = ab8500_regulator_info;
  1454. abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
  1455. abx500_regulator.init = ab8500_reg_init;
  1456. abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
  1457. abx500_regulator.match = ab8500_regulator_match;
  1458. abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
  1459. }
  1460. }
  1461. static int ab8500_regulator_register(struct platform_device *pdev,
  1462. struct regulator_init_data *init_data,
  1463. int id, struct device_node *np)
  1464. {
  1465. struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
  1466. struct ab8500_regulator_info *info = NULL;
  1467. struct regulator_config config = { };
  1468. struct regulator_dev *rdev;
  1469. /* assign per-regulator data */
  1470. info = &abx500_regulator.info[id];
  1471. info->dev = &pdev->dev;
  1472. config.dev = &pdev->dev;
  1473. config.init_data = init_data;
  1474. config.driver_data = info;
  1475. config.of_node = np;
  1476. /* fix for hardware before ab8500v2.0 */
  1477. if (is_ab8500_1p1_or_earlier(ab8500)) {
  1478. if (info->desc.id == AB8500_LDO_AUX3) {
  1479. info->desc.n_voltages =
  1480. ARRAY_SIZE(ldo_vauxn_voltages);
  1481. info->desc.volt_table = ldo_vauxn_voltages;
  1482. info->voltage_mask = 0xf;
  1483. }
  1484. }
  1485. /* register regulator with framework */
  1486. rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
  1487. if (IS_ERR(rdev)) {
  1488. dev_err(&pdev->dev, "failed to register regulator %s\n",
  1489. info->desc.name);
  1490. return PTR_ERR(rdev);
  1491. }
  1492. return 0;
  1493. }
  1494. static int ab8500_regulator_probe(struct platform_device *pdev)
  1495. {
  1496. struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
  1497. struct device_node *np = pdev->dev.of_node;
  1498. struct of_regulator_match *match;
  1499. int err, i;
  1500. if (!ab8500) {
  1501. dev_err(&pdev->dev, "null mfd parent\n");
  1502. return -EINVAL;
  1503. }
  1504. abx500_get_regulator_info(ab8500);
  1505. err = of_regulator_match(&pdev->dev, np,
  1506. abx500_regulator.match,
  1507. abx500_regulator.match_size);
  1508. if (err < 0) {
  1509. dev_err(&pdev->dev,
  1510. "Error parsing regulator init data: %d\n", err);
  1511. return err;
  1512. }
  1513. match = abx500_regulator.match;
  1514. for (i = 0; i < abx500_regulator.info_size; i++) {
  1515. err = ab8500_regulator_register(pdev, match[i].init_data, i,
  1516. match[i].of_node);
  1517. if (err)
  1518. return err;
  1519. }
  1520. return 0;
  1521. }
  1522. static struct platform_driver ab8500_regulator_driver = {
  1523. .probe = ab8500_regulator_probe,
  1524. .driver = {
  1525. .name = "ab8500-regulator",
  1526. },
  1527. };
  1528. static int __init ab8500_regulator_init(void)
  1529. {
  1530. int ret;
  1531. ret = platform_driver_register(&ab8500_regulator_driver);
  1532. if (ret != 0)
  1533. pr_err("Failed to register ab8500 regulator: %d\n", ret);
  1534. return ret;
  1535. }
  1536. subsys_initcall(ab8500_regulator_init);
  1537. static void __exit ab8500_regulator_exit(void)
  1538. {
  1539. platform_driver_unregister(&ab8500_regulator_driver);
  1540. }
  1541. module_exit(ab8500_regulator_exit);
  1542. MODULE_LICENSE("GPL v2");
  1543. MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
  1544. MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
  1545. MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
  1546. MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
  1547. MODULE_ALIAS("platform:ab8500-regulator");