tsi721.h 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Tsi721 PCIExpress-to-SRIO bridge definitions
  4. *
  5. * Copyright 2011, Integrated Device Technology, Inc.
  6. */
  7. #ifndef __TSI721_H
  8. #define __TSI721_H
  9. /* Debug output filtering masks */
  10. enum {
  11. DBG_NONE = 0,
  12. DBG_INIT = BIT(0), /* driver init */
  13. DBG_EXIT = BIT(1), /* driver exit */
  14. DBG_MPORT = BIT(2), /* mport add/remove */
  15. DBG_MAINT = BIT(3), /* maintenance ops messages */
  16. DBG_DMA = BIT(4), /* DMA transfer messages */
  17. DBG_DMAV = BIT(5), /* verbose DMA transfer messages */
  18. DBG_IBW = BIT(6), /* inbound window */
  19. DBG_EVENT = BIT(7), /* event handling messages */
  20. DBG_OBW = BIT(8), /* outbound window messages */
  21. DBG_DBELL = BIT(9), /* doorbell messages */
  22. DBG_OMSG = BIT(10), /* doorbell messages */
  23. DBG_IMSG = BIT(11), /* doorbell messages */
  24. DBG_ALL = ~0,
  25. };
  26. #ifdef DEBUG
  27. extern u32 tsi_dbg_level;
  28. #define tsi_debug(level, dev, fmt, arg...) \
  29. do { \
  30. if (DBG_##level & tsi_dbg_level) \
  31. dev_dbg(dev, "%s: " fmt "\n", __func__, ##arg); \
  32. } while (0)
  33. #else
  34. #define tsi_debug(level, dev, fmt, arg...) \
  35. no_printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##arg)
  36. #endif
  37. #define tsi_info(dev, fmt, arg...) \
  38. dev_info(dev, "%s: " fmt "\n", __func__, ##arg)
  39. #define tsi_warn(dev, fmt, arg...) \
  40. dev_warn(dev, "%s: WARNING " fmt "\n", __func__, ##arg)
  41. #define tsi_err(dev, fmt, arg...) \
  42. dev_err(dev, "%s: ERROR " fmt "\n", __func__, ##arg)
  43. #define DRV_NAME "tsi721"
  44. #define DEFAULT_HOPCOUNT 0xff
  45. #define DEFAULT_DESTID 0xff
  46. /* PCI device ID */
  47. #define PCI_DEVICE_ID_TSI721 0x80ab
  48. #define BAR_0 0
  49. #define BAR_1 1
  50. #define BAR_2 2
  51. #define BAR_4 4
  52. #define TSI721_PC2SR_BARS 2
  53. #define TSI721_PC2SR_WINS 8
  54. #define TSI721_PC2SR_ZONES 8
  55. #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
  56. #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
  57. #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */
  58. /* Memory space sizes */
  59. #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */
  60. #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */
  61. #define RIO_TT_CODE_8 0x00000000
  62. #define RIO_TT_CODE_16 0x00000001
  63. #define TSI721_DMA_MAXCH 8
  64. #define TSI721_DMA_MINSTSSZ 32
  65. #define TSI721_DMA_STSBLKSZ 8
  66. #define TSI721_SRIO_MAXCH 8
  67. #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3])
  68. #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5])
  69. #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
  70. #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */
  71. /* Register definitions */
  72. /*
  73. * Registers in PCIe configuration space
  74. */
  75. #define TSI721_PCIECFG_MSIXTBL 0x0a4
  76. #define TSI721_MSIXTBL_OFFSET 0x2c000
  77. #define TSI721_PCIECFG_MSIXPBA 0x0a8
  78. #define TSI721_MSIXPBA_OFFSET 0x2a000
  79. #define TSI721_PCIECFG_EPCTL 0x400
  80. /*
  81. * Event Management Registers
  82. */
  83. #define TSI721_RIO_EM_INT_STAT 0x10910
  84. #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
  85. #define TSI721_RIO_EM_INT_ENABLE 0x10914
  86. #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
  87. #define TSI721_RIO_EM_DEV_INT_EN 0x10930
  88. #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
  89. /*
  90. * Port-Write Block Registers
  91. */
  92. #define TSI721_RIO_PW_CTL 0x10a04
  93. #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
  94. #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
  95. #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28)
  96. #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29)
  97. #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30)
  98. #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31)
  99. #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
  100. #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
  101. #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
  102. #define TSI721_RIO_PW_RX_STAT 0x10a10
  103. #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
  104. #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
  105. #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
  106. #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
  107. #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
  108. #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
  109. #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
  110. /*
  111. * Inbound Doorbells
  112. */
  113. #define TSI721_IDB_ENTRY_SIZE 64
  114. #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
  115. #define TSI721_IDQ_SUSPEND 0x00000002
  116. #define TSI721_IDQ_INIT 0x00000001
  117. #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
  118. #define TSI721_IDQ_RUN 0x00200000
  119. #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
  120. #define TSI721_IDQ_MASK_MASK 0xffff0000
  121. #define TSI721_IDQ_MASK_PATT 0x0000ffff
  122. #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
  123. #define TSI721_IDQ_RP_PTR 0x0007ffff
  124. #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
  125. #define TSI721_IDQ_WP_PTR 0x0007ffff
  126. #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
  127. #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
  128. #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
  129. #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
  130. #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
  131. #define TSI721_IDQ_SIZE_MIN 512
  132. #define TSI721_IDQ_SIZE_MAX (512 * 1024)
  133. #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
  134. #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
  135. #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
  136. #define TSI721_SR_CHINT_ODBOK 0x00000020
  137. #define TSI721_SR_CHINT_IDBQRCV 0x00000010
  138. #define TSI721_SR_CHINT_SUSP 0x00000008
  139. #define TSI721_SR_CHINT_ODBTO 0x00000004
  140. #define TSI721_SR_CHINT_ODBRTRY 0x00000002
  141. #define TSI721_SR_CHINT_ODBERR 0x00000001
  142. #define TSI721_SR_CHINT_ALL 0x0000003f
  143. #define TSI721_IBWIN_NUM 8
  144. #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20)
  145. #define TSI721_IBWIN_LB_BA 0xfffff000
  146. #define TSI721_IBWIN_LB_WEN 0x00000001
  147. #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20)
  148. #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20)
  149. #define TSI721_IBWIN_SZ_SIZE 0x00001f00
  150. #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
  151. #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20)
  152. #define TSI721_IBWIN_TLA_ADD 0xfffff000
  153. #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20)
  154. #define TSI721_SR2PC_GEN_INTE 0x29800
  155. #define TSI721_SR2PC_PWE 0x29804
  156. #define TSI721_SR2PC_GEN_INT 0x29808
  157. #define TSI721_DEV_INTE 0x29840
  158. #define TSI721_DEV_INT 0x29844
  159. #define TSI721_DEV_INTSET 0x29848
  160. #define TSI721_DEV_INT_BDMA_CH 0x00002000
  161. #define TSI721_DEV_INT_BDMA_NCH 0x00001000
  162. #define TSI721_DEV_INT_SMSG_CH 0x00000800
  163. #define TSI721_DEV_INT_SMSG_NCH 0x00000400
  164. #define TSI721_DEV_INT_SR2PC_CH 0x00000200
  165. #define TSI721_DEV_INT_SRIO 0x00000020
  166. #define TSI721_DEV_CHAN_INTE 0x2984c
  167. #define TSI721_DEV_CHAN_INT 0x29850
  168. #define TSI721_INT_SR2PC_CHAN_M 0xff000000
  169. #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x)))
  170. #define TSI721_INT_IMSG_CHAN_M 0x00ff0000
  171. #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
  172. #define TSI721_INT_OMSG_CHAN_M 0x0000ff00
  173. #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
  174. #define TSI721_INT_BDMA_CHAN_M 0x000000ff
  175. #define TSI721_INT_BDMA_CHAN(x) (1 << (x))
  176. /*
  177. * PC2SR block registers
  178. */
  179. #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
  180. #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
  181. #define TSI721_OBWINLB_BA 0xffff8000
  182. #define TSI721_OBWINLB_WEN 0x00000001
  183. #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
  184. #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
  185. #define TSI721_OBWINSZ_SIZE 0x00001f00
  186. #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
  187. #define TSI721_ZONE_SEL 0x41300
  188. #define TSI721_ZONE_SEL_RD_WRB 0x00020000
  189. #define TSI721_ZONE_SEL_GO 0x00010000
  190. #define TSI721_ZONE_SEL_WIN 0x00000038
  191. #define TSI721_ZONE_SEL_ZONE 0x00000007
  192. #define TSI721_LUT_DATA0 0x41304
  193. #define TSI721_LUT_DATA0_ADD 0xfffff000
  194. #define TSI721_LUT_DATA0_RDTYPE 0x00000f00
  195. #define TSI721_LUT_DATA0_NREAD 0x00000100
  196. #define TSI721_LUT_DATA0_MNTRD 0x00000200
  197. #define TSI721_LUT_DATA0_RDCRF 0x00000020
  198. #define TSI721_LUT_DATA0_WRCRF 0x00000010
  199. #define TSI721_LUT_DATA0_WRTYPE 0x0000000f
  200. #define TSI721_LUT_DATA0_NWR 0x00000001
  201. #define TSI721_LUT_DATA0_MNTWR 0x00000002
  202. #define TSI721_LUT_DATA0_NWR_R 0x00000004
  203. #define TSI721_LUT_DATA1 0x41308
  204. #define TSI721_LUT_DATA2 0x4130c
  205. #define TSI721_LUT_DATA2_HC 0xff000000
  206. #define TSI721_LUT_DATA2_ADD65 0x000c0000
  207. #define TSI721_LUT_DATA2_TT 0x00030000
  208. #define TSI721_LUT_DATA2_DSTID 0x0000ffff
  209. #define TSI721_PC2SR_INTE 0x41310
  210. #define TSI721_DEVCTL 0x48004
  211. #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
  212. #define TSI721_I2C_INT_ENABLE 0x49120
  213. /*
  214. * Block DMA Engine Registers
  215. * x = 0..7
  216. */
  217. #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
  218. #define TSI721_DMAC_DWRCNT 0x000
  219. #define TSI721_DMAC_DRDCNT 0x004
  220. #define TSI721_DMAC_CTL 0x008
  221. #define TSI721_DMAC_CTL_SUSP 0x00000002
  222. #define TSI721_DMAC_CTL_INIT 0x00000001
  223. #define TSI721_DMAC_INT 0x00c
  224. #define TSI721_DMAC_INT_STFULL 0x00000010
  225. #define TSI721_DMAC_INT_DONE 0x00000008
  226. #define TSI721_DMAC_INT_SUSP 0x00000004
  227. #define TSI721_DMAC_INT_ERR 0x00000002
  228. #define TSI721_DMAC_INT_IOFDONE 0x00000001
  229. #define TSI721_DMAC_INT_ALL 0x0000001f
  230. #define TSI721_DMAC_INTSET 0x010
  231. #define TSI721_DMAC_STS 0x014
  232. #define TSI721_DMAC_STS_ABORT 0x00400000
  233. #define TSI721_DMAC_STS_RUN 0x00200000
  234. #define TSI721_DMAC_STS_CS 0x001f0000
  235. #define TSI721_DMAC_INTE 0x018
  236. #define TSI721_DMAC_DPTRL 0x024
  237. #define TSI721_DMAC_DPTRL_MASK 0xffffffe0
  238. #define TSI721_DMAC_DPTRH 0x028
  239. #define TSI721_DMAC_DSBL 0x02c
  240. #define TSI721_DMAC_DSBL_MASK 0xffffffc0
  241. #define TSI721_DMAC_DSBH 0x030
  242. #define TSI721_DMAC_DSSZ 0x034
  243. #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
  244. #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
  245. #define TSI721_DMAC_DSRP 0x038
  246. #define TSI721_DMAC_DSRP_MASK 0x0007ffff
  247. #define TSI721_DMAC_DSWP 0x03c
  248. #define TSI721_DMAC_DSWP_MASK 0x0007ffff
  249. #define TSI721_BDMA_INTE 0x5f000
  250. /*
  251. * Messaging definitions
  252. */
  253. #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE
  254. #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE
  255. #define TSI721_IMSG_MAXCH 8
  256. #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH
  257. #define TSI721_IMSGD_MIN_RING_SIZE 32
  258. #define TSI721_IMSGD_RING_SIZE 512
  259. #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */
  260. #define TSI721_OMSGD_MIN_RING_SIZE 32
  261. #define TSI721_OMSGD_RING_SIZE 512
  262. /*
  263. * Outbound Messaging Engine Registers
  264. * x = 0..7
  265. */
  266. #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
  267. #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
  268. #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
  269. #define TSI721_OBDMAC_CTL_MASK 0x00000007
  270. #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
  271. #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
  272. #define TSI721_OBDMAC_CTL_INIT 0x00000001
  273. #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
  274. #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
  275. #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
  276. #define TSI721_OBDMAC_INT_MASK 0x0000001F
  277. #define TSI721_OBDMAC_INT_ST_FULL 0x00000010
  278. #define TSI721_OBDMAC_INT_DONE 0x00000008
  279. #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
  280. #define TSI721_OBDMAC_INT_ERROR 0x00000002
  281. #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
  282. #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK
  283. #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
  284. #define TSI721_OBDMAC_STS_MASK 0x007f0000
  285. #define TSI721_OBDMAC_STS_ABORT 0x00400000
  286. #define TSI721_OBDMAC_STS_RUN 0x00200000
  287. #define TSI721_OBDMAC_STS_CS 0x001f0000
  288. #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
  289. #define TSI721_OBDMAC_PWE_MASK 0x00000002
  290. #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
  291. #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
  292. #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
  293. #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
  294. #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
  295. #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
  296. #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
  297. #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
  298. #define TSI721_OBDMAC_DSBH_MASK 0xffffffff
  299. #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
  300. #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
  301. #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
  302. #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
  303. #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
  304. #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
  305. #define TSI721_RQRPTO 0x60010
  306. #define TSI721_RQRPTO_MASK 0x00ffffff
  307. #define TSI721_RQRPTO_VAL 400 /* Response TO value */
  308. /*
  309. * Inbound Messaging Engine Registers
  310. * x = 0..7
  311. */
  312. #define TSI721_IB_DEVID_GLOBAL 0xffff
  313. #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
  314. #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
  315. #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
  316. #define TSI721_IBDMAC_FQBH_MASK 0xffffffff
  317. #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE
  318. #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
  319. #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
  320. #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
  321. #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
  322. #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
  323. #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
  324. #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
  325. #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
  326. #define TSI721_IB_DEVID 0x60020
  327. #define TSI721_IB_DEVID_MASK 0x0000ffff
  328. #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
  329. #define TSI721_IBDMAC_CTL_MASK 0x00000003
  330. #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
  331. #define TSI721_IBDMAC_CTL_INIT 0x00000001
  332. #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
  333. #define TSI721_IBDMAC_STS_MASK 0x007f0000
  334. #define TSI721_IBSMAC_STS_ABORT 0x00400000
  335. #define TSI721_IBSMAC_STS_RUN 0x00200000
  336. #define TSI721_IBSMAC_STS_CS 0x001f0000
  337. #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
  338. #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
  339. #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
  340. #define TSI721_IBDMAC_INT_MASK 0x0000100f
  341. #define TSI721_IBDMAC_INT_SRTO 0x00001000
  342. #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
  343. #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
  344. #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
  345. #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
  346. #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK
  347. #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
  348. #define TSI721_IBDMAC_PWE_MASK 0x00001700
  349. #define TSI721_IBDMAC_PWE_SRTO 0x00001000
  350. #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
  351. #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
  352. #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
  353. #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
  354. #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
  355. #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
  356. #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
  357. #define TSI721_IBDMAC_DQBH_MASK 0xffffffff
  358. #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
  359. #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
  360. #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
  361. #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
  362. #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
  363. #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
  364. /*
  365. * Messaging Engine Interrupts
  366. */
  367. #define TSI721_SMSG_PWE 0x6a004
  368. #define TSI721_SMSG_INTE 0x6a000
  369. #define TSI721_SMSG_INT 0x6a008
  370. #define TSI721_SMSG_INTSET 0x6a010
  371. #define TSI721_SMSG_INT_MASK 0x0086ffff
  372. #define TSI721_SMSG_INT_UNS_RSP 0x00800000
  373. #define TSI721_SMSG_INT_ECC_NCOR 0x00040000
  374. #define TSI721_SMSG_INT_ECC_COR 0x00020000
  375. #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
  376. #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
  377. #define TSI721_SMSG_ECC_LOG 0x6a014
  378. #define TSI721_SMSG_ECC_LOG_MASK 0x00070007
  379. #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
  380. #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
  381. #define TSI721_RETRY_GEN_CNT 0x6a100
  382. #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
  383. #define TSI721_RETRY_RX_CNT 0x6a104
  384. #define TSI721_RETRY_RX_CNT_MASK 0xffffffff
  385. #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
  386. #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
  387. #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
  388. #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
  389. /*
  390. * Block DMA Descriptors
  391. */
  392. struct tsi721_dma_desc {
  393. __le32 type_id;
  394. #define TSI721_DMAD_DEVID 0x0000ffff
  395. #define TSI721_DMAD_CRF 0x00010000
  396. #define TSI721_DMAD_PRIO 0x00060000
  397. #define TSI721_DMAD_RTYPE 0x00780000
  398. #define TSI721_DMAD_IOF 0x08000000
  399. #define TSI721_DMAD_DTYPE 0xe0000000
  400. __le32 bcount;
  401. #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
  402. #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
  403. #define TSI721_DMAD_TT 0x0c000000
  404. #define TSI721_DMAD_RADDR0 0xc0000000
  405. union {
  406. __le32 raddr_lo; /* if DTYPE == (1 || 2) */
  407. __le32 next_lo; /* if DTYPE == 3 */
  408. };
  409. #define TSI721_DMAD_CFGOFF 0x00ffffff
  410. #define TSI721_DMAD_HOPCNT 0xff000000
  411. union {
  412. __le32 raddr_hi; /* if DTYPE == (1 || 2) */
  413. __le32 next_hi; /* if DTYPE == 3 */
  414. };
  415. union {
  416. struct { /* if DTYPE == 1 */
  417. __le32 bufptr_lo;
  418. __le32 bufptr_hi;
  419. __le32 s_dist;
  420. __le32 s_size;
  421. } t1;
  422. __le32 data[4]; /* if DTYPE == 2 */
  423. u32 reserved[4]; /* if DTYPE == 3 */
  424. };
  425. } __aligned(32);
  426. /*
  427. * Inbound Messaging Descriptor
  428. */
  429. struct tsi721_imsg_desc {
  430. __le32 type_id;
  431. #define TSI721_IMD_DEVID 0x0000ffff
  432. #define TSI721_IMD_CRF 0x00010000
  433. #define TSI721_IMD_PRIO 0x00060000
  434. #define TSI721_IMD_TT 0x00180000
  435. #define TSI721_IMD_DTYPE 0xe0000000
  436. __le32 msg_info;
  437. #define TSI721_IMD_BCOUNT 0x00000ff8
  438. #define TSI721_IMD_SSIZE 0x0000f000
  439. #define TSI721_IMD_LETER 0x00030000
  440. #define TSI721_IMD_XMBOX 0x003c0000
  441. #define TSI721_IMD_MBOX 0x00c00000
  442. #define TSI721_IMD_CS 0x78000000
  443. #define TSI721_IMD_HO 0x80000000
  444. __le32 bufptr_lo;
  445. __le32 bufptr_hi;
  446. u32 reserved[12];
  447. } __aligned(64);
  448. /*
  449. * Outbound Messaging Descriptor
  450. */
  451. struct tsi721_omsg_desc {
  452. __le32 type_id;
  453. #define TSI721_OMD_DEVID 0x0000ffff
  454. #define TSI721_OMD_CRF 0x00010000
  455. #define TSI721_OMD_PRIO 0x00060000
  456. #define TSI721_OMD_IOF 0x08000000
  457. #define TSI721_OMD_DTYPE 0xe0000000
  458. #define TSI721_OMD_RSRVD 0x17f80000
  459. __le32 msg_info;
  460. #define TSI721_OMD_BCOUNT 0x00000ff8
  461. #define TSI721_OMD_SSIZE 0x0000f000
  462. #define TSI721_OMD_LETER 0x00030000
  463. #define TSI721_OMD_XMBOX 0x003c0000
  464. #define TSI721_OMD_MBOX 0x00c00000
  465. #define TSI721_OMD_TT 0x0c000000
  466. union {
  467. __le32 bufptr_lo; /* if DTYPE == 4 */
  468. __le32 next_lo; /* if DTYPE == 5 */
  469. };
  470. union {
  471. __le32 bufptr_hi; /* if DTYPE == 4 */
  472. __le32 next_hi; /* if DTYPE == 5 */
  473. };
  474. } __aligned(16);
  475. struct tsi721_dma_sts {
  476. __le64 desc_sts[8];
  477. } __aligned(64);
  478. struct tsi721_desc_sts_fifo {
  479. union {
  480. __le64 da64;
  481. struct {
  482. __le32 lo;
  483. __le32 hi;
  484. } da32;
  485. } stat[8];
  486. } __aligned(64);
  487. /* Descriptor types for BDMA and Messaging blocks */
  488. enum dma_dtype {
  489. DTYPE1 = 1, /* Data Transfer DMA Descriptor */
  490. DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */
  491. DTYPE3 = 3, /* Block Pointer DMA Descriptor */
  492. DTYPE4 = 4, /* Outbound Msg DMA Descriptor */
  493. DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
  494. DTYPE6 = 6 /* Inbound Messaging Descriptor */
  495. };
  496. enum dma_rtype {
  497. NREAD = 0,
  498. LAST_NWRITE_R = 1,
  499. ALL_NWRITE = 2,
  500. ALL_NWRITE_R = 3,
  501. MAINT_RD = 4,
  502. MAINT_WR = 5
  503. };
  504. /*
  505. * mport Driver Definitions
  506. */
  507. #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH
  508. #define TSI721_DMACH_MAINT 7 /* DMA channel for maint requests */
  509. #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
  510. #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
  511. #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
  512. enum tsi721_smsg_int_flag {
  513. SMSG_INT_NONE = 0x00000000,
  514. SMSG_INT_ECC_COR_CH = 0x000000ff,
  515. SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
  516. SMSG_INT_ECC_COR = 0x00020000,
  517. SMSG_INT_ECC_NCOR = 0x00040000,
  518. SMSG_INT_UNS_RSP = 0x00800000,
  519. SMSG_INT_ALL = 0x0006ffff
  520. };
  521. /* Structures */
  522. #ifdef CONFIG_RAPIDIO_DMA_ENGINE
  523. #define TSI721_BDMA_MAX_BCOUNT (TSI721_DMAD_BCOUNT1 + 1)
  524. struct tsi721_tx_desc {
  525. struct dma_async_tx_descriptor txd;
  526. u16 destid;
  527. /* low 64-bits of 66-bit RIO address */
  528. u64 rio_addr;
  529. /* upper 2-bits of 66-bit RIO address */
  530. u8 rio_addr_u;
  531. enum dma_rtype rtype;
  532. struct list_head desc_node;
  533. struct scatterlist *sg;
  534. unsigned int sg_len;
  535. enum dma_status status;
  536. };
  537. struct tsi721_bdma_chan {
  538. int id;
  539. void __iomem *regs;
  540. int bd_num; /* number of HW buffer descriptors */
  541. void *bd_base; /* start of DMA descriptors */
  542. dma_addr_t bd_phys;
  543. void *sts_base; /* start of DMA BD status FIFO */
  544. dma_addr_t sts_phys;
  545. int sts_size;
  546. u32 sts_rdptr;
  547. u32 wr_count;
  548. u32 wr_count_next;
  549. struct dma_chan dchan;
  550. struct tsi721_tx_desc *tx_desc;
  551. spinlock_t lock;
  552. struct tsi721_tx_desc *active_tx;
  553. struct list_head queue;
  554. struct list_head free_list;
  555. struct tasklet_struct tasklet;
  556. bool active;
  557. };
  558. #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
  559. struct tsi721_bdma_maint {
  560. int ch_id; /* BDMA channel number */
  561. int bd_num; /* number of buffer descriptors */
  562. void *bd_base; /* start of DMA descriptors */
  563. dma_addr_t bd_phys;
  564. void *sts_base; /* start of DMA BD status FIFO */
  565. dma_addr_t sts_phys;
  566. int sts_size;
  567. };
  568. struct tsi721_imsg_ring {
  569. u32 size;
  570. /* VA/PA of data buffers for incoming messages */
  571. void *buf_base;
  572. dma_addr_t buf_phys;
  573. /* VA/PA of circular free buffer list */
  574. void *imfq_base;
  575. dma_addr_t imfq_phys;
  576. /* VA/PA of Inbound message descriptors */
  577. void *imd_base;
  578. dma_addr_t imd_phys;
  579. /* Inbound Queue buffer pointers */
  580. void *imq_base[TSI721_IMSGD_RING_SIZE];
  581. u32 rx_slot;
  582. void *dev_id;
  583. u32 fq_wrptr;
  584. u32 desc_rdptr;
  585. spinlock_t lock;
  586. };
  587. struct tsi721_omsg_ring {
  588. u32 size;
  589. /* VA/PA of OB Msg descriptors */
  590. void *omd_base;
  591. dma_addr_t omd_phys;
  592. /* VA/PA of OB Msg data buffers */
  593. void *omq_base[TSI721_OMSGD_RING_SIZE];
  594. dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE];
  595. /* VA/PA of OB Msg descriptor status FIFO */
  596. void *sts_base;
  597. dma_addr_t sts_phys;
  598. u32 sts_size; /* # of allocated status entries */
  599. u32 sts_rdptr;
  600. u32 tx_slot;
  601. void *dev_id;
  602. u32 wr_count;
  603. spinlock_t lock;
  604. };
  605. enum tsi721_flags {
  606. TSI721_USING_MSI = (1 << 0),
  607. TSI721_USING_MSIX = (1 << 1),
  608. TSI721_IMSGID_SET = (1 << 2),
  609. };
  610. #ifdef CONFIG_PCI_MSI
  611. /*
  612. * MSI-X Table Entries (0 ... 69)
  613. */
  614. #define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
  615. #define TSI721_MSIX_DMACH_INT(x) (8 + (x))
  616. #define TSI721_MSIX_BDMA_INT 16
  617. #define TSI721_MSIX_OMSG_DONE(x) (17 + (x))
  618. #define TSI721_MSIX_OMSG_INT(x) (25 + (x))
  619. #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x))
  620. #define TSI721_MSIX_IMSG_INT(x) (41 + (x))
  621. #define TSI721_MSIX_MSG_INT 49
  622. #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x))
  623. #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x))
  624. #define TSI721_MSIX_SR2PC_INT 66
  625. #define TSI721_MSIX_PC2SR_INT 67
  626. #define TSI721_MSIX_SRIO_MAC_INT 68
  627. #define TSI721_MSIX_I2C_INT 69
  628. /* MSI-X vector and init table entry indexes */
  629. enum tsi721_msix_vect {
  630. TSI721_VECT_IDB,
  631. TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */
  632. TSI721_VECT_OMB0_DONE,
  633. TSI721_VECT_OMB1_DONE,
  634. TSI721_VECT_OMB2_DONE,
  635. TSI721_VECT_OMB3_DONE,
  636. TSI721_VECT_OMB0_INT,
  637. TSI721_VECT_OMB1_INT,
  638. TSI721_VECT_OMB2_INT,
  639. TSI721_VECT_OMB3_INT,
  640. TSI721_VECT_IMB0_RCV,
  641. TSI721_VECT_IMB1_RCV,
  642. TSI721_VECT_IMB2_RCV,
  643. TSI721_VECT_IMB3_RCV,
  644. TSI721_VECT_IMB0_INT,
  645. TSI721_VECT_IMB1_INT,
  646. TSI721_VECT_IMB2_INT,
  647. TSI721_VECT_IMB3_INT,
  648. #ifdef CONFIG_RAPIDIO_DMA_ENGINE
  649. TSI721_VECT_DMA0_DONE,
  650. TSI721_VECT_DMA1_DONE,
  651. TSI721_VECT_DMA2_DONE,
  652. TSI721_VECT_DMA3_DONE,
  653. TSI721_VECT_DMA4_DONE,
  654. TSI721_VECT_DMA5_DONE,
  655. TSI721_VECT_DMA6_DONE,
  656. TSI721_VECT_DMA7_DONE,
  657. TSI721_VECT_DMA0_INT,
  658. TSI721_VECT_DMA1_INT,
  659. TSI721_VECT_DMA2_INT,
  660. TSI721_VECT_DMA3_INT,
  661. TSI721_VECT_DMA4_INT,
  662. TSI721_VECT_DMA5_INT,
  663. TSI721_VECT_DMA6_INT,
  664. TSI721_VECT_DMA7_INT,
  665. #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
  666. TSI721_VECT_MAX
  667. };
  668. #define IRQ_DEVICE_NAME_MAX 64
  669. struct msix_irq {
  670. u16 vector;
  671. char irq_name[IRQ_DEVICE_NAME_MAX];
  672. };
  673. #endif /* CONFIG_PCI_MSI */
  674. struct tsi721_ib_win_mapping {
  675. struct list_head node;
  676. dma_addr_t lstart;
  677. };
  678. struct tsi721_ib_win {
  679. u64 rstart;
  680. u32 size;
  681. dma_addr_t lstart;
  682. bool active;
  683. bool xlat;
  684. struct list_head mappings;
  685. };
  686. struct tsi721_obw_bar {
  687. u64 base;
  688. u64 size;
  689. u64 free;
  690. };
  691. struct tsi721_ob_win {
  692. u64 base;
  693. u32 size;
  694. u16 destid;
  695. u64 rstart;
  696. bool active;
  697. struct tsi721_obw_bar *pbar;
  698. };
  699. struct tsi721_device {
  700. struct pci_dev *pdev;
  701. struct rio_mport mport;
  702. u32 flags;
  703. void __iomem *regs;
  704. #ifdef CONFIG_PCI_MSI
  705. struct msix_irq msix[TSI721_VECT_MAX];
  706. #endif
  707. /* Doorbells */
  708. void __iomem *odb_base;
  709. void *idb_base;
  710. dma_addr_t idb_dma;
  711. struct work_struct idb_work;
  712. u32 db_discard_count;
  713. /* Inbound Port-Write */
  714. struct work_struct pw_work;
  715. struct kfifo pw_fifo;
  716. spinlock_t pw_fifo_lock;
  717. u32 pw_discard_count;
  718. /* BDMA Engine */
  719. struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
  720. #ifdef CONFIG_RAPIDIO_DMA_ENGINE
  721. struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
  722. #endif
  723. /* Inbound Messaging */
  724. int imsg_init[TSI721_IMSG_CHNUM];
  725. struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM];
  726. /* Outbound Messaging */
  727. int omsg_init[TSI721_OMSG_CHNUM];
  728. struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];
  729. /* Inbound Mapping Windows */
  730. struct tsi721_ib_win ib_win[TSI721_IBWIN_NUM];
  731. int ibwin_cnt;
  732. /* Outbound Mapping Windows */
  733. struct tsi721_obw_bar p2r_bar[2];
  734. struct tsi721_ob_win ob_win[TSI721_OBWIN_NUM];
  735. int obwin_cnt;
  736. };
  737. #ifdef CONFIG_RAPIDIO_DMA_ENGINE
  738. extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
  739. extern int tsi721_register_dma(struct tsi721_device *priv);
  740. extern void tsi721_unregister_dma(struct tsi721_device *priv);
  741. extern void tsi721_dma_stop_all(struct tsi721_device *priv);
  742. #else
  743. #define tsi721_dma_stop_all(priv) do {} while (0)
  744. #define tsi721_unregister_dma(priv) do {} while (0)
  745. #endif
  746. #endif