pwm-vt8500.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/pwm/pwm-vt8500.c
  4. *
  5. * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  6. * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/pwm.h>
  15. #include <linux/delay.h>
  16. #include <linux/clk.h>
  17. #include <asm/div64.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_address.h>
  21. /*
  22. * SoC architecture allocates register space for 4 PWMs but only
  23. * 2 are currently implemented.
  24. */
  25. #define VT8500_NR_PWMS 2
  26. #define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
  27. #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
  28. #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
  29. #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
  30. #define REG_STATUS 0x40
  31. #define CTRL_ENABLE BIT(0)
  32. #define CTRL_INVERT BIT(1)
  33. #define CTRL_AUTOLOAD BIT(2)
  34. #define CTRL_STOP_IMM BIT(3)
  35. #define CTRL_LOAD_PRESCALE BIT(4)
  36. #define CTRL_LOAD_PERIOD BIT(5)
  37. #define STATUS_CTRL_UPDATE BIT(0)
  38. #define STATUS_SCALAR_UPDATE BIT(1)
  39. #define STATUS_PERIOD_UPDATE BIT(2)
  40. #define STATUS_DUTY_UPDATE BIT(3)
  41. #define STATUS_ALL_UPDATE 0x0F
  42. struct vt8500_chip {
  43. struct pwm_chip chip;
  44. void __iomem *base;
  45. struct clk *clk;
  46. };
  47. #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
  48. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  49. static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
  50. {
  51. int loops = msecs_to_loops(10);
  52. u32 mask = bitmask << (nr << 8);
  53. while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
  54. cpu_relax();
  55. if (unlikely(!loops))
  56. dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
  57. mask);
  58. }
  59. static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  60. int duty_ns, int period_ns)
  61. {
  62. struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
  63. unsigned long long c;
  64. unsigned long period_cycles, prescale, pv, dc;
  65. int err;
  66. u32 val;
  67. err = clk_enable(vt8500->clk);
  68. if (err < 0) {
  69. dev_err(chip->dev, "failed to enable clock\n");
  70. return err;
  71. }
  72. c = clk_get_rate(vt8500->clk);
  73. c = c * period_ns;
  74. do_div(c, 1000000000);
  75. period_cycles = c;
  76. if (period_cycles < 1)
  77. period_cycles = 1;
  78. prescale = (period_cycles - 1) / 4096;
  79. pv = period_cycles / (prescale + 1) - 1;
  80. if (pv > 4095)
  81. pv = 4095;
  82. if (prescale > 1023) {
  83. clk_disable(vt8500->clk);
  84. return -EINVAL;
  85. }
  86. c = (unsigned long long)pv * duty_ns;
  87. do_div(c, period_ns);
  88. dc = c;
  89. writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
  90. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
  91. writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
  92. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
  93. writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
  94. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
  95. val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
  96. val |= CTRL_AUTOLOAD;
  97. writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
  98. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
  99. clk_disable(vt8500->clk);
  100. return 0;
  101. }
  102. static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  103. {
  104. struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
  105. int err;
  106. u32 val;
  107. err = clk_enable(vt8500->clk);
  108. if (err < 0) {
  109. dev_err(chip->dev, "failed to enable clock\n");
  110. return err;
  111. }
  112. val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
  113. val |= CTRL_ENABLE;
  114. writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
  115. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
  116. return 0;
  117. }
  118. static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  119. {
  120. struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
  121. u32 val;
  122. val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
  123. val &= ~CTRL_ENABLE;
  124. writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
  125. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
  126. clk_disable(vt8500->clk);
  127. }
  128. static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
  129. struct pwm_device *pwm,
  130. enum pwm_polarity polarity)
  131. {
  132. struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
  133. u32 val;
  134. val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
  135. if (polarity == PWM_POLARITY_INVERSED)
  136. val |= CTRL_INVERT;
  137. else
  138. val &= ~CTRL_INVERT;
  139. writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
  140. pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
  141. return 0;
  142. }
  143. static const struct pwm_ops vt8500_pwm_ops = {
  144. .enable = vt8500_pwm_enable,
  145. .disable = vt8500_pwm_disable,
  146. .config = vt8500_pwm_config,
  147. .set_polarity = vt8500_pwm_set_polarity,
  148. .owner = THIS_MODULE,
  149. };
  150. static const struct of_device_id vt8500_pwm_dt_ids[] = {
  151. { .compatible = "via,vt8500-pwm", },
  152. { /* Sentinel */ }
  153. };
  154. MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
  155. static int vt8500_pwm_probe(struct platform_device *pdev)
  156. {
  157. struct vt8500_chip *chip;
  158. struct resource *r;
  159. struct device_node *np = pdev->dev.of_node;
  160. int ret;
  161. if (!np) {
  162. dev_err(&pdev->dev, "invalid devicetree node\n");
  163. return -EINVAL;
  164. }
  165. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  166. if (chip == NULL)
  167. return -ENOMEM;
  168. chip->chip.dev = &pdev->dev;
  169. chip->chip.ops = &vt8500_pwm_ops;
  170. chip->chip.of_xlate = of_pwm_xlate_with_flags;
  171. chip->chip.of_pwm_n_cells = 3;
  172. chip->chip.base = -1;
  173. chip->chip.npwm = VT8500_NR_PWMS;
  174. chip->clk = devm_clk_get(&pdev->dev, NULL);
  175. if (IS_ERR(chip->clk)) {
  176. dev_err(&pdev->dev, "clock source not specified\n");
  177. return PTR_ERR(chip->clk);
  178. }
  179. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  180. chip->base = devm_ioremap_resource(&pdev->dev, r);
  181. if (IS_ERR(chip->base))
  182. return PTR_ERR(chip->base);
  183. ret = clk_prepare(chip->clk);
  184. if (ret < 0) {
  185. dev_err(&pdev->dev, "failed to prepare clock\n");
  186. return ret;
  187. }
  188. ret = pwmchip_add(&chip->chip);
  189. if (ret < 0) {
  190. dev_err(&pdev->dev, "failed to add PWM chip\n");
  191. clk_unprepare(chip->clk);
  192. return ret;
  193. }
  194. platform_set_drvdata(pdev, chip);
  195. return ret;
  196. }
  197. static int vt8500_pwm_remove(struct platform_device *pdev)
  198. {
  199. struct vt8500_chip *chip;
  200. chip = platform_get_drvdata(pdev);
  201. if (chip == NULL)
  202. return -ENODEV;
  203. clk_unprepare(chip->clk);
  204. return pwmchip_remove(&chip->chip);
  205. }
  206. static struct platform_driver vt8500_pwm_driver = {
  207. .probe = vt8500_pwm_probe,
  208. .remove = vt8500_pwm_remove,
  209. .driver = {
  210. .name = "vt8500-pwm",
  211. .of_match_table = vt8500_pwm_dt_ids,
  212. },
  213. };
  214. module_platform_driver(vt8500_pwm_driver);
  215. MODULE_DESCRIPTION("VT8500 PWM Driver");
  216. MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
  217. MODULE_LICENSE("GPL v2");