pwm-tegra.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * drivers/pwm/pwm-tegra.c
  4. *
  5. * Tegra pulse-width-modulation controller driver
  6. *
  7. * Copyright (c) 2010-2020, NVIDIA Corporation.
  8. * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
  9. *
  10. * Overview of Tegra Pulse Width Modulator Register:
  11. * 1. 13-bit: Frequency division (SCALE)
  12. * 2. 8-bit : Pulse division (DUTY)
  13. * 3. 1-bit : Enable bit
  14. *
  15. * The PWM clock frequency is divided by 256 before subdividing it based
  16. * on the programmable frequency division value to generate the required
  17. * frequency for PWM output. The maximum output frequency that can be
  18. * achieved is (max rate of source clock) / 256.
  19. * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
  20. * 408 MHz/256 = 1.6 MHz.
  21. * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
  22. *
  23. * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
  24. * To achieve 100% duty cycle, program Bit [24] of this register to
  25. * 1’b1. In which case the other bits [23:16] are set to don't care.
  26. *
  27. * Limitations:
  28. * - When PWM is disabled, the output is driven to inactive.
  29. * - It does not allow the current PWM period to complete and
  30. * stops abruptly.
  31. *
  32. * - If the register is reconfigured while PWM is running,
  33. * it does not complete the currently running period.
  34. *
  35. * - If the user input duty is beyond acceptible limits,
  36. * -EINVAL is returned.
  37. */
  38. #include <linux/clk.h>
  39. #include <linux/err.h>
  40. #include <linux/io.h>
  41. #include <linux/module.h>
  42. #include <linux/of.h>
  43. #include <linux/of_device.h>
  44. #include <linux/pwm.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/pinctrl/consumer.h>
  47. #include <linux/slab.h>
  48. #include <linux/reset.h>
  49. #define PWM_ENABLE (1 << 31)
  50. #define PWM_DUTY_WIDTH 8
  51. #define PWM_DUTY_SHIFT 16
  52. #define PWM_SCALE_WIDTH 13
  53. #define PWM_SCALE_SHIFT 0
  54. struct tegra_pwm_soc {
  55. unsigned int num_channels;
  56. /* Maximum IP frequency for given SoCs */
  57. unsigned long max_frequency;
  58. };
  59. struct tegra_pwm_chip {
  60. struct pwm_chip chip;
  61. struct device *dev;
  62. struct clk *clk;
  63. struct reset_control*rst;
  64. unsigned long clk_rate;
  65. unsigned long min_period_ns;
  66. void __iomem *regs;
  67. const struct tegra_pwm_soc *soc;
  68. };
  69. static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
  70. {
  71. return container_of(chip, struct tegra_pwm_chip, chip);
  72. }
  73. static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
  74. {
  75. return readl(chip->regs + (num << 4));
  76. }
  77. static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
  78. unsigned long val)
  79. {
  80. writel(val, chip->regs + (num << 4));
  81. }
  82. static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  83. int duty_ns, int period_ns)
  84. {
  85. struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
  86. unsigned long long c = duty_ns, hz;
  87. unsigned long rate, required_clk_rate;
  88. u32 val = 0;
  89. int err;
  90. /*
  91. * Convert from duty_ns / period_ns to a fixed number of duty ticks
  92. * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
  93. * nearest integer during division.
  94. */
  95. c *= (1 << PWM_DUTY_WIDTH);
  96. c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
  97. val = (u32)c << PWM_DUTY_SHIFT;
  98. /*
  99. * min period = max clock limit >> PWM_DUTY_WIDTH
  100. */
  101. if (period_ns < pc->min_period_ns)
  102. return -EINVAL;
  103. /*
  104. * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
  105. * cycles at the PWM clock rate will take period_ns nanoseconds.
  106. *
  107. * num_channels: If single instance of PWM controller has multiple
  108. * channels (e.g. Tegra210 or older) then it is not possible to
  109. * configure separate clock rates to each of the channels, in such
  110. * case the value stored during probe will be referred.
  111. *
  112. * If every PWM controller instance has one channel respectively, i.e.
  113. * nums_channels == 1 then only the clock rate can be modified
  114. * dynamically (e.g. Tegra186 or Tegra194).
  115. */
  116. if (pc->soc->num_channels == 1) {
  117. /*
  118. * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
  119. * with the maximum possible rate that the controller can
  120. * provide. Any further lower value can be derived by setting
  121. * PFM bits[0:12].
  122. *
  123. * required_clk_rate is a reference rate for source clock and
  124. * it is derived based on user requested period. By setting the
  125. * source clock rate as required_clk_rate, PWM controller will
  126. * be able to configure the requested period.
  127. */
  128. required_clk_rate =
  129. (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
  130. err = clk_set_rate(pc->clk, required_clk_rate);
  131. if (err < 0)
  132. return -EINVAL;
  133. /* Store the new rate for further references */
  134. pc->clk_rate = clk_get_rate(pc->clk);
  135. }
  136. rate = pc->clk_rate >> PWM_DUTY_WIDTH;
  137. /* Consider precision in PWM_SCALE_WIDTH rate calculation */
  138. hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
  139. rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
  140. /*
  141. * Since the actual PWM divider is the register's frequency divider
  142. * field plus 1, we need to decrement to get the correct value to
  143. * write to the register.
  144. */
  145. if (rate > 0)
  146. rate--;
  147. /*
  148. * Make sure that the rate will fit in the register's frequency
  149. * divider field.
  150. */
  151. if (rate >> PWM_SCALE_WIDTH)
  152. return -EINVAL;
  153. val |= rate << PWM_SCALE_SHIFT;
  154. /*
  155. * If the PWM channel is disabled, make sure to turn on the clock
  156. * before writing the register. Otherwise, keep it enabled.
  157. */
  158. if (!pwm_is_enabled(pwm)) {
  159. err = clk_prepare_enable(pc->clk);
  160. if (err < 0)
  161. return err;
  162. } else
  163. val |= PWM_ENABLE;
  164. pwm_writel(pc, pwm->hwpwm, val);
  165. /*
  166. * If the PWM is not enabled, turn the clock off again to save power.
  167. */
  168. if (!pwm_is_enabled(pwm))
  169. clk_disable_unprepare(pc->clk);
  170. return 0;
  171. }
  172. static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  173. {
  174. struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
  175. int rc = 0;
  176. u32 val;
  177. rc = clk_prepare_enable(pc->clk);
  178. if (rc < 0)
  179. return rc;
  180. val = pwm_readl(pc, pwm->hwpwm);
  181. val |= PWM_ENABLE;
  182. pwm_writel(pc, pwm->hwpwm, val);
  183. return 0;
  184. }
  185. static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  186. {
  187. struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
  188. u32 val;
  189. val = pwm_readl(pc, pwm->hwpwm);
  190. val &= ~PWM_ENABLE;
  191. pwm_writel(pc, pwm->hwpwm, val);
  192. clk_disable_unprepare(pc->clk);
  193. }
  194. static const struct pwm_ops tegra_pwm_ops = {
  195. .config = tegra_pwm_config,
  196. .enable = tegra_pwm_enable,
  197. .disable = tegra_pwm_disable,
  198. .owner = THIS_MODULE,
  199. };
  200. static int tegra_pwm_probe(struct platform_device *pdev)
  201. {
  202. struct tegra_pwm_chip *pwm;
  203. struct resource *r;
  204. int ret;
  205. pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
  206. if (!pwm)
  207. return -ENOMEM;
  208. pwm->soc = of_device_get_match_data(&pdev->dev);
  209. pwm->dev = &pdev->dev;
  210. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  211. pwm->regs = devm_ioremap_resource(&pdev->dev, r);
  212. if (IS_ERR(pwm->regs))
  213. return PTR_ERR(pwm->regs);
  214. platform_set_drvdata(pdev, pwm);
  215. pwm->clk = devm_clk_get(&pdev->dev, NULL);
  216. if (IS_ERR(pwm->clk))
  217. return PTR_ERR(pwm->clk);
  218. /* Set maximum frequency of the IP */
  219. ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
  220. if (ret < 0) {
  221. dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
  222. return ret;
  223. }
  224. /*
  225. * The requested and configured frequency may differ due to
  226. * clock register resolutions. Get the configured frequency
  227. * so that PWM period can be calculated more accurately.
  228. */
  229. pwm->clk_rate = clk_get_rate(pwm->clk);
  230. /* Set minimum limit of PWM period for the IP */
  231. pwm->min_period_ns =
  232. (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
  233. pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
  234. if (IS_ERR(pwm->rst)) {
  235. ret = PTR_ERR(pwm->rst);
  236. dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
  237. return ret;
  238. }
  239. reset_control_deassert(pwm->rst);
  240. pwm->chip.dev = &pdev->dev;
  241. pwm->chip.ops = &tegra_pwm_ops;
  242. pwm->chip.base = -1;
  243. pwm->chip.npwm = pwm->soc->num_channels;
  244. ret = pwmchip_add(&pwm->chip);
  245. if (ret < 0) {
  246. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  247. reset_control_assert(pwm->rst);
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. static int tegra_pwm_remove(struct platform_device *pdev)
  253. {
  254. struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
  255. int err;
  256. if (WARN_ON(!pc))
  257. return -ENODEV;
  258. err = clk_prepare_enable(pc->clk);
  259. if (err < 0)
  260. return err;
  261. reset_control_assert(pc->rst);
  262. clk_disable_unprepare(pc->clk);
  263. return pwmchip_remove(&pc->chip);
  264. }
  265. #ifdef CONFIG_PM_SLEEP
  266. static int tegra_pwm_suspend(struct device *dev)
  267. {
  268. return pinctrl_pm_select_sleep_state(dev);
  269. }
  270. static int tegra_pwm_resume(struct device *dev)
  271. {
  272. return pinctrl_pm_select_default_state(dev);
  273. }
  274. #endif
  275. static const struct tegra_pwm_soc tegra20_pwm_soc = {
  276. .num_channels = 4,
  277. .max_frequency = 48000000UL,
  278. };
  279. static const struct tegra_pwm_soc tegra186_pwm_soc = {
  280. .num_channels = 1,
  281. .max_frequency = 102000000UL,
  282. };
  283. static const struct tegra_pwm_soc tegra194_pwm_soc = {
  284. .num_channels = 1,
  285. .max_frequency = 408000000UL,
  286. };
  287. static const struct of_device_id tegra_pwm_of_match[] = {
  288. { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
  289. { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
  290. { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
  291. { }
  292. };
  293. MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
  294. static const struct dev_pm_ops tegra_pwm_pm_ops = {
  295. SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
  296. };
  297. static struct platform_driver tegra_pwm_driver = {
  298. .driver = {
  299. .name = "tegra-pwm",
  300. .of_match_table = tegra_pwm_of_match,
  301. .pm = &tegra_pwm_pm_ops,
  302. },
  303. .probe = tegra_pwm_probe,
  304. .remove = tegra_pwm_remove,
  305. };
  306. module_platform_driver(tegra_pwm_driver);
  307. MODULE_LICENSE("GPL");
  308. MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
  309. MODULE_DESCRIPTION("Tegra PWM controller driver");
  310. MODULE_ALIAS("platform:tegra-pwm");