pwm-sun4i.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Allwinner sun4i Pulse Width Modulation Controller
  4. *
  5. * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
  6. *
  7. * Limitations:
  8. * - When outputing the source clock directly, the PWM logic will be bypassed
  9. * and the currently running period is not guaranteed to be completed
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/reset.h>
  23. #include <linux/slab.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/time.h>
  26. #define PWM_CTRL_REG 0x0
  27. #define PWM_CH_PRD_BASE 0x4
  28. #define PWM_CH_PRD_OFFSET 0x4
  29. #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  30. #define PWMCH_OFFSET 15
  31. #define PWM_PRESCAL_MASK GENMASK(3, 0)
  32. #define PWM_PRESCAL_OFF 0
  33. #define PWM_EN BIT(4)
  34. #define PWM_ACT_STATE BIT(5)
  35. #define PWM_CLK_GATING BIT(6)
  36. #define PWM_MODE BIT(7)
  37. #define PWM_PULSE BIT(8)
  38. #define PWM_BYPASS BIT(9)
  39. #define PWM_RDY_BASE 28
  40. #define PWM_RDY_OFFSET 1
  41. #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  42. #define PWM_PRD(prd) (((prd) - 1) << 16)
  43. #define PWM_PRD_MASK GENMASK(15, 0)
  44. #define PWM_DTY_MASK GENMASK(15, 0)
  45. #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
  46. #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
  47. #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
  48. #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
  49. static const u32 prescaler_table[] = {
  50. 120,
  51. 180,
  52. 240,
  53. 360,
  54. 480,
  55. 0,
  56. 0,
  57. 0,
  58. 12000,
  59. 24000,
  60. 36000,
  61. 48000,
  62. 72000,
  63. 0,
  64. 0,
  65. 0, /* Actually 1 but tested separately */
  66. };
  67. struct sun4i_pwm_data {
  68. bool has_prescaler_bypass;
  69. bool has_direct_mod_clk_output;
  70. unsigned int npwm;
  71. };
  72. struct sun4i_pwm_chip {
  73. struct pwm_chip chip;
  74. struct clk *bus_clk;
  75. struct clk *clk;
  76. struct reset_control *rst;
  77. void __iomem *base;
  78. spinlock_t ctrl_lock;
  79. const struct sun4i_pwm_data *data;
  80. unsigned long next_period[2];
  81. };
  82. static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
  83. {
  84. return container_of(chip, struct sun4i_pwm_chip, chip);
  85. }
  86. static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
  87. unsigned long offset)
  88. {
  89. return readl(chip->base + offset);
  90. }
  91. static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
  92. u32 val, unsigned long offset)
  93. {
  94. writel(val, chip->base + offset);
  95. }
  96. static void sun4i_pwm_get_state(struct pwm_chip *chip,
  97. struct pwm_device *pwm,
  98. struct pwm_state *state)
  99. {
  100. struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
  101. u64 clk_rate, tmp;
  102. u32 val;
  103. unsigned int prescaler;
  104. clk_rate = clk_get_rate(sun4i_pwm->clk);
  105. val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  106. /*
  107. * PWM chapter in H6 manual has a diagram which explains that if bypass
  108. * bit is set, no other setting has any meaning. Even more, experiment
  109. * proved that also enable bit is ignored in this case.
  110. */
  111. if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
  112. sun4i_pwm->data->has_direct_mod_clk_output) {
  113. state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
  114. state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
  115. state->polarity = PWM_POLARITY_NORMAL;
  116. state->enabled = true;
  117. return;
  118. }
  119. if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
  120. sun4i_pwm->data->has_prescaler_bypass)
  121. prescaler = 1;
  122. else
  123. prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
  124. if (prescaler == 0)
  125. return;
  126. if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
  127. state->polarity = PWM_POLARITY_NORMAL;
  128. else
  129. state->polarity = PWM_POLARITY_INVERSED;
  130. if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
  131. BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
  132. state->enabled = true;
  133. else
  134. state->enabled = false;
  135. val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
  136. tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
  137. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  138. tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
  139. state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  140. }
  141. static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
  142. const struct pwm_state *state,
  143. u32 *dty, u32 *prd, unsigned int *prsclr,
  144. bool *bypass)
  145. {
  146. u64 clk_rate, div = 0;
  147. unsigned int prescaler = 0;
  148. clk_rate = clk_get_rate(sun4i_pwm->clk);
  149. *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
  150. state->enabled &&
  151. (state->period * clk_rate >= NSEC_PER_SEC) &&
  152. (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
  153. (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
  154. /* Skip calculation of other parameters if we bypass them */
  155. if (*bypass)
  156. return 0;
  157. if (sun4i_pwm->data->has_prescaler_bypass) {
  158. /* First, test without any prescaler when available */
  159. prescaler = PWM_PRESCAL_MASK;
  160. /*
  161. * When not using any prescaler, the clock period in nanoseconds
  162. * is not an integer so round it half up instead of
  163. * truncating to get less surprising values.
  164. */
  165. div = clk_rate * state->period + NSEC_PER_SEC / 2;
  166. do_div(div, NSEC_PER_SEC);
  167. if (div - 1 > PWM_PRD_MASK)
  168. prescaler = 0;
  169. }
  170. if (prescaler == 0) {
  171. /* Go up from the first divider */
  172. for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
  173. unsigned int pval = prescaler_table[prescaler];
  174. if (!pval)
  175. continue;
  176. div = clk_rate;
  177. do_div(div, pval);
  178. div = div * state->period;
  179. do_div(div, NSEC_PER_SEC);
  180. if (div - 1 <= PWM_PRD_MASK)
  181. break;
  182. }
  183. if (div - 1 > PWM_PRD_MASK)
  184. return -EINVAL;
  185. }
  186. *prd = div;
  187. div *= state->duty_cycle;
  188. do_div(div, state->period);
  189. *dty = div;
  190. *prsclr = prescaler;
  191. return 0;
  192. }
  193. static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  194. const struct pwm_state *state)
  195. {
  196. struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
  197. struct pwm_state cstate;
  198. u32 ctrl, duty = 0, period = 0, val;
  199. int ret;
  200. unsigned int delay_us, prescaler = 0;
  201. unsigned long now;
  202. bool bypass;
  203. pwm_get_state(pwm, &cstate);
  204. if (!cstate.enabled) {
  205. ret = clk_prepare_enable(sun4i_pwm->clk);
  206. if (ret) {
  207. dev_err(chip->dev, "failed to enable PWM clock\n");
  208. return ret;
  209. }
  210. }
  211. ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
  212. &bypass);
  213. if (ret) {
  214. dev_err(chip->dev, "period exceeds the maximum value\n");
  215. if (!cstate.enabled)
  216. clk_disable_unprepare(sun4i_pwm->clk);
  217. return ret;
  218. }
  219. spin_lock(&sun4i_pwm->ctrl_lock);
  220. ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  221. if (sun4i_pwm->data->has_direct_mod_clk_output) {
  222. if (bypass) {
  223. ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
  224. /* We can skip other parameter */
  225. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  226. spin_unlock(&sun4i_pwm->ctrl_lock);
  227. return 0;
  228. }
  229. ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
  230. }
  231. if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
  232. /* Prescaler changed, the clock has to be gated */
  233. ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  234. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  235. ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
  236. ctrl |= BIT_CH(prescaler, pwm->hwpwm);
  237. }
  238. val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
  239. sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
  240. sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
  241. nsecs_to_jiffies(cstate.period + 1000);
  242. if (state->polarity != PWM_POLARITY_NORMAL)
  243. ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
  244. else
  245. ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
  246. ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  247. if (state->enabled)
  248. ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
  249. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  250. spin_unlock(&sun4i_pwm->ctrl_lock);
  251. if (state->enabled)
  252. return 0;
  253. /* We need a full period to elapse before disabling the channel. */
  254. now = jiffies;
  255. if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
  256. delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
  257. now);
  258. if ((delay_us / 500) > MAX_UDELAY_MS)
  259. msleep(delay_us / 1000 + 1);
  260. else
  261. usleep_range(delay_us, delay_us * 2);
  262. }
  263. spin_lock(&sun4i_pwm->ctrl_lock);
  264. ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
  265. ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
  266. ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
  267. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
  268. spin_unlock(&sun4i_pwm->ctrl_lock);
  269. clk_disable_unprepare(sun4i_pwm->clk);
  270. return 0;
  271. }
  272. static const struct pwm_ops sun4i_pwm_ops = {
  273. .apply = sun4i_pwm_apply,
  274. .get_state = sun4i_pwm_get_state,
  275. .owner = THIS_MODULE,
  276. };
  277. static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
  278. .has_prescaler_bypass = false,
  279. .npwm = 2,
  280. };
  281. static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
  282. .has_prescaler_bypass = true,
  283. .npwm = 2,
  284. };
  285. static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
  286. .has_prescaler_bypass = true,
  287. .npwm = 1,
  288. };
  289. static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
  290. .has_prescaler_bypass = true,
  291. .has_direct_mod_clk_output = true,
  292. .npwm = 1,
  293. };
  294. static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
  295. .has_prescaler_bypass = true,
  296. .has_direct_mod_clk_output = true,
  297. .npwm = 2,
  298. };
  299. static const struct of_device_id sun4i_pwm_dt_ids[] = {
  300. {
  301. .compatible = "allwinner,sun4i-a10-pwm",
  302. .data = &sun4i_pwm_dual_nobypass,
  303. }, {
  304. .compatible = "allwinner,sun5i-a10s-pwm",
  305. .data = &sun4i_pwm_dual_bypass,
  306. }, {
  307. .compatible = "allwinner,sun5i-a13-pwm",
  308. .data = &sun4i_pwm_single_bypass,
  309. }, {
  310. .compatible = "allwinner,sun7i-a20-pwm",
  311. .data = &sun4i_pwm_dual_bypass,
  312. }, {
  313. .compatible = "allwinner,sun8i-h3-pwm",
  314. .data = &sun4i_pwm_single_bypass,
  315. }, {
  316. .compatible = "allwinner,sun50i-a64-pwm",
  317. .data = &sun50i_a64_pwm_data,
  318. }, {
  319. .compatible = "allwinner,sun50i-h6-pwm",
  320. .data = &sun50i_h6_pwm_data,
  321. }, {
  322. /* sentinel */
  323. },
  324. };
  325. MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
  326. static int sun4i_pwm_probe(struct platform_device *pdev)
  327. {
  328. struct sun4i_pwm_chip *pwm;
  329. struct resource *res;
  330. int ret;
  331. pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
  332. if (!pwm)
  333. return -ENOMEM;
  334. pwm->data = of_device_get_match_data(&pdev->dev);
  335. if (!pwm->data)
  336. return -ENODEV;
  337. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. pwm->base = devm_ioremap_resource(&pdev->dev, res);
  339. if (IS_ERR(pwm->base))
  340. return PTR_ERR(pwm->base);
  341. /*
  342. * All hardware variants need a source clock that is divided and
  343. * then feeds the counter that defines the output wave form. In the
  344. * device tree this clock is either unnamed or called "mod".
  345. * Some variants (e.g. H6) need another clock to access the
  346. * hardware registers; this is called "bus".
  347. * So we request "mod" first (and ignore the corner case that a
  348. * parent provides a "mod" clock while the right one would be the
  349. * unnamed one of the PWM device) and if this is not found we fall
  350. * back to the first clock of the PWM.
  351. */
  352. pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
  353. if (IS_ERR(pwm->clk))
  354. return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
  355. "get mod clock failed\n");
  356. if (!pwm->clk) {
  357. pwm->clk = devm_clk_get(&pdev->dev, NULL);
  358. if (IS_ERR(pwm->clk))
  359. return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
  360. "get unnamed clock failed\n");
  361. }
  362. pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
  363. if (IS_ERR(pwm->bus_clk))
  364. return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
  365. "get bus clock failed\n");
  366. pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  367. if (IS_ERR(pwm->rst))
  368. return dev_err_probe(&pdev->dev, PTR_ERR(pwm->rst),
  369. "get reset failed\n");
  370. /* Deassert reset */
  371. ret = reset_control_deassert(pwm->rst);
  372. if (ret) {
  373. dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
  374. ERR_PTR(ret));
  375. return ret;
  376. }
  377. /*
  378. * We're keeping the bus clock on for the sake of simplicity.
  379. * Actually it only needs to be on for hardware register accesses.
  380. */
  381. ret = clk_prepare_enable(pwm->bus_clk);
  382. if (ret) {
  383. dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
  384. ERR_PTR(ret));
  385. goto err_bus;
  386. }
  387. pwm->chip.dev = &pdev->dev;
  388. pwm->chip.ops = &sun4i_pwm_ops;
  389. pwm->chip.base = -1;
  390. pwm->chip.npwm = pwm->data->npwm;
  391. pwm->chip.of_xlate = of_pwm_xlate_with_flags;
  392. pwm->chip.of_pwm_n_cells = 3;
  393. spin_lock_init(&pwm->ctrl_lock);
  394. ret = pwmchip_add(&pwm->chip);
  395. if (ret < 0) {
  396. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  397. goto err_pwm_add;
  398. }
  399. platform_set_drvdata(pdev, pwm);
  400. return 0;
  401. err_pwm_add:
  402. clk_disable_unprepare(pwm->bus_clk);
  403. err_bus:
  404. reset_control_assert(pwm->rst);
  405. return ret;
  406. }
  407. static int sun4i_pwm_remove(struct platform_device *pdev)
  408. {
  409. struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
  410. int ret;
  411. ret = pwmchip_remove(&pwm->chip);
  412. if (ret)
  413. return ret;
  414. clk_disable_unprepare(pwm->bus_clk);
  415. reset_control_assert(pwm->rst);
  416. return 0;
  417. }
  418. static struct platform_driver sun4i_pwm_driver = {
  419. .driver = {
  420. .name = "sun4i-pwm",
  421. .of_match_table = sun4i_pwm_dt_ids,
  422. },
  423. .probe = sun4i_pwm_probe,
  424. .remove = sun4i_pwm_remove,
  425. };
  426. module_platform_driver(sun4i_pwm_driver);
  427. MODULE_ALIAS("platform:sun4i-pwm");
  428. MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
  429. MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
  430. MODULE_LICENSE("GPL v2");