pwm-stm32.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2016
  4. *
  5. * Author: Gerald Baeza <gerald.baeza@st.com>
  6. *
  7. * Inspired by timer-stm32.c from Maxime Coquelin
  8. * pwm-atmel.c from Bo Shen
  9. */
  10. #include <linux/bitfield.h>
  11. #include <linux/mfd/stm32-timers.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/pinctrl/consumer.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pwm.h>
  17. #define CCMR_CHANNEL_SHIFT 8
  18. #define CCMR_CHANNEL_MASK 0xFF
  19. #define MAX_BREAKINPUT 2
  20. struct stm32_breakinput {
  21. u32 index;
  22. u32 level;
  23. u32 filter;
  24. };
  25. struct stm32_pwm {
  26. struct pwm_chip chip;
  27. struct mutex lock; /* protect pwm config/enable */
  28. struct clk *clk;
  29. struct regmap *regmap;
  30. u32 max_arr;
  31. bool have_complementary_output;
  32. struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
  33. unsigned int num_breakinputs;
  34. u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
  35. };
  36. static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
  37. {
  38. return container_of(chip, struct stm32_pwm, chip);
  39. }
  40. static u32 active_channels(struct stm32_pwm *dev)
  41. {
  42. u32 ccer;
  43. regmap_read(dev->regmap, TIM_CCER, &ccer);
  44. return ccer & TIM_CCER_CCXE;
  45. }
  46. static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
  47. {
  48. switch (ch) {
  49. case 0:
  50. return regmap_write(dev->regmap, TIM_CCR1, value);
  51. case 1:
  52. return regmap_write(dev->regmap, TIM_CCR2, value);
  53. case 2:
  54. return regmap_write(dev->regmap, TIM_CCR3, value);
  55. case 3:
  56. return regmap_write(dev->regmap, TIM_CCR4, value);
  57. }
  58. return -EINVAL;
  59. }
  60. #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
  61. #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
  62. #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
  63. #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
  64. /*
  65. * Capture using PWM input mode:
  66. * ___ ___
  67. * TI[1, 2, 3 or 4]: ........._| |________|
  68. * ^0 ^1 ^2
  69. * . . .
  70. * . . XXXXX
  71. * . . XXXXX |
  72. * . XXXXX . |
  73. * XXXXX . . |
  74. * COUNTER: ______XXXXX . . . |_XXX
  75. * start^ . . . ^stop
  76. * . . . .
  77. * v v . v
  78. * v
  79. * CCR1/CCR3: tx..........t0...........t2
  80. * CCR2/CCR4: tx..............t1.........
  81. *
  82. * DMA burst transfer: | |
  83. * v v
  84. * DMA buffer: { t0, tx } { t2, t1 }
  85. * DMA done: ^
  86. *
  87. * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
  88. * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
  89. * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
  90. * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
  91. * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
  92. *
  93. * DMA done, compute:
  94. * - Period = t2 - t0
  95. * - Duty cycle = t1 - t0
  96. */
  97. static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
  98. unsigned long tmo_ms, u32 *raw_prd,
  99. u32 *raw_dty)
  100. {
  101. struct device *parent = priv->chip.dev->parent;
  102. enum stm32_timers_dmas dma_id;
  103. u32 ccen, ccr;
  104. int ret;
  105. /* Ensure registers have been updated, enable counter and capture */
  106. regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
  107. regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
  108. /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
  109. dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
  110. ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
  111. ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
  112. regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
  113. /*
  114. * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
  115. * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
  116. * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
  117. * or { CCR3, CCR4 }, { CCR3, CCR4 }
  118. */
  119. ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
  120. 2, tmo_ms);
  121. if (ret)
  122. goto stop;
  123. /* Period: t2 - t0 (take care of counter overflow) */
  124. if (priv->capture[0] <= priv->capture[2])
  125. *raw_prd = priv->capture[2] - priv->capture[0];
  126. else
  127. *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
  128. /* Duty cycle capture requires at least two capture units */
  129. if (pwm->chip->npwm < 2)
  130. *raw_dty = 0;
  131. else if (priv->capture[0] <= priv->capture[3])
  132. *raw_dty = priv->capture[3] - priv->capture[0];
  133. else
  134. *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
  135. if (*raw_dty > *raw_prd) {
  136. /*
  137. * Race beetween PWM input and DMA: it may happen
  138. * falling edge triggers new capture on TI2/4 before DMA
  139. * had a chance to read CCR2/4. It means capture[1]
  140. * contains period + duty_cycle. So, subtract period.
  141. */
  142. *raw_dty -= *raw_prd;
  143. }
  144. stop:
  145. regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
  146. regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
  147. return ret;
  148. }
  149. static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
  150. struct pwm_capture *result, unsigned long tmo_ms)
  151. {
  152. struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
  153. unsigned long long prd, div, dty;
  154. unsigned long rate;
  155. unsigned int psc = 0, icpsc, scale;
  156. u32 raw_prd = 0, raw_dty = 0;
  157. int ret = 0;
  158. mutex_lock(&priv->lock);
  159. if (active_channels(priv)) {
  160. ret = -EBUSY;
  161. goto unlock;
  162. }
  163. ret = clk_enable(priv->clk);
  164. if (ret) {
  165. dev_err(priv->chip.dev, "failed to enable counter clock\n");
  166. goto unlock;
  167. }
  168. rate = clk_get_rate(priv->clk);
  169. if (!rate) {
  170. ret = -EINVAL;
  171. goto clk_dis;
  172. }
  173. /* prescaler: fit timeout window provided by upper layer */
  174. div = (unsigned long long)rate * (unsigned long long)tmo_ms;
  175. do_div(div, MSEC_PER_SEC);
  176. prd = div;
  177. while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
  178. psc++;
  179. div = prd;
  180. do_div(div, psc + 1);
  181. }
  182. regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
  183. regmap_write(priv->regmap, TIM_PSC, psc);
  184. /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
  185. regmap_update_bits(priv->regmap,
  186. pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
  187. TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
  188. TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
  189. TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
  190. /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
  191. regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
  192. TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
  193. TIM_CCER_CC2P : TIM_CCER_CC4P);
  194. ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
  195. if (ret)
  196. goto stop;
  197. /*
  198. * Got a capture. Try to improve accuracy at high rates:
  199. * - decrease counter clock prescaler, scale up to max rate.
  200. * - use input prescaler, capture once every /2 /4 or /8 edges.
  201. */
  202. if (raw_prd) {
  203. u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
  204. scale = max_arr / min(max_arr, raw_prd);
  205. } else {
  206. scale = priv->max_arr; /* bellow resolution, use max scale */
  207. }
  208. if (psc && scale > 1) {
  209. /* 2nd measure with new scale */
  210. psc /= scale;
  211. regmap_write(priv->regmap, TIM_PSC, psc);
  212. ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
  213. &raw_dty);
  214. if (ret)
  215. goto stop;
  216. }
  217. /* Compute intermediate period not to exceed timeout at low rates */
  218. prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
  219. do_div(prd, rate);
  220. for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
  221. /* input prescaler: also keep arbitrary margin */
  222. if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
  223. break;
  224. if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
  225. break;
  226. }
  227. if (!icpsc)
  228. goto done;
  229. /* Last chance to improve period accuracy, using input prescaler */
  230. regmap_update_bits(priv->regmap,
  231. pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
  232. TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
  233. FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
  234. FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
  235. ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
  236. if (ret)
  237. goto stop;
  238. if (raw_dty >= (raw_prd >> icpsc)) {
  239. /*
  240. * We may fall here using input prescaler, when input
  241. * capture starts on high side (before falling edge).
  242. * Example with icpsc to capture on each 4 events:
  243. *
  244. * start 1st capture 2nd capture
  245. * v v v
  246. * ___ _____ _____ _____ _____ ____
  247. * TI1..4 |__| |__| |__| |__| |__|
  248. * v v . . . . . v v
  249. * icpsc1/3: . 0 . 1 . 2 . 3 . 0
  250. * icpsc2/4: 0 1 2 3 0
  251. * v v v v
  252. * CCR1/3 ......t0..............................t2
  253. * CCR2/4 ..t1..............................t1'...
  254. * . . .
  255. * Capture0: .<----------------------------->.
  256. * Capture1: .<-------------------------->. .
  257. * . . .
  258. * Period: .<------> . .
  259. * Low side: .<>.
  260. *
  261. * Result:
  262. * - Period = Capture0 / icpsc
  263. * - Duty = Period - Low side = Period - (Capture0 - Capture1)
  264. */
  265. raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
  266. }
  267. done:
  268. prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
  269. result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
  270. dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
  271. result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
  272. stop:
  273. regmap_write(priv->regmap, TIM_CCER, 0);
  274. regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
  275. regmap_write(priv->regmap, TIM_PSC, 0);
  276. clk_dis:
  277. clk_disable(priv->clk);
  278. unlock:
  279. mutex_unlock(&priv->lock);
  280. return ret;
  281. }
  282. static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
  283. int duty_ns, int period_ns)
  284. {
  285. unsigned long long prd, div, dty;
  286. unsigned int prescaler = 0;
  287. u32 ccmr, mask, shift;
  288. /* Period and prescaler values depends on clock rate */
  289. div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
  290. do_div(div, NSEC_PER_SEC);
  291. prd = div;
  292. while (div > priv->max_arr) {
  293. prescaler++;
  294. div = prd;
  295. do_div(div, prescaler + 1);
  296. }
  297. prd = div;
  298. if (prescaler > MAX_TIM_PSC)
  299. return -EINVAL;
  300. /*
  301. * All channels share the same prescaler and counter so when two
  302. * channels are active at the same time we can't change them
  303. */
  304. if (active_channels(priv) & ~(1 << ch * 4)) {
  305. u32 psc, arr;
  306. regmap_read(priv->regmap, TIM_PSC, &psc);
  307. regmap_read(priv->regmap, TIM_ARR, &arr);
  308. if ((psc != prescaler) || (arr != prd - 1))
  309. return -EBUSY;
  310. }
  311. regmap_write(priv->regmap, TIM_PSC, prescaler);
  312. regmap_write(priv->regmap, TIM_ARR, prd - 1);
  313. regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
  314. /* Calculate the duty cycles */
  315. dty = prd * duty_ns;
  316. do_div(dty, period_ns);
  317. write_ccrx(priv, ch, dty);
  318. /* Configure output mode */
  319. shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
  320. ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
  321. mask = CCMR_CHANNEL_MASK << shift;
  322. if (ch < 2)
  323. regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
  324. else
  325. regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
  326. regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
  327. return 0;
  328. }
  329. static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
  330. enum pwm_polarity polarity)
  331. {
  332. u32 mask;
  333. mask = TIM_CCER_CC1P << (ch * 4);
  334. if (priv->have_complementary_output)
  335. mask |= TIM_CCER_CC1NP << (ch * 4);
  336. regmap_update_bits(priv->regmap, TIM_CCER, mask,
  337. polarity == PWM_POLARITY_NORMAL ? 0 : mask);
  338. return 0;
  339. }
  340. static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
  341. {
  342. u32 mask;
  343. int ret;
  344. ret = clk_enable(priv->clk);
  345. if (ret)
  346. return ret;
  347. /* Enable channel */
  348. mask = TIM_CCER_CC1E << (ch * 4);
  349. if (priv->have_complementary_output)
  350. mask |= TIM_CCER_CC1NE << (ch * 4);
  351. regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
  352. /* Make sure that registers are updated */
  353. regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
  354. /* Enable controller */
  355. regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
  356. return 0;
  357. }
  358. static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
  359. {
  360. u32 mask;
  361. /* Disable channel */
  362. mask = TIM_CCER_CC1E << (ch * 4);
  363. if (priv->have_complementary_output)
  364. mask |= TIM_CCER_CC1NE << (ch * 4);
  365. regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
  366. /* When all channels are disabled, we can disable the controller */
  367. if (!active_channels(priv))
  368. regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
  369. clk_disable(priv->clk);
  370. }
  371. static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  372. const struct pwm_state *state)
  373. {
  374. bool enabled;
  375. struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
  376. int ret;
  377. enabled = pwm->state.enabled;
  378. if (enabled && !state->enabled) {
  379. stm32_pwm_disable(priv, pwm->hwpwm);
  380. return 0;
  381. }
  382. if (state->polarity != pwm->state.polarity)
  383. stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
  384. ret = stm32_pwm_config(priv, pwm->hwpwm,
  385. state->duty_cycle, state->period);
  386. if (ret)
  387. return ret;
  388. if (!enabled && state->enabled)
  389. ret = stm32_pwm_enable(priv, pwm->hwpwm);
  390. return ret;
  391. }
  392. static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
  393. const struct pwm_state *state)
  394. {
  395. struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
  396. int ret;
  397. /* protect common prescaler for all active channels */
  398. mutex_lock(&priv->lock);
  399. ret = stm32_pwm_apply(chip, pwm, state);
  400. mutex_unlock(&priv->lock);
  401. return ret;
  402. }
  403. static const struct pwm_ops stm32pwm_ops = {
  404. .owner = THIS_MODULE,
  405. .apply = stm32_pwm_apply_locked,
  406. .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
  407. };
  408. static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
  409. const struct stm32_breakinput *bi)
  410. {
  411. u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
  412. u32 bke = TIM_BDTR_BKE(bi->index);
  413. u32 bkp = TIM_BDTR_BKP(bi->index);
  414. u32 bkf = TIM_BDTR_BKF(bi->index);
  415. u32 mask = bkf | bkp | bke;
  416. u32 bdtr;
  417. bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
  418. if (bi->level)
  419. bdtr |= bkp;
  420. regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
  421. regmap_read(priv->regmap, TIM_BDTR, &bdtr);
  422. return (bdtr & bke) ? 0 : -EINVAL;
  423. }
  424. static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
  425. {
  426. unsigned int i;
  427. int ret;
  428. for (i = 0; i < priv->num_breakinputs; i++) {
  429. ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
  430. if (ret < 0)
  431. return ret;
  432. }
  433. return 0;
  434. }
  435. static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
  436. struct device_node *np)
  437. {
  438. int nb, ret, array_size;
  439. unsigned int i;
  440. nb = of_property_count_elems_of_size(np, "st,breakinput",
  441. sizeof(struct stm32_breakinput));
  442. /*
  443. * Because "st,breakinput" parameter is optional do not make probe
  444. * failed if it doesn't exist.
  445. */
  446. if (nb <= 0)
  447. return 0;
  448. if (nb > MAX_BREAKINPUT)
  449. return -EINVAL;
  450. priv->num_breakinputs = nb;
  451. array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
  452. ret = of_property_read_u32_array(np, "st,breakinput",
  453. (u32 *)priv->breakinputs, array_size);
  454. if (ret)
  455. return ret;
  456. for (i = 0; i < priv->num_breakinputs; i++) {
  457. if (priv->breakinputs[i].index > 1 ||
  458. priv->breakinputs[i].level > 1 ||
  459. priv->breakinputs[i].filter > 15)
  460. return -EINVAL;
  461. }
  462. return stm32_pwm_apply_breakinputs(priv);
  463. }
  464. static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
  465. {
  466. u32 ccer;
  467. /*
  468. * If complementary bit doesn't exist writing 1 will have no
  469. * effect so we can detect it.
  470. */
  471. regmap_update_bits(priv->regmap,
  472. TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
  473. regmap_read(priv->regmap, TIM_CCER, &ccer);
  474. regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
  475. priv->have_complementary_output = (ccer != 0);
  476. }
  477. static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
  478. {
  479. u32 ccer;
  480. int npwm = 0;
  481. /*
  482. * If channels enable bits don't exist writing 1 will have no
  483. * effect so we can detect and count them.
  484. */
  485. regmap_update_bits(priv->regmap,
  486. TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
  487. regmap_read(priv->regmap, TIM_CCER, &ccer);
  488. regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
  489. if (ccer & TIM_CCER_CC1E)
  490. npwm++;
  491. if (ccer & TIM_CCER_CC2E)
  492. npwm++;
  493. if (ccer & TIM_CCER_CC3E)
  494. npwm++;
  495. if (ccer & TIM_CCER_CC4E)
  496. npwm++;
  497. return npwm;
  498. }
  499. static int stm32_pwm_probe(struct platform_device *pdev)
  500. {
  501. struct device *dev = &pdev->dev;
  502. struct device_node *np = dev->of_node;
  503. struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
  504. struct stm32_pwm *priv;
  505. int ret;
  506. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  507. if (!priv)
  508. return -ENOMEM;
  509. mutex_init(&priv->lock);
  510. priv->regmap = ddata->regmap;
  511. priv->clk = ddata->clk;
  512. priv->max_arr = ddata->max_arr;
  513. priv->chip.of_xlate = of_pwm_xlate_with_flags;
  514. priv->chip.of_pwm_n_cells = 3;
  515. if (!priv->regmap || !priv->clk)
  516. return -EINVAL;
  517. ret = stm32_pwm_probe_breakinputs(priv, np);
  518. if (ret)
  519. return ret;
  520. stm32_pwm_detect_complementary(priv);
  521. priv->chip.base = -1;
  522. priv->chip.dev = dev;
  523. priv->chip.ops = &stm32pwm_ops;
  524. priv->chip.npwm = stm32_pwm_detect_channels(priv);
  525. ret = pwmchip_add(&priv->chip);
  526. if (ret < 0)
  527. return ret;
  528. platform_set_drvdata(pdev, priv);
  529. return 0;
  530. }
  531. static int stm32_pwm_remove(struct platform_device *pdev)
  532. {
  533. struct stm32_pwm *priv = platform_get_drvdata(pdev);
  534. unsigned int i;
  535. for (i = 0; i < priv->chip.npwm; i++)
  536. pwm_disable(&priv->chip.pwms[i]);
  537. pwmchip_remove(&priv->chip);
  538. return 0;
  539. }
  540. static int __maybe_unused stm32_pwm_suspend(struct device *dev)
  541. {
  542. struct stm32_pwm *priv = dev_get_drvdata(dev);
  543. unsigned int i;
  544. u32 ccer, mask;
  545. /* Look for active channels */
  546. ccer = active_channels(priv);
  547. for (i = 0; i < priv->chip.npwm; i++) {
  548. mask = TIM_CCER_CC1E << (i * 4);
  549. if (ccer & mask) {
  550. dev_err(dev, "PWM %u still in use by consumer %s\n",
  551. i, priv->chip.pwms[i].label);
  552. return -EBUSY;
  553. }
  554. }
  555. return pinctrl_pm_select_sleep_state(dev);
  556. }
  557. static int __maybe_unused stm32_pwm_resume(struct device *dev)
  558. {
  559. struct stm32_pwm *priv = dev_get_drvdata(dev);
  560. int ret;
  561. ret = pinctrl_pm_select_default_state(dev);
  562. if (ret)
  563. return ret;
  564. /* restore breakinput registers that may have been lost in low power */
  565. return stm32_pwm_apply_breakinputs(priv);
  566. }
  567. static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
  568. static const struct of_device_id stm32_pwm_of_match[] = {
  569. { .compatible = "st,stm32-pwm", },
  570. { /* end node */ },
  571. };
  572. MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
  573. static struct platform_driver stm32_pwm_driver = {
  574. .probe = stm32_pwm_probe,
  575. .remove = stm32_pwm_remove,
  576. .driver = {
  577. .name = "stm32-pwm",
  578. .of_match_table = stm32_pwm_of_match,
  579. .pm = &stm32_pwm_pm_ops,
  580. },
  581. };
  582. module_platform_driver(stm32_pwm_driver);
  583. MODULE_ALIAS("platform:stm32-pwm");
  584. MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
  585. MODULE_LICENSE("GPL v2");