pwm-sifive.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017-2018 SiFive
  4. * For SiFive's PWM IP block documentation please refer Chapter 14 of
  5. * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  6. *
  7. * Limitations:
  8. * - When changing both duty cycle and period, we cannot prevent in
  9. * software that the output might produce a period with mixed
  10. * settings (new period length and old duty cycle).
  11. * - The hardware cannot generate a 100% duty cycle.
  12. * - The hardware generates only inverted output.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pwm.h>
  19. #include <linux/slab.h>
  20. #include <linux/bitfield.h>
  21. /* Register offsets */
  22. #define PWM_SIFIVE_PWMCFG 0x0
  23. #define PWM_SIFIVE_PWMCOUNT 0x8
  24. #define PWM_SIFIVE_PWMS 0x10
  25. #define PWM_SIFIVE_PWMCMP0 0x20
  26. /* PWMCFG fields */
  27. #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
  28. #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
  29. #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
  30. #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
  31. #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
  32. #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
  33. #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
  34. #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
  35. #define PWM_SIFIVE_PWMCFG_IP BIT(28)
  36. /* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
  37. #define PWM_SIFIVE_SIZE_PWMCMP 4
  38. #define PWM_SIFIVE_CMPWIDTH 16
  39. #define PWM_SIFIVE_DEFAULT_PERIOD 10000000
  40. struct pwm_sifive_ddata {
  41. struct pwm_chip chip;
  42. struct mutex lock; /* lock to protect user_count */
  43. struct notifier_block notifier;
  44. struct clk *clk;
  45. void __iomem *regs;
  46. unsigned int real_period;
  47. unsigned int approx_period;
  48. int user_count;
  49. };
  50. static inline
  51. struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
  52. {
  53. return container_of(c, struct pwm_sifive_ddata, chip);
  54. }
  55. static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
  56. {
  57. struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  58. mutex_lock(&ddata->lock);
  59. ddata->user_count++;
  60. mutex_unlock(&ddata->lock);
  61. return 0;
  62. }
  63. static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
  64. {
  65. struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  66. mutex_lock(&ddata->lock);
  67. ddata->user_count--;
  68. mutex_unlock(&ddata->lock);
  69. }
  70. static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
  71. unsigned long rate)
  72. {
  73. unsigned long long num;
  74. unsigned long scale_pow;
  75. int scale;
  76. u32 val;
  77. /*
  78. * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
  79. * period length is using pwmscale which provides the number of bits the
  80. * counter is shifted before being feed to the comparators. A period
  81. * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
  82. * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
  83. */
  84. scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
  85. scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
  86. val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
  87. FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
  88. writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
  89. /* As scale <= 15 the shift operation cannot overflow. */
  90. num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
  91. ddata->real_period = div64_ul(num, rate);
  92. dev_dbg(ddata->chip.dev,
  93. "New real_period = %u ns\n", ddata->real_period);
  94. }
  95. static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  96. struct pwm_state *state)
  97. {
  98. struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  99. u32 duty, val;
  100. duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP0 +
  101. pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
  102. state->enabled = duty > 0;
  103. val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
  104. if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
  105. state->enabled = false;
  106. state->period = ddata->real_period;
  107. state->duty_cycle =
  108. (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
  109. state->polarity = PWM_POLARITY_INVERSED;
  110. }
  111. static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
  112. {
  113. struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  114. int ret;
  115. if (enable) {
  116. ret = clk_enable(ddata->clk);
  117. if (ret) {
  118. dev_err(ddata->chip.dev, "Enable clk failed\n");
  119. return ret;
  120. }
  121. }
  122. if (!enable)
  123. clk_disable(ddata->clk);
  124. return 0;
  125. }
  126. static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  127. const struct pwm_state *state)
  128. {
  129. struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  130. struct pwm_state cur_state;
  131. unsigned int duty_cycle;
  132. unsigned long long num;
  133. bool enabled;
  134. int ret = 0;
  135. u32 frac;
  136. if (state->polarity != PWM_POLARITY_INVERSED)
  137. return -EINVAL;
  138. ret = clk_enable(ddata->clk);
  139. if (ret) {
  140. dev_err(ddata->chip.dev, "Enable clk failed\n");
  141. return ret;
  142. }
  143. mutex_lock(&ddata->lock);
  144. cur_state = pwm->state;
  145. enabled = cur_state.enabled;
  146. duty_cycle = state->duty_cycle;
  147. if (!state->enabled)
  148. duty_cycle = 0;
  149. /*
  150. * The problem of output producing mixed setting as mentioned at top,
  151. * occurs here. To minimize the window for this problem, we are
  152. * calculating the register values first and then writing them
  153. * consecutively
  154. */
  155. num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
  156. frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
  157. /* The hardware cannot generate a 100% duty cycle */
  158. frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
  159. if (state->period != ddata->approx_period) {
  160. if (ddata->user_count != 1) {
  161. ret = -EBUSY;
  162. goto exit;
  163. }
  164. ddata->approx_period = state->period;
  165. pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
  166. }
  167. writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP0 +
  168. pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
  169. if (state->enabled != enabled)
  170. pwm_sifive_enable(chip, state->enabled);
  171. exit:
  172. clk_disable(ddata->clk);
  173. mutex_unlock(&ddata->lock);
  174. return ret;
  175. }
  176. static const struct pwm_ops pwm_sifive_ops = {
  177. .request = pwm_sifive_request,
  178. .free = pwm_sifive_free,
  179. .get_state = pwm_sifive_get_state,
  180. .apply = pwm_sifive_apply,
  181. .owner = THIS_MODULE,
  182. };
  183. static int pwm_sifive_clock_notifier(struct notifier_block *nb,
  184. unsigned long event, void *data)
  185. {
  186. struct clk_notifier_data *ndata = data;
  187. struct pwm_sifive_ddata *ddata =
  188. container_of(nb, struct pwm_sifive_ddata, notifier);
  189. if (event == POST_RATE_CHANGE)
  190. pwm_sifive_update_clock(ddata, ndata->new_rate);
  191. return NOTIFY_OK;
  192. }
  193. static int pwm_sifive_probe(struct platform_device *pdev)
  194. {
  195. struct device *dev = &pdev->dev;
  196. struct pwm_sifive_ddata *ddata;
  197. struct pwm_chip *chip;
  198. struct resource *res;
  199. int ret;
  200. ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
  201. if (!ddata)
  202. return -ENOMEM;
  203. mutex_init(&ddata->lock);
  204. chip = &ddata->chip;
  205. chip->dev = dev;
  206. chip->ops = &pwm_sifive_ops;
  207. chip->of_xlate = of_pwm_xlate_with_flags;
  208. chip->of_pwm_n_cells = 3;
  209. chip->base = -1;
  210. chip->npwm = 4;
  211. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  212. ddata->regs = devm_ioremap_resource(dev, res);
  213. if (IS_ERR(ddata->regs))
  214. return PTR_ERR(ddata->regs);
  215. ddata->clk = devm_clk_get(dev, NULL);
  216. if (IS_ERR(ddata->clk))
  217. return dev_err_probe(dev, PTR_ERR(ddata->clk),
  218. "Unable to find controller clock\n");
  219. ret = clk_prepare_enable(ddata->clk);
  220. if (ret) {
  221. dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
  222. return ret;
  223. }
  224. /* Watch for changes to underlying clock frequency */
  225. ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
  226. ret = clk_notifier_register(ddata->clk, &ddata->notifier);
  227. if (ret) {
  228. dev_err(dev, "failed to register clock notifier: %d\n", ret);
  229. goto disable_clk;
  230. }
  231. ret = pwmchip_add(chip);
  232. if (ret < 0) {
  233. dev_err(dev, "cannot register PWM: %d\n", ret);
  234. goto unregister_clk;
  235. }
  236. platform_set_drvdata(pdev, ddata);
  237. dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
  238. return 0;
  239. unregister_clk:
  240. clk_notifier_unregister(ddata->clk, &ddata->notifier);
  241. disable_clk:
  242. clk_disable_unprepare(ddata->clk);
  243. return ret;
  244. }
  245. static int pwm_sifive_remove(struct platform_device *dev)
  246. {
  247. struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
  248. bool is_enabled = false;
  249. struct pwm_device *pwm;
  250. int ret, ch;
  251. for (ch = 0; ch < ddata->chip.npwm; ch++) {
  252. pwm = &ddata->chip.pwms[ch];
  253. if (pwm->state.enabled) {
  254. is_enabled = true;
  255. break;
  256. }
  257. }
  258. if (is_enabled)
  259. clk_disable(ddata->clk);
  260. clk_disable_unprepare(ddata->clk);
  261. ret = pwmchip_remove(&ddata->chip);
  262. clk_notifier_unregister(ddata->clk, &ddata->notifier);
  263. return ret;
  264. }
  265. static const struct of_device_id pwm_sifive_of_match[] = {
  266. { .compatible = "sifive,pwm0" },
  267. {},
  268. };
  269. MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
  270. static struct platform_driver pwm_sifive_driver = {
  271. .probe = pwm_sifive_probe,
  272. .remove = pwm_sifive_remove,
  273. .driver = {
  274. .name = "pwm-sifive",
  275. .of_match_table = pwm_sifive_of_match,
  276. },
  277. };
  278. module_platform_driver(pwm_sifive_driver);
  279. MODULE_DESCRIPTION("SiFive PWM driver");
  280. MODULE_LICENSE("GPL v2");