pwm-omap-dmtimer.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
  4. * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
  5. * Copyright (c) 2012 NeilBrown <neilb@suse.de>
  6. * Heavily based on earlier code which is:
  7. * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
  8. *
  9. * Also based on pwm-samsung.c
  10. *
  11. * Description:
  12. * This file is the core OMAP support for the generic, Linux
  13. * PWM driver / controller, using the OMAP's dual-mode timers
  14. * with a timer counter that goes up. When it overflows it gets
  15. * reloaded with the load value and the pwm output goes up.
  16. * When counter matches with match register, the output goes down.
  17. * Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
  18. *
  19. * Limitations:
  20. * - When PWM is stopped, timer counter gets stopped immediately. This
  21. * doesn't allow the current PWM period to complete and stops abruptly.
  22. * - When PWM is running and changing both duty cycle and period,
  23. * we cannot prevent in software that the output might produce
  24. * a period with mixed settings. Especially when period/duty_cyle
  25. * is updated while the pwm pin is high, current pwm period/duty_cycle
  26. * can get updated as below based on the current timer counter:
  27. * - period for current cycle = current_period + new period
  28. * - duty_cycle for current period = current period + new duty_cycle.
  29. * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
  30. * user requests a change in polarity when in active state:
  31. * - PWM is stopped abruptly(without completing the current cycle)
  32. * - Polarity is changed
  33. * - A fresh cycle is started.
  34. */
  35. #include <linux/clk.h>
  36. #include <linux/err.h>
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/mutex.h>
  40. #include <linux/of.h>
  41. #include <linux/of_platform.h>
  42. #include <clocksource/timer-ti-dm.h>
  43. #include <linux/platform_data/dmtimer-omap.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/pm_runtime.h>
  46. #include <linux/pwm.h>
  47. #include <linux/slab.h>
  48. #include <linux/time.h>
  49. #define DM_TIMER_LOAD_MIN 0xfffffffe
  50. #define DM_TIMER_MAX 0xffffffff
  51. /**
  52. * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
  53. * corresponding to omap dmtimer.
  54. * @chip: PWM chip structure representing PWM controller
  55. * @mutex: Mutex to protect pwm apply state
  56. * @dm_timer: Pointer to omap dm timer.
  57. * @pdata: Pointer to omap dm timer ops.
  58. * @dm_timer_pdev: Pointer to omap dm timer platform device
  59. */
  60. struct pwm_omap_dmtimer_chip {
  61. struct pwm_chip chip;
  62. /* Mutex to protect pwm apply state */
  63. struct mutex mutex;
  64. struct omap_dm_timer *dm_timer;
  65. const struct omap_dm_timer_ops *pdata;
  66. struct platform_device *dm_timer_pdev;
  67. };
  68. static inline struct pwm_omap_dmtimer_chip *
  69. to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  70. {
  71. return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
  72. }
  73. /**
  74. * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
  75. * @clk_rate: pwm timer clock rate
  76. * @ns: time frame in nano seconds.
  77. *
  78. * Return number of clock cycles in a given period(ins ns).
  79. */
  80. static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  81. {
  82. return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
  83. }
  84. /**
  85. * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
  86. * @omap: Pointer to pwm omap dm timer chip
  87. */
  88. static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  89. {
  90. /*
  91. * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  92. * started at 0xFFFFFFFE when overflow and match is used to ensure
  93. * that the PWM line is toggled on the first event.
  94. *
  95. * Note that omap_dm_timer_enable/disable is for register access and
  96. * not the timer counter itself.
  97. */
  98. omap->pdata->enable(omap->dm_timer);
  99. omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
  100. omap->pdata->disable(omap->dm_timer);
  101. omap->pdata->start(omap->dm_timer);
  102. }
  103. /**
  104. * pwm_omap_dmtimer_is_enabled() - Detect if the pwm is enabled.
  105. * @omap: Pointer to pwm omap dm timer chip
  106. *
  107. * Return true if pwm is enabled else false.
  108. */
  109. static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
  110. {
  111. u32 status;
  112. status = omap->pdata->get_pwm_status(omap->dm_timer);
  113. return !!(status & OMAP_TIMER_CTRL_ST);
  114. }
  115. /**
  116. * pwm_omap_dmtimer_polarity() - Detect the polarity of pwm.
  117. * @omap: Pointer to pwm omap dm timer chip
  118. *
  119. * Return the polarity of pwm.
  120. */
  121. static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
  122. {
  123. u32 status;
  124. status = omap->pdata->get_pwm_status(omap->dm_timer);
  125. return !!(status & OMAP_TIMER_CTRL_SCPWM);
  126. }
  127. /**
  128. * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
  129. * @chip: Pointer to PWM controller
  130. * @pwm: Pointer to PWM channel
  131. * @duty_ns: New duty cycle in nano seconds
  132. * @period_ns: New period in nano seconds
  133. *
  134. * Return 0 if successfully changed the period/duty_cycle else appropriate
  135. * error.
  136. */
  137. static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
  138. struct pwm_device *pwm,
  139. int duty_ns, int period_ns)
  140. {
  141. struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  142. u32 period_cycles, duty_cycles;
  143. u32 load_value, match_value;
  144. unsigned long clk_rate;
  145. struct clk *fclk;
  146. dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
  147. duty_ns, period_ns);
  148. if (duty_ns == pwm_get_duty_cycle(pwm) &&
  149. period_ns == pwm_get_period(pwm))
  150. return 0;
  151. fclk = omap->pdata->get_fclk(omap->dm_timer);
  152. if (!fclk) {
  153. dev_err(chip->dev, "invalid pmtimer fclk\n");
  154. return -EINVAL;
  155. }
  156. clk_rate = clk_get_rate(fclk);
  157. if (!clk_rate) {
  158. dev_err(chip->dev, "invalid pmtimer fclk rate\n");
  159. return -EINVAL;
  160. }
  161. dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
  162. /*
  163. * Calculate the appropriate load and match values based on the
  164. * specified period and duty cycle. The load value determines the
  165. * period time and the match value determines the duty time.
  166. *
  167. * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
  168. * Similarly, the active time lasts (match_value-load_value+1) cycles.
  169. * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
  170. * clock cycles.
  171. *
  172. * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
  173. *
  174. * References:
  175. * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
  176. * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
  177. */
  178. period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
  179. duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
  180. if (period_cycles < 2) {
  181. dev_info(chip->dev,
  182. "period %d ns too short for clock rate %lu Hz\n",
  183. period_ns, clk_rate);
  184. return -EINVAL;
  185. }
  186. if (duty_cycles < 1) {
  187. dev_dbg(chip->dev,
  188. "duty cycle %d ns is too short for clock rate %lu Hz\n",
  189. duty_ns, clk_rate);
  190. dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
  191. duty_cycles = 1;
  192. } else if (duty_cycles >= period_cycles) {
  193. dev_dbg(chip->dev,
  194. "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
  195. duty_ns, period_ns, clk_rate);
  196. dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
  197. duty_cycles = period_cycles - 1;
  198. }
  199. dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
  200. DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
  201. clk_rate),
  202. DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
  203. clk_rate));
  204. load_value = (DM_TIMER_MAX - period_cycles) + 1;
  205. match_value = load_value + duty_cycles - 1;
  206. omap->pdata->set_load(omap->dm_timer, load_value);
  207. omap->pdata->set_match(omap->dm_timer, true, match_value);
  208. dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
  209. load_value, load_value, match_value, match_value);
  210. return 0;
  211. }
  212. /**
  213. * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
  214. * @chip: Pointer to PWM controller
  215. * @pwm: Pointer to PWM channel
  216. * @polarity: New pwm polarity to be set
  217. */
  218. static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
  219. struct pwm_device *pwm,
  220. enum pwm_polarity polarity)
  221. {
  222. struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  223. bool enabled;
  224. /* Disable the PWM before changing the polarity. */
  225. enabled = pwm_omap_dmtimer_is_enabled(omap);
  226. if (enabled)
  227. omap->pdata->stop(omap->dm_timer);
  228. omap->pdata->set_pwm(omap->dm_timer,
  229. polarity == PWM_POLARITY_INVERSED,
  230. true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
  231. true);
  232. if (enabled)
  233. pwm_omap_dmtimer_start(omap);
  234. }
  235. /**
  236. * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
  237. * @chip: Pointer to PWM controller
  238. * @pwm: Pointer to PWM channel
  239. * @state: New state to apply
  240. *
  241. * Return 0 if successfully changed the state else appropriate error.
  242. */
  243. static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
  244. struct pwm_device *pwm,
  245. const struct pwm_state *state)
  246. {
  247. struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  248. int ret = 0;
  249. mutex_lock(&omap->mutex);
  250. if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
  251. omap->pdata->stop(omap->dm_timer);
  252. goto unlock_mutex;
  253. }
  254. if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
  255. pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
  256. ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
  257. state->period);
  258. if (ret)
  259. goto unlock_mutex;
  260. if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
  261. omap->pdata->set_pwm(omap->dm_timer,
  262. state->polarity == PWM_POLARITY_INVERSED,
  263. true,
  264. OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
  265. true);
  266. pwm_omap_dmtimer_start(omap);
  267. }
  268. unlock_mutex:
  269. mutex_unlock(&omap->mutex);
  270. return ret;
  271. }
  272. static const struct pwm_ops pwm_omap_dmtimer_ops = {
  273. .apply = pwm_omap_dmtimer_apply,
  274. .owner = THIS_MODULE,
  275. };
  276. static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
  277. {
  278. struct device_node *np = pdev->dev.of_node;
  279. struct dmtimer_platform_data *timer_pdata;
  280. const struct omap_dm_timer_ops *pdata;
  281. struct platform_device *timer_pdev;
  282. struct pwm_omap_dmtimer_chip *omap;
  283. struct omap_dm_timer *dm_timer;
  284. struct device_node *timer;
  285. int ret = 0;
  286. u32 v;
  287. timer = of_parse_phandle(np, "ti,timers", 0);
  288. if (!timer)
  289. return -ENODEV;
  290. timer_pdev = of_find_device_by_node(timer);
  291. if (!timer_pdev) {
  292. dev_err(&pdev->dev, "Unable to find Timer pdev\n");
  293. ret = -ENODEV;
  294. goto err_find_timer_pdev;
  295. }
  296. timer_pdata = dev_get_platdata(&timer_pdev->dev);
  297. if (!timer_pdata) {
  298. dev_dbg(&pdev->dev,
  299. "dmtimer pdata structure NULL, deferring probe\n");
  300. ret = -EPROBE_DEFER;
  301. goto err_platdata;
  302. }
  303. pdata = timer_pdata->timer_ops;
  304. if (!pdata || !pdata->request_by_node ||
  305. !pdata->free ||
  306. !pdata->enable ||
  307. !pdata->disable ||
  308. !pdata->get_fclk ||
  309. !pdata->start ||
  310. !pdata->stop ||
  311. !pdata->set_load ||
  312. !pdata->set_match ||
  313. !pdata->set_pwm ||
  314. !pdata->get_pwm_status ||
  315. !pdata->set_prescaler ||
  316. !pdata->write_counter) {
  317. dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
  318. ret = -EINVAL;
  319. goto err_platdata;
  320. }
  321. if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
  322. dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
  323. ret = -ENODEV;
  324. goto err_timer_property;
  325. }
  326. dm_timer = pdata->request_by_node(timer);
  327. if (!dm_timer) {
  328. ret = -EPROBE_DEFER;
  329. goto err_request_timer;
  330. }
  331. omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
  332. if (!omap) {
  333. ret = -ENOMEM;
  334. goto err_alloc_omap;
  335. }
  336. omap->pdata = pdata;
  337. omap->dm_timer = dm_timer;
  338. omap->dm_timer_pdev = timer_pdev;
  339. /*
  340. * Ensure that the timer is stopped before we allow PWM core to call
  341. * pwm_enable.
  342. */
  343. if (pm_runtime_active(&omap->dm_timer_pdev->dev))
  344. omap->pdata->stop(omap->dm_timer);
  345. if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
  346. omap->pdata->set_prescaler(omap->dm_timer, v);
  347. /* setup dmtimer clock source */
  348. if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
  349. omap->pdata->set_source(omap->dm_timer, v);
  350. omap->chip.dev = &pdev->dev;
  351. omap->chip.ops = &pwm_omap_dmtimer_ops;
  352. omap->chip.base = -1;
  353. omap->chip.npwm = 1;
  354. omap->chip.of_xlate = of_pwm_xlate_with_flags;
  355. omap->chip.of_pwm_n_cells = 3;
  356. mutex_init(&omap->mutex);
  357. ret = pwmchip_add(&omap->chip);
  358. if (ret < 0) {
  359. dev_err(&pdev->dev, "failed to register PWM\n");
  360. goto err_pwmchip_add;
  361. }
  362. of_node_put(timer);
  363. platform_set_drvdata(pdev, omap);
  364. return 0;
  365. err_pwmchip_add:
  366. /*
  367. * *omap is allocated using devm_kzalloc,
  368. * so no free necessary here
  369. */
  370. err_alloc_omap:
  371. pdata->free(dm_timer);
  372. err_request_timer:
  373. err_timer_property:
  374. err_platdata:
  375. put_device(&timer_pdev->dev);
  376. err_find_timer_pdev:
  377. of_node_put(timer);
  378. return ret;
  379. }
  380. static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
  381. {
  382. struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
  383. int ret;
  384. ret = pwmchip_remove(&omap->chip);
  385. if (ret)
  386. return ret;
  387. if (pm_runtime_active(&omap->dm_timer_pdev->dev))
  388. omap->pdata->stop(omap->dm_timer);
  389. omap->pdata->free(omap->dm_timer);
  390. put_device(&omap->dm_timer_pdev->dev);
  391. mutex_destroy(&omap->mutex);
  392. return 0;
  393. }
  394. static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
  395. {.compatible = "ti,omap-dmtimer-pwm"},
  396. {}
  397. };
  398. MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
  399. static struct platform_driver pwm_omap_dmtimer_driver = {
  400. .driver = {
  401. .name = "omap-dmtimer-pwm",
  402. .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
  403. },
  404. .probe = pwm_omap_dmtimer_probe,
  405. .remove = pwm_omap_dmtimer_remove,
  406. };
  407. module_platform_driver(pwm_omap_dmtimer_driver);
  408. MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
  409. MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
  410. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  411. MODULE_LICENSE("GPL v2");
  412. MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");