pwm-mtk-disp.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MediaTek display pulse-width-modulation controller driver.
  4. * Copyright (c) 2015 MediaTek Inc.
  5. * Author: YH Huang <yh.huang@mediatek.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pwm.h>
  15. #include <linux/slab.h>
  16. #define DISP_PWM_EN 0x00
  17. #define PWM_CLKDIV_SHIFT 16
  18. #define PWM_CLKDIV_MAX 0x3ff
  19. #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
  20. #define PWM_PERIOD_BIT_WIDTH 12
  21. #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
  22. #define PWM_HIGH_WIDTH_SHIFT 16
  23. #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
  24. struct mtk_pwm_data {
  25. u32 enable_mask;
  26. unsigned int con0;
  27. u32 con0_sel;
  28. unsigned int con1;
  29. bool has_commit;
  30. unsigned int commit;
  31. unsigned int commit_mask;
  32. unsigned int bls_debug;
  33. u32 bls_debug_mask;
  34. };
  35. struct mtk_disp_pwm {
  36. struct pwm_chip chip;
  37. const struct mtk_pwm_data *data;
  38. struct clk *clk_main;
  39. struct clk *clk_mm;
  40. void __iomem *base;
  41. };
  42. static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
  43. {
  44. return container_of(chip, struct mtk_disp_pwm, chip);
  45. }
  46. static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
  47. u32 mask, u32 data)
  48. {
  49. void __iomem *address = mdp->base + offset;
  50. u32 value;
  51. value = readl(address);
  52. value &= ~mask;
  53. value |= data;
  54. writel(value, address);
  55. }
  56. static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  57. int duty_ns, int period_ns)
  58. {
  59. struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  60. u32 clk_div, period, high_width, value;
  61. u64 div, rate;
  62. int err;
  63. /*
  64. * Find period, high_width and clk_div to suit duty_ns and period_ns.
  65. * Calculate proper div value to keep period value in the bound.
  66. *
  67. * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
  68. * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
  69. *
  70. * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
  71. * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
  72. */
  73. rate = clk_get_rate(mdp->clk_main);
  74. clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
  75. PWM_PERIOD_BIT_WIDTH;
  76. if (clk_div > PWM_CLKDIV_MAX)
  77. return -EINVAL;
  78. div = NSEC_PER_SEC * (clk_div + 1);
  79. period = div64_u64(rate * period_ns, div);
  80. if (period > 0)
  81. period--;
  82. high_width = div64_u64(rate * duty_ns, div);
  83. value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
  84. err = clk_enable(mdp->clk_main);
  85. if (err < 0)
  86. return err;
  87. err = clk_enable(mdp->clk_mm);
  88. if (err < 0) {
  89. clk_disable(mdp->clk_main);
  90. return err;
  91. }
  92. mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
  93. PWM_CLKDIV_MASK,
  94. clk_div << PWM_CLKDIV_SHIFT);
  95. mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
  96. PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
  97. value);
  98. if (mdp->data->has_commit) {
  99. mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
  100. mdp->data->commit_mask,
  101. mdp->data->commit_mask);
  102. mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
  103. mdp->data->commit_mask,
  104. 0x0);
  105. }
  106. clk_disable(mdp->clk_mm);
  107. clk_disable(mdp->clk_main);
  108. return 0;
  109. }
  110. static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  111. {
  112. struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  113. int err;
  114. err = clk_enable(mdp->clk_main);
  115. if (err < 0)
  116. return err;
  117. err = clk_enable(mdp->clk_mm);
  118. if (err < 0) {
  119. clk_disable(mdp->clk_main);
  120. return err;
  121. }
  122. mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
  123. mdp->data->enable_mask);
  124. return 0;
  125. }
  126. static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  127. {
  128. struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  129. mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
  130. 0x0);
  131. clk_disable(mdp->clk_mm);
  132. clk_disable(mdp->clk_main);
  133. }
  134. static const struct pwm_ops mtk_disp_pwm_ops = {
  135. .config = mtk_disp_pwm_config,
  136. .enable = mtk_disp_pwm_enable,
  137. .disable = mtk_disp_pwm_disable,
  138. .owner = THIS_MODULE,
  139. };
  140. static int mtk_disp_pwm_probe(struct platform_device *pdev)
  141. {
  142. struct mtk_disp_pwm *mdp;
  143. struct resource *r;
  144. int ret;
  145. mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
  146. if (!mdp)
  147. return -ENOMEM;
  148. mdp->data = of_device_get_match_data(&pdev->dev);
  149. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  150. mdp->base = devm_ioremap_resource(&pdev->dev, r);
  151. if (IS_ERR(mdp->base))
  152. return PTR_ERR(mdp->base);
  153. mdp->clk_main = devm_clk_get(&pdev->dev, "main");
  154. if (IS_ERR(mdp->clk_main))
  155. return PTR_ERR(mdp->clk_main);
  156. mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
  157. if (IS_ERR(mdp->clk_mm))
  158. return PTR_ERR(mdp->clk_mm);
  159. ret = clk_prepare(mdp->clk_main);
  160. if (ret < 0)
  161. return ret;
  162. ret = clk_prepare(mdp->clk_mm);
  163. if (ret < 0)
  164. goto disable_clk_main;
  165. mdp->chip.dev = &pdev->dev;
  166. mdp->chip.ops = &mtk_disp_pwm_ops;
  167. mdp->chip.base = -1;
  168. mdp->chip.npwm = 1;
  169. ret = pwmchip_add(&mdp->chip);
  170. if (ret < 0) {
  171. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  172. goto disable_clk_mm;
  173. }
  174. platform_set_drvdata(pdev, mdp);
  175. /*
  176. * For MT2701, disable double buffer before writing register
  177. * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
  178. */
  179. if (!mdp->data->has_commit) {
  180. mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
  181. mdp->data->bls_debug_mask,
  182. mdp->data->bls_debug_mask);
  183. mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
  184. mdp->data->con0_sel,
  185. mdp->data->con0_sel);
  186. }
  187. return 0;
  188. disable_clk_mm:
  189. clk_unprepare(mdp->clk_mm);
  190. disable_clk_main:
  191. clk_unprepare(mdp->clk_main);
  192. return ret;
  193. }
  194. static int mtk_disp_pwm_remove(struct platform_device *pdev)
  195. {
  196. struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
  197. int ret;
  198. ret = pwmchip_remove(&mdp->chip);
  199. clk_unprepare(mdp->clk_mm);
  200. clk_unprepare(mdp->clk_main);
  201. return ret;
  202. }
  203. static const struct mtk_pwm_data mt2701_pwm_data = {
  204. .enable_mask = BIT(16),
  205. .con0 = 0xa8,
  206. .con0_sel = 0x2,
  207. .con1 = 0xac,
  208. .has_commit = false,
  209. .bls_debug = 0xb0,
  210. .bls_debug_mask = 0x3,
  211. };
  212. static const struct mtk_pwm_data mt8173_pwm_data = {
  213. .enable_mask = BIT(0),
  214. .con0 = 0x10,
  215. .con0_sel = 0x0,
  216. .con1 = 0x14,
  217. .has_commit = true,
  218. .commit = 0x8,
  219. .commit_mask = 0x1,
  220. };
  221. static const struct mtk_pwm_data mt8183_pwm_data = {
  222. .enable_mask = BIT(0),
  223. .con0 = 0x18,
  224. .con0_sel = 0x0,
  225. .con1 = 0x1c,
  226. .has_commit = false,
  227. .bls_debug = 0x80,
  228. .bls_debug_mask = 0x3,
  229. };
  230. static const struct of_device_id mtk_disp_pwm_of_match[] = {
  231. { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
  232. { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
  233. { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
  234. { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
  235. { }
  236. };
  237. MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
  238. static struct platform_driver mtk_disp_pwm_driver = {
  239. .driver = {
  240. .name = "mediatek-disp-pwm",
  241. .of_match_table = mtk_disp_pwm_of_match,
  242. },
  243. .probe = mtk_disp_pwm_probe,
  244. .remove = mtk_disp_pwm_remove,
  245. };
  246. module_platform_driver(mtk_disp_pwm_driver);
  247. MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
  248. MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
  249. MODULE_LICENSE("GPL v2");