pwm-meson.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /*
  3. * PWM controller driver for Amlogic Meson SoCs.
  4. *
  5. * This PWM is only a set of Gates, Dividers and Counters:
  6. * PWM output is achieved by calculating a clock that permits calculating
  7. * two periods (low and high). The counter then has to be set to switch after
  8. * N cycles for the first half period.
  9. * The hardware has no "polarity" setting. This driver reverses the period
  10. * cycles (the low length is inverted with the high length) for
  11. * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
  12. * from the hardware.
  13. * Setting the duty cycle will disable and re-enable the PWM output.
  14. * Disabling the PWM stops the output immediately (without waiting for the
  15. * current period to complete first).
  16. *
  17. * The public S912 (GXM) datasheet contains some documentation for this PWM
  18. * controller starting on page 543:
  19. * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
  20. * An updated version of this IP block is found in S922X (G12B) SoCs. The
  21. * datasheet contains the description for this IP block revision starting at
  22. * page 1084:
  23. * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
  24. *
  25. * Copyright (c) 2016 BayLibre, SAS.
  26. * Author: Neil Armstrong <narmstrong@baylibre.com>
  27. * Copyright (C) 2014 Amlogic, Inc.
  28. */
  29. #include <linux/bitfield.h>
  30. #include <linux/bits.h>
  31. #include <linux/clk.h>
  32. #include <linux/clk-provider.h>
  33. #include <linux/err.h>
  34. #include <linux/io.h>
  35. #include <linux/kernel.h>
  36. #include <linux/math64.h>
  37. #include <linux/module.h>
  38. #include <linux/of.h>
  39. #include <linux/of_device.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/pwm.h>
  42. #include <linux/slab.h>
  43. #include <linux/spinlock.h>
  44. #define REG_PWM_A 0x0
  45. #define REG_PWM_B 0x4
  46. #define PWM_LOW_MASK GENMASK(15, 0)
  47. #define PWM_HIGH_MASK GENMASK(31, 16)
  48. #define REG_MISC_AB 0x8
  49. #define MISC_B_CLK_EN BIT(23)
  50. #define MISC_A_CLK_EN BIT(15)
  51. #define MISC_CLK_DIV_MASK 0x7f
  52. #define MISC_B_CLK_DIV_SHIFT 16
  53. #define MISC_A_CLK_DIV_SHIFT 8
  54. #define MISC_B_CLK_SEL_SHIFT 6
  55. #define MISC_A_CLK_SEL_SHIFT 4
  56. #define MISC_CLK_SEL_MASK 0x3
  57. #define MISC_B_EN BIT(1)
  58. #define MISC_A_EN BIT(0)
  59. #define MESON_NUM_PWMS 2
  60. static struct meson_pwm_channel_data {
  61. u8 reg_offset;
  62. u8 clk_sel_shift;
  63. u8 clk_div_shift;
  64. u32 clk_en_mask;
  65. u32 pwm_en_mask;
  66. } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
  67. {
  68. .reg_offset = REG_PWM_A,
  69. .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
  70. .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
  71. .clk_en_mask = MISC_A_CLK_EN,
  72. .pwm_en_mask = MISC_A_EN,
  73. },
  74. {
  75. .reg_offset = REG_PWM_B,
  76. .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
  77. .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
  78. .clk_en_mask = MISC_B_CLK_EN,
  79. .pwm_en_mask = MISC_B_EN,
  80. }
  81. };
  82. struct meson_pwm_channel {
  83. unsigned int hi;
  84. unsigned int lo;
  85. u8 pre_div;
  86. struct clk *clk_parent;
  87. struct clk_mux mux;
  88. struct clk *clk;
  89. };
  90. struct meson_pwm_data {
  91. const char * const *parent_names;
  92. unsigned int num_parents;
  93. };
  94. struct meson_pwm {
  95. struct pwm_chip chip;
  96. const struct meson_pwm_data *data;
  97. struct meson_pwm_channel channels[MESON_NUM_PWMS];
  98. void __iomem *base;
  99. /*
  100. * Protects register (write) access to the REG_MISC_AB register
  101. * that is shared between the two PWMs.
  102. */
  103. spinlock_t lock;
  104. };
  105. static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
  106. {
  107. return container_of(chip, struct meson_pwm, chip);
  108. }
  109. static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  110. {
  111. struct meson_pwm *meson = to_meson_pwm(chip);
  112. struct meson_pwm_channel *channel;
  113. struct device *dev = chip->dev;
  114. int err;
  115. channel = pwm_get_chip_data(pwm);
  116. if (channel)
  117. return 0;
  118. channel = &meson->channels[pwm->hwpwm];
  119. if (channel->clk_parent) {
  120. err = clk_set_parent(channel->clk, channel->clk_parent);
  121. if (err < 0) {
  122. dev_err(dev, "failed to set parent %s for %s: %d\n",
  123. __clk_get_name(channel->clk_parent),
  124. __clk_get_name(channel->clk), err);
  125. return err;
  126. }
  127. }
  128. err = clk_prepare_enable(channel->clk);
  129. if (err < 0) {
  130. dev_err(dev, "failed to enable clock %s: %d\n",
  131. __clk_get_name(channel->clk), err);
  132. return err;
  133. }
  134. return pwm_set_chip_data(pwm, channel);
  135. }
  136. static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  137. {
  138. struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
  139. if (channel)
  140. clk_disable_unprepare(channel->clk);
  141. }
  142. static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
  143. const struct pwm_state *state)
  144. {
  145. struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
  146. unsigned int duty, period, pre_div, cnt, duty_cnt;
  147. unsigned long fin_freq;
  148. duty = state->duty_cycle;
  149. period = state->period;
  150. if (state->polarity == PWM_POLARITY_INVERSED)
  151. duty = period - duty;
  152. fin_freq = clk_get_rate(channel->clk);
  153. if (fin_freq == 0) {
  154. dev_err(meson->chip.dev, "invalid source clock frequency\n");
  155. return -EINVAL;
  156. }
  157. dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
  158. pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
  159. if (pre_div > MISC_CLK_DIV_MASK) {
  160. dev_err(meson->chip.dev, "unable to get period pre_div\n");
  161. return -EINVAL;
  162. }
  163. cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
  164. if (cnt > 0xffff) {
  165. dev_err(meson->chip.dev, "unable to get period cnt\n");
  166. return -EINVAL;
  167. }
  168. dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
  169. pre_div, cnt);
  170. if (duty == period) {
  171. channel->pre_div = pre_div;
  172. channel->hi = cnt;
  173. channel->lo = 0;
  174. } else if (duty == 0) {
  175. channel->pre_div = pre_div;
  176. channel->hi = 0;
  177. channel->lo = cnt;
  178. } else {
  179. /* Then check is we can have the duty with the same pre_div */
  180. duty_cnt = div64_u64(fin_freq * (u64)duty,
  181. NSEC_PER_SEC * (pre_div + 1));
  182. if (duty_cnt > 0xffff) {
  183. dev_err(meson->chip.dev, "unable to get duty cycle\n");
  184. return -EINVAL;
  185. }
  186. dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
  187. duty, pre_div, duty_cnt);
  188. channel->pre_div = pre_div;
  189. channel->hi = duty_cnt;
  190. channel->lo = cnt - duty_cnt;
  191. }
  192. return 0;
  193. }
  194. static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
  195. {
  196. struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
  197. struct meson_pwm_channel_data *channel_data;
  198. unsigned long flags;
  199. u32 value;
  200. channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
  201. spin_lock_irqsave(&meson->lock, flags);
  202. value = readl(meson->base + REG_MISC_AB);
  203. value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
  204. value |= channel->pre_div << channel_data->clk_div_shift;
  205. value |= channel_data->clk_en_mask;
  206. writel(value, meson->base + REG_MISC_AB);
  207. value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
  208. FIELD_PREP(PWM_LOW_MASK, channel->lo);
  209. writel(value, meson->base + channel_data->reg_offset);
  210. value = readl(meson->base + REG_MISC_AB);
  211. value |= channel_data->pwm_en_mask;
  212. writel(value, meson->base + REG_MISC_AB);
  213. spin_unlock_irqrestore(&meson->lock, flags);
  214. }
  215. static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
  216. {
  217. unsigned long flags;
  218. u32 value;
  219. spin_lock_irqsave(&meson->lock, flags);
  220. value = readl(meson->base + REG_MISC_AB);
  221. value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
  222. writel(value, meson->base + REG_MISC_AB);
  223. spin_unlock_irqrestore(&meson->lock, flags);
  224. }
  225. static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  226. const struct pwm_state *state)
  227. {
  228. struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
  229. struct meson_pwm *meson = to_meson_pwm(chip);
  230. int err = 0;
  231. if (!state)
  232. return -EINVAL;
  233. if (!state->enabled) {
  234. if (state->polarity == PWM_POLARITY_INVERSED) {
  235. /*
  236. * This IP block revision doesn't have an "always high"
  237. * setting which we can use for "inverted disabled".
  238. * Instead we achieve this using the same settings
  239. * that we use a pre_div of 0 (to get the shortest
  240. * possible duration for one "count") and
  241. * "period == duty_cycle". This results in a signal
  242. * which is LOW for one "count", while being HIGH for
  243. * the rest of the (so the signal is HIGH for slightly
  244. * less than 100% of the period, but this is the best
  245. * we can achieve).
  246. */
  247. channel->pre_div = 0;
  248. channel->hi = ~0;
  249. channel->lo = 0;
  250. meson_pwm_enable(meson, pwm);
  251. } else {
  252. meson_pwm_disable(meson, pwm);
  253. }
  254. } else {
  255. err = meson_pwm_calc(meson, pwm, state);
  256. if (err < 0)
  257. return err;
  258. meson_pwm_enable(meson, pwm);
  259. }
  260. return 0;
  261. }
  262. static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
  263. struct pwm_device *pwm, u32 cnt)
  264. {
  265. struct meson_pwm *meson = to_meson_pwm(chip);
  266. struct meson_pwm_channel *channel;
  267. unsigned long fin_freq;
  268. u32 fin_ns;
  269. /* to_meson_pwm() can only be used after .get_state() is called */
  270. channel = &meson->channels[pwm->hwpwm];
  271. fin_freq = clk_get_rate(channel->clk);
  272. if (fin_freq == 0)
  273. return 0;
  274. fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
  275. return cnt * fin_ns * (channel->pre_div + 1);
  276. }
  277. static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  278. struct pwm_state *state)
  279. {
  280. struct meson_pwm *meson = to_meson_pwm(chip);
  281. struct meson_pwm_channel_data *channel_data;
  282. struct meson_pwm_channel *channel;
  283. u32 value, tmp;
  284. if (!state)
  285. return;
  286. channel = &meson->channels[pwm->hwpwm];
  287. channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
  288. value = readl(meson->base + REG_MISC_AB);
  289. tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
  290. state->enabled = (value & tmp) == tmp;
  291. tmp = value >> channel_data->clk_div_shift;
  292. channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
  293. value = readl(meson->base + channel_data->reg_offset);
  294. channel->lo = FIELD_GET(PWM_LOW_MASK, value);
  295. channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
  296. if (channel->lo == 0) {
  297. state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
  298. state->duty_cycle = state->period;
  299. } else if (channel->lo >= channel->hi) {
  300. state->period = meson_pwm_cnt_to_ns(chip, pwm,
  301. channel->lo + channel->hi);
  302. state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
  303. channel->hi);
  304. } else {
  305. state->period = 0;
  306. state->duty_cycle = 0;
  307. }
  308. }
  309. static const struct pwm_ops meson_pwm_ops = {
  310. .request = meson_pwm_request,
  311. .free = meson_pwm_free,
  312. .apply = meson_pwm_apply,
  313. .get_state = meson_pwm_get_state,
  314. .owner = THIS_MODULE,
  315. };
  316. static const char * const pwm_meson8b_parent_names[] = {
  317. "xtal", "vid_pll", "fclk_div4", "fclk_div3"
  318. };
  319. static const struct meson_pwm_data pwm_meson8b_data = {
  320. .parent_names = pwm_meson8b_parent_names,
  321. .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
  322. };
  323. static const char * const pwm_gxbb_parent_names[] = {
  324. "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
  325. };
  326. static const struct meson_pwm_data pwm_gxbb_data = {
  327. .parent_names = pwm_gxbb_parent_names,
  328. .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
  329. };
  330. /*
  331. * Only the 2 first inputs of the GXBB AO PWMs are valid
  332. * The last 2 are grounded
  333. */
  334. static const char * const pwm_gxbb_ao_parent_names[] = {
  335. "xtal", "clk81"
  336. };
  337. static const struct meson_pwm_data pwm_gxbb_ao_data = {
  338. .parent_names = pwm_gxbb_ao_parent_names,
  339. .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
  340. };
  341. static const char * const pwm_axg_ee_parent_names[] = {
  342. "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
  343. };
  344. static const struct meson_pwm_data pwm_axg_ee_data = {
  345. .parent_names = pwm_axg_ee_parent_names,
  346. .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
  347. };
  348. static const char * const pwm_axg_ao_parent_names[] = {
  349. "aoclk81", "xtal", "fclk_div4", "fclk_div5"
  350. };
  351. static const struct meson_pwm_data pwm_axg_ao_data = {
  352. .parent_names = pwm_axg_ao_parent_names,
  353. .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
  354. };
  355. static const char * const pwm_g12a_ao_ab_parent_names[] = {
  356. "xtal", "aoclk81", "fclk_div4", "fclk_div5"
  357. };
  358. static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
  359. .parent_names = pwm_g12a_ao_ab_parent_names,
  360. .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
  361. };
  362. static const char * const pwm_g12a_ao_cd_parent_names[] = {
  363. "xtal", "aoclk81",
  364. };
  365. static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
  366. .parent_names = pwm_g12a_ao_cd_parent_names,
  367. .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
  368. };
  369. static const char * const pwm_g12a_ee_parent_names[] = {
  370. "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
  371. };
  372. static const struct meson_pwm_data pwm_g12a_ee_data = {
  373. .parent_names = pwm_g12a_ee_parent_names,
  374. .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
  375. };
  376. static const struct of_device_id meson_pwm_matches[] = {
  377. {
  378. .compatible = "amlogic,meson8b-pwm",
  379. .data = &pwm_meson8b_data
  380. },
  381. {
  382. .compatible = "amlogic,meson-gxbb-pwm",
  383. .data = &pwm_gxbb_data
  384. },
  385. {
  386. .compatible = "amlogic,meson-gxbb-ao-pwm",
  387. .data = &pwm_gxbb_ao_data
  388. },
  389. {
  390. .compatible = "amlogic,meson-axg-ee-pwm",
  391. .data = &pwm_axg_ee_data
  392. },
  393. {
  394. .compatible = "amlogic,meson-axg-ao-pwm",
  395. .data = &pwm_axg_ao_data
  396. },
  397. {
  398. .compatible = "amlogic,meson-g12a-ee-pwm",
  399. .data = &pwm_g12a_ee_data
  400. },
  401. {
  402. .compatible = "amlogic,meson-g12a-ao-pwm-ab",
  403. .data = &pwm_g12a_ao_ab_data
  404. },
  405. {
  406. .compatible = "amlogic,meson-g12a-ao-pwm-cd",
  407. .data = &pwm_g12a_ao_cd_data
  408. },
  409. {},
  410. };
  411. MODULE_DEVICE_TABLE(of, meson_pwm_matches);
  412. static int meson_pwm_init_channels(struct meson_pwm *meson)
  413. {
  414. struct device *dev = meson->chip.dev;
  415. struct clk_init_data init;
  416. unsigned int i;
  417. char name[255];
  418. int err;
  419. for (i = 0; i < meson->chip.npwm; i++) {
  420. struct meson_pwm_channel *channel = &meson->channels[i];
  421. snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
  422. init.name = name;
  423. init.ops = &clk_mux_ops;
  424. init.flags = 0;
  425. init.parent_names = meson->data->parent_names;
  426. init.num_parents = meson->data->num_parents;
  427. channel->mux.reg = meson->base + REG_MISC_AB;
  428. channel->mux.shift =
  429. meson_pwm_per_channel_data[i].clk_sel_shift;
  430. channel->mux.mask = MISC_CLK_SEL_MASK;
  431. channel->mux.flags = 0;
  432. channel->mux.lock = &meson->lock;
  433. channel->mux.table = NULL;
  434. channel->mux.hw.init = &init;
  435. channel->clk = devm_clk_register(dev, &channel->mux.hw);
  436. if (IS_ERR(channel->clk)) {
  437. err = PTR_ERR(channel->clk);
  438. dev_err(dev, "failed to register %s: %d\n", name, err);
  439. return err;
  440. }
  441. snprintf(name, sizeof(name), "clkin%u", i);
  442. channel->clk_parent = devm_clk_get_optional(dev, name);
  443. if (IS_ERR(channel->clk_parent))
  444. return PTR_ERR(channel->clk_parent);
  445. }
  446. return 0;
  447. }
  448. static int meson_pwm_probe(struct platform_device *pdev)
  449. {
  450. struct meson_pwm *meson;
  451. struct resource *regs;
  452. int err;
  453. meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
  454. if (!meson)
  455. return -ENOMEM;
  456. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  457. meson->base = devm_ioremap_resource(&pdev->dev, regs);
  458. if (IS_ERR(meson->base))
  459. return PTR_ERR(meson->base);
  460. spin_lock_init(&meson->lock);
  461. meson->chip.dev = &pdev->dev;
  462. meson->chip.ops = &meson_pwm_ops;
  463. meson->chip.base = -1;
  464. meson->chip.npwm = MESON_NUM_PWMS;
  465. meson->chip.of_xlate = of_pwm_xlate_with_flags;
  466. meson->chip.of_pwm_n_cells = 3;
  467. meson->data = of_device_get_match_data(&pdev->dev);
  468. err = meson_pwm_init_channels(meson);
  469. if (err < 0)
  470. return err;
  471. err = pwmchip_add(&meson->chip);
  472. if (err < 0) {
  473. dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
  474. return err;
  475. }
  476. platform_set_drvdata(pdev, meson);
  477. return 0;
  478. }
  479. static int meson_pwm_remove(struct platform_device *pdev)
  480. {
  481. struct meson_pwm *meson = platform_get_drvdata(pdev);
  482. return pwmchip_remove(&meson->chip);
  483. }
  484. static struct platform_driver meson_pwm_driver = {
  485. .driver = {
  486. .name = "meson-pwm",
  487. .of_match_table = meson_pwm_matches,
  488. },
  489. .probe = meson_pwm_probe,
  490. .remove = meson_pwm_remove,
  491. };
  492. module_platform_driver(meson_pwm_driver);
  493. MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
  494. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  495. MODULE_LICENSE("Dual BSD/GPL");