pwm-mediatek.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek Pulse Width Modulator driver
  4. *
  5. * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  6. * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
  7. *
  8. */
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/ioport.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/clk.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pwm.h>
  19. #include <linux/slab.h>
  20. #include <linux/types.h>
  21. /* PWM registers and bits definitions */
  22. #define PWMCON 0x00
  23. #define PWMHDUR 0x04
  24. #define PWMLDUR 0x08
  25. #define PWMGDUR 0x0c
  26. #define PWMWAVENUM 0x28
  27. #define PWMDWIDTH 0x2c
  28. #define PWM45DWIDTH_FIXUP 0x30
  29. #define PWMTHRES 0x30
  30. #define PWM45THRES_FIXUP 0x34
  31. #define PWM_CLK_DIV_MAX 7
  32. struct pwm_mediatek_of_data {
  33. unsigned int num_pwms;
  34. bool pwm45_fixup;
  35. };
  36. /**
  37. * struct pwm_mediatek_chip - struct representing PWM chip
  38. * @chip: linux PWM chip representation
  39. * @regs: base address of PWM chip
  40. * @clk_top: the top clock generator
  41. * @clk_main: the clock used by PWM core
  42. * @clk_pwms: the clock used by each PWM channel
  43. * @clk_freq: the fix clock frequency of legacy MIPS SoC
  44. * @soc: pointer to chip's platform data
  45. */
  46. struct pwm_mediatek_chip {
  47. struct pwm_chip chip;
  48. void __iomem *regs;
  49. struct clk *clk_top;
  50. struct clk *clk_main;
  51. struct clk **clk_pwms;
  52. const struct pwm_mediatek_of_data *soc;
  53. };
  54. static const unsigned int pwm_mediatek_reg_offset[] = {
  55. 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  56. };
  57. static inline struct pwm_mediatek_chip *
  58. to_pwm_mediatek_chip(struct pwm_chip *chip)
  59. {
  60. return container_of(chip, struct pwm_mediatek_chip, chip);
  61. }
  62. static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
  63. struct pwm_device *pwm)
  64. {
  65. struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  66. int ret;
  67. ret = clk_prepare_enable(pc->clk_top);
  68. if (ret < 0)
  69. return ret;
  70. ret = clk_prepare_enable(pc->clk_main);
  71. if (ret < 0)
  72. goto disable_clk_top;
  73. ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
  74. if (ret < 0)
  75. goto disable_clk_main;
  76. return 0;
  77. disable_clk_main:
  78. clk_disable_unprepare(pc->clk_main);
  79. disable_clk_top:
  80. clk_disable_unprepare(pc->clk_top);
  81. return ret;
  82. }
  83. static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
  84. struct pwm_device *pwm)
  85. {
  86. struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  87. clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
  88. clk_disable_unprepare(pc->clk_main);
  89. clk_disable_unprepare(pc->clk_top);
  90. }
  91. static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
  92. unsigned int num, unsigned int offset)
  93. {
  94. return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
  95. }
  96. static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
  97. unsigned int num, unsigned int offset,
  98. u32 value)
  99. {
  100. writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
  101. }
  102. static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
  103. int duty_ns, int period_ns)
  104. {
  105. struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  106. u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
  107. reg_thres = PWMTHRES;
  108. u64 resolution;
  109. int ret;
  110. ret = pwm_mediatek_clk_enable(chip, pwm);
  111. if (ret < 0)
  112. return ret;
  113. /* Using resolution in picosecond gets accuracy higher */
  114. resolution = (u64)NSEC_PER_SEC * 1000;
  115. do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
  116. cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
  117. while (cnt_period > 8191) {
  118. resolution *= 2;
  119. clkdiv++;
  120. cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
  121. resolution);
  122. }
  123. if (clkdiv > PWM_CLK_DIV_MAX) {
  124. pwm_mediatek_clk_disable(chip, pwm);
  125. dev_err(chip->dev, "period %d not supported\n", period_ns);
  126. return -EINVAL;
  127. }
  128. if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
  129. /*
  130. * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
  131. * from the other PWMs on MT7623.
  132. */
  133. reg_width = PWM45DWIDTH_FIXUP;
  134. reg_thres = PWM45THRES_FIXUP;
  135. }
  136. cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
  137. pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
  138. pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
  139. pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
  140. pwm_mediatek_clk_disable(chip, pwm);
  141. return 0;
  142. }
  143. static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  144. {
  145. struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  146. u32 value;
  147. int ret;
  148. ret = pwm_mediatek_clk_enable(chip, pwm);
  149. if (ret < 0)
  150. return ret;
  151. value = readl(pc->regs);
  152. value |= BIT(pwm->hwpwm);
  153. writel(value, pc->regs);
  154. return 0;
  155. }
  156. static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  157. {
  158. struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  159. u32 value;
  160. value = readl(pc->regs);
  161. value &= ~BIT(pwm->hwpwm);
  162. writel(value, pc->regs);
  163. pwm_mediatek_clk_disable(chip, pwm);
  164. }
  165. static const struct pwm_ops pwm_mediatek_ops = {
  166. .config = pwm_mediatek_config,
  167. .enable = pwm_mediatek_enable,
  168. .disable = pwm_mediatek_disable,
  169. .owner = THIS_MODULE,
  170. };
  171. static int pwm_mediatek_probe(struct platform_device *pdev)
  172. {
  173. struct pwm_mediatek_chip *pc;
  174. struct resource *res;
  175. unsigned int i;
  176. int ret;
  177. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  178. if (!pc)
  179. return -ENOMEM;
  180. pc->soc = of_device_get_match_data(&pdev->dev);
  181. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  182. pc->regs = devm_ioremap_resource(&pdev->dev, res);
  183. if (IS_ERR(pc->regs))
  184. return PTR_ERR(pc->regs);
  185. pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
  186. sizeof(*pc->clk_pwms), GFP_KERNEL);
  187. if (!pc->clk_pwms)
  188. return -ENOMEM;
  189. pc->clk_top = devm_clk_get(&pdev->dev, "top");
  190. if (IS_ERR(pc->clk_top)) {
  191. dev_err(&pdev->dev, "clock: top fail: %ld\n",
  192. PTR_ERR(pc->clk_top));
  193. return PTR_ERR(pc->clk_top);
  194. }
  195. pc->clk_main = devm_clk_get(&pdev->dev, "main");
  196. if (IS_ERR(pc->clk_main)) {
  197. dev_err(&pdev->dev, "clock: main fail: %ld\n",
  198. PTR_ERR(pc->clk_main));
  199. return PTR_ERR(pc->clk_main);
  200. }
  201. for (i = 0; i < pc->soc->num_pwms; i++) {
  202. char name[8];
  203. snprintf(name, sizeof(name), "pwm%d", i + 1);
  204. pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
  205. if (IS_ERR(pc->clk_pwms[i])) {
  206. dev_err(&pdev->dev, "clock: %s fail: %ld\n",
  207. name, PTR_ERR(pc->clk_pwms[i]));
  208. return PTR_ERR(pc->clk_pwms[i]);
  209. }
  210. }
  211. platform_set_drvdata(pdev, pc);
  212. pc->chip.dev = &pdev->dev;
  213. pc->chip.ops = &pwm_mediatek_ops;
  214. pc->chip.base = -1;
  215. pc->chip.npwm = pc->soc->num_pwms;
  216. ret = pwmchip_add(&pc->chip);
  217. if (ret < 0) {
  218. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  219. return ret;
  220. }
  221. return 0;
  222. }
  223. static int pwm_mediatek_remove(struct platform_device *pdev)
  224. {
  225. struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
  226. return pwmchip_remove(&pc->chip);
  227. }
  228. static const struct pwm_mediatek_of_data mt2712_pwm_data = {
  229. .num_pwms = 8,
  230. .pwm45_fixup = false,
  231. };
  232. static const struct pwm_mediatek_of_data mt7622_pwm_data = {
  233. .num_pwms = 6,
  234. .pwm45_fixup = false,
  235. };
  236. static const struct pwm_mediatek_of_data mt7623_pwm_data = {
  237. .num_pwms = 5,
  238. .pwm45_fixup = true,
  239. };
  240. static const struct pwm_mediatek_of_data mt7628_pwm_data = {
  241. .num_pwms = 4,
  242. .pwm45_fixup = true,
  243. };
  244. static const struct pwm_mediatek_of_data mt7629_pwm_data = {
  245. .num_pwms = 1,
  246. .pwm45_fixup = false,
  247. };
  248. static const struct pwm_mediatek_of_data mt8516_pwm_data = {
  249. .num_pwms = 5,
  250. .pwm45_fixup = false,
  251. };
  252. static const struct of_device_id pwm_mediatek_of_match[] = {
  253. { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
  254. { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
  255. { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
  256. { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
  257. { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
  258. { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
  259. { },
  260. };
  261. MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
  262. static struct platform_driver pwm_mediatek_driver = {
  263. .driver = {
  264. .name = "pwm-mediatek",
  265. .of_match_table = pwm_mediatek_of_match,
  266. },
  267. .probe = pwm_mediatek_probe,
  268. .remove = pwm_mediatek_remove,
  269. };
  270. module_platform_driver(pwm_mediatek_driver);
  271. MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  272. MODULE_LICENSE("GPL v2");