pwm-fsl-ftm.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale FlexTimer Module (FTM) PWM Driver
  4. *
  5. * Copyright 2012-2013 Freescale Semiconductor, Inc.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm.h>
  17. #include <linux/pwm.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <linux/fsl/ftm.h>
  21. #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
  22. enum fsl_pwm_clk {
  23. FSL_PWM_CLK_SYS,
  24. FSL_PWM_CLK_FIX,
  25. FSL_PWM_CLK_EXT,
  26. FSL_PWM_CLK_CNTEN,
  27. FSL_PWM_CLK_MAX
  28. };
  29. struct fsl_ftm_soc {
  30. bool has_enable_bits;
  31. };
  32. struct fsl_pwm_periodcfg {
  33. enum fsl_pwm_clk clk_select;
  34. unsigned int clk_ps;
  35. unsigned int mod_period;
  36. };
  37. struct fsl_pwm_chip {
  38. struct pwm_chip chip;
  39. struct mutex lock;
  40. struct regmap *regmap;
  41. /* This value is valid iff a pwm is running */
  42. struct fsl_pwm_periodcfg period;
  43. struct clk *ipg_clk;
  44. struct clk *clk[FSL_PWM_CLK_MAX];
  45. const struct fsl_ftm_soc *soc;
  46. };
  47. static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
  48. {
  49. return container_of(chip, struct fsl_pwm_chip, chip);
  50. }
  51. static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
  52. {
  53. u32 val;
  54. regmap_read(fpc->regmap, FTM_FMS, &val);
  55. if (val & FTM_FMS_WPEN)
  56. regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
  57. FTM_MODE_WPDIS);
  58. }
  59. static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
  60. {
  61. regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
  62. }
  63. static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
  64. const struct fsl_pwm_periodcfg *b)
  65. {
  66. if (a->clk_select != b->clk_select)
  67. return false;
  68. if (a->clk_ps != b->clk_ps)
  69. return false;
  70. if (a->mod_period != b->mod_period)
  71. return false;
  72. return true;
  73. }
  74. static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  75. {
  76. int ret;
  77. struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
  78. ret = clk_prepare_enable(fpc->ipg_clk);
  79. if (!ret && fpc->soc->has_enable_bits) {
  80. mutex_lock(&fpc->lock);
  81. regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
  82. BIT(pwm->hwpwm + 16));
  83. mutex_unlock(&fpc->lock);
  84. }
  85. return ret;
  86. }
  87. static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  88. {
  89. struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
  90. if (fpc->soc->has_enable_bits) {
  91. mutex_lock(&fpc->lock);
  92. regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
  93. 0);
  94. mutex_unlock(&fpc->lock);
  95. }
  96. clk_disable_unprepare(fpc->ipg_clk);
  97. }
  98. static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
  99. unsigned int ticks)
  100. {
  101. unsigned long rate;
  102. unsigned long long exval;
  103. rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
  104. exval = ticks;
  105. exval *= 1000000000UL;
  106. do_div(exval, rate >> fpc->period.clk_ps);
  107. return exval;
  108. }
  109. static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
  110. unsigned int period_ns,
  111. enum fsl_pwm_clk index,
  112. struct fsl_pwm_periodcfg *periodcfg
  113. )
  114. {
  115. unsigned long long c;
  116. unsigned int ps;
  117. c = clk_get_rate(fpc->clk[index]);
  118. c = c * period_ns;
  119. do_div(c, 1000000000UL);
  120. if (c == 0)
  121. return false;
  122. for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
  123. if (c <= 0x10000) {
  124. periodcfg->clk_select = index;
  125. periodcfg->clk_ps = ps;
  126. periodcfg->mod_period = c - 1;
  127. return true;
  128. }
  129. }
  130. return false;
  131. }
  132. static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
  133. unsigned int period_ns,
  134. struct fsl_pwm_periodcfg *periodcfg)
  135. {
  136. enum fsl_pwm_clk m0, m1;
  137. unsigned long fix_rate, ext_rate;
  138. bool ret;
  139. ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
  140. periodcfg);
  141. if (ret)
  142. return true;
  143. fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
  144. ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
  145. if (fix_rate > ext_rate) {
  146. m0 = FSL_PWM_CLK_FIX;
  147. m1 = FSL_PWM_CLK_EXT;
  148. } else {
  149. m0 = FSL_PWM_CLK_EXT;
  150. m1 = FSL_PWM_CLK_FIX;
  151. }
  152. ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
  153. if (ret)
  154. return true;
  155. return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
  156. }
  157. static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
  158. unsigned int duty_ns)
  159. {
  160. unsigned long long duty;
  161. unsigned int period = fpc->period.mod_period + 1;
  162. unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
  163. duty = (unsigned long long)duty_ns * period;
  164. do_div(duty, period_ns);
  165. return (unsigned int)duty;
  166. }
  167. static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
  168. struct pwm_device *pwm)
  169. {
  170. u32 val;
  171. regmap_read(fpc->regmap, FTM_OUTMASK, &val);
  172. if (~val & 0xFF)
  173. return true;
  174. else
  175. return false;
  176. }
  177. static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
  178. struct pwm_device *pwm)
  179. {
  180. u32 val;
  181. regmap_read(fpc->regmap, FTM_OUTMASK, &val);
  182. if (~(val | BIT(pwm->hwpwm)) & 0xFF)
  183. return true;
  184. else
  185. return false;
  186. }
  187. static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
  188. struct pwm_device *pwm,
  189. const struct pwm_state *newstate)
  190. {
  191. unsigned int duty;
  192. u32 reg_polarity;
  193. struct fsl_pwm_periodcfg periodcfg;
  194. bool do_write_period = false;
  195. if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
  196. dev_err(fpc->chip.dev, "failed to calculate new period\n");
  197. return -EINVAL;
  198. }
  199. if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
  200. do_write_period = true;
  201. /*
  202. * The Freescale FTM controller supports only a single period for
  203. * all PWM channels, therefore verify if the newly computed period
  204. * is different than the current period being used. In such case
  205. * we allow to change the period only if no other pwm is running.
  206. */
  207. else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
  208. if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
  209. dev_err(fpc->chip.dev,
  210. "Cannot change period for PWM %u, disable other PWMs first\n",
  211. pwm->hwpwm);
  212. return -EBUSY;
  213. }
  214. if (fpc->period.clk_select != periodcfg.clk_select) {
  215. int ret;
  216. enum fsl_pwm_clk oldclk = fpc->period.clk_select;
  217. enum fsl_pwm_clk newclk = periodcfg.clk_select;
  218. ret = clk_prepare_enable(fpc->clk[newclk]);
  219. if (ret)
  220. return ret;
  221. clk_disable_unprepare(fpc->clk[oldclk]);
  222. }
  223. do_write_period = true;
  224. }
  225. ftm_clear_write_protection(fpc);
  226. if (do_write_period) {
  227. regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
  228. FTM_SC_CLK(periodcfg.clk_select));
  229. regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
  230. periodcfg.clk_ps);
  231. regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
  232. fpc->period = periodcfg;
  233. }
  234. duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
  235. regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
  236. FTM_CSC_MSB | FTM_CSC_ELSB);
  237. regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
  238. reg_polarity = 0;
  239. if (newstate->polarity == PWM_POLARITY_INVERSED)
  240. reg_polarity = BIT(pwm->hwpwm);
  241. regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
  242. ftm_set_write_protection(fpc);
  243. return 0;
  244. }
  245. static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  246. const struct pwm_state *newstate)
  247. {
  248. struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
  249. struct pwm_state *oldstate = &pwm->state;
  250. int ret = 0;
  251. /*
  252. * oldstate to newstate : action
  253. *
  254. * disabled to disabled : ignore
  255. * enabled to disabled : disable
  256. * enabled to enabled : update settings
  257. * disabled to enabled : update settings + enable
  258. */
  259. mutex_lock(&fpc->lock);
  260. if (!newstate->enabled) {
  261. if (oldstate->enabled) {
  262. regmap_update_bits(fpc->regmap, FTM_OUTMASK,
  263. BIT(pwm->hwpwm), BIT(pwm->hwpwm));
  264. clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
  265. clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
  266. }
  267. goto end_mutex;
  268. }
  269. ret = fsl_pwm_apply_config(fpc, pwm, newstate);
  270. if (ret)
  271. goto end_mutex;
  272. /* check if need to enable */
  273. if (!oldstate->enabled) {
  274. ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
  275. if (ret)
  276. goto end_mutex;
  277. ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
  278. if (ret) {
  279. clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
  280. goto end_mutex;
  281. }
  282. regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
  283. 0);
  284. }
  285. end_mutex:
  286. mutex_unlock(&fpc->lock);
  287. return ret;
  288. }
  289. static const struct pwm_ops fsl_pwm_ops = {
  290. .request = fsl_pwm_request,
  291. .free = fsl_pwm_free,
  292. .apply = fsl_pwm_apply,
  293. .owner = THIS_MODULE,
  294. };
  295. static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
  296. {
  297. int ret;
  298. ret = clk_prepare_enable(fpc->ipg_clk);
  299. if (ret)
  300. return ret;
  301. regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
  302. regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
  303. regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
  304. clk_disable_unprepare(fpc->ipg_clk);
  305. return 0;
  306. }
  307. static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
  308. {
  309. switch (reg) {
  310. case FTM_FMS:
  311. case FTM_MODE:
  312. case FTM_CNT:
  313. return true;
  314. }
  315. return false;
  316. }
  317. static const struct regmap_config fsl_pwm_regmap_config = {
  318. .reg_bits = 32,
  319. .reg_stride = 4,
  320. .val_bits = 32,
  321. .max_register = FTM_PWMLOAD,
  322. .volatile_reg = fsl_pwm_volatile_reg,
  323. .cache_type = REGCACHE_FLAT,
  324. };
  325. static int fsl_pwm_probe(struct platform_device *pdev)
  326. {
  327. struct fsl_pwm_chip *fpc;
  328. struct resource *res;
  329. void __iomem *base;
  330. int ret;
  331. fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
  332. if (!fpc)
  333. return -ENOMEM;
  334. mutex_init(&fpc->lock);
  335. fpc->soc = of_device_get_match_data(&pdev->dev);
  336. fpc->chip.dev = &pdev->dev;
  337. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. base = devm_ioremap_resource(&pdev->dev, res);
  339. if (IS_ERR(base))
  340. return PTR_ERR(base);
  341. fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
  342. &fsl_pwm_regmap_config);
  343. if (IS_ERR(fpc->regmap)) {
  344. dev_err(&pdev->dev, "regmap init failed\n");
  345. return PTR_ERR(fpc->regmap);
  346. }
  347. fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
  348. if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
  349. dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
  350. return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
  351. }
  352. fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
  353. if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
  354. return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
  355. fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
  356. if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
  357. return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
  358. fpc->clk[FSL_PWM_CLK_CNTEN] =
  359. devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
  360. if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
  361. return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
  362. /*
  363. * ipg_clk is the interface clock for the IP. If not provided, use the
  364. * ftm_sys clock as the default.
  365. */
  366. fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  367. if (IS_ERR(fpc->ipg_clk))
  368. fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
  369. fpc->chip.ops = &fsl_pwm_ops;
  370. fpc->chip.of_xlate = of_pwm_xlate_with_flags;
  371. fpc->chip.of_pwm_n_cells = 3;
  372. fpc->chip.base = -1;
  373. fpc->chip.npwm = 8;
  374. ret = pwmchip_add(&fpc->chip);
  375. if (ret < 0) {
  376. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  377. return ret;
  378. }
  379. platform_set_drvdata(pdev, fpc);
  380. return fsl_pwm_init(fpc);
  381. }
  382. static int fsl_pwm_remove(struct platform_device *pdev)
  383. {
  384. struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
  385. return pwmchip_remove(&fpc->chip);
  386. }
  387. #ifdef CONFIG_PM_SLEEP
  388. static int fsl_pwm_suspend(struct device *dev)
  389. {
  390. struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
  391. int i;
  392. regcache_cache_only(fpc->regmap, true);
  393. regcache_mark_dirty(fpc->regmap);
  394. for (i = 0; i < fpc->chip.npwm; i++) {
  395. struct pwm_device *pwm = &fpc->chip.pwms[i];
  396. if (!test_bit(PWMF_REQUESTED, &pwm->flags))
  397. continue;
  398. clk_disable_unprepare(fpc->ipg_clk);
  399. if (!pwm_is_enabled(pwm))
  400. continue;
  401. clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
  402. clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
  403. }
  404. return 0;
  405. }
  406. static int fsl_pwm_resume(struct device *dev)
  407. {
  408. struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
  409. int i;
  410. for (i = 0; i < fpc->chip.npwm; i++) {
  411. struct pwm_device *pwm = &fpc->chip.pwms[i];
  412. if (!test_bit(PWMF_REQUESTED, &pwm->flags))
  413. continue;
  414. clk_prepare_enable(fpc->ipg_clk);
  415. if (!pwm_is_enabled(pwm))
  416. continue;
  417. clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
  418. clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
  419. }
  420. /* restore all registers from cache */
  421. regcache_cache_only(fpc->regmap, false);
  422. regcache_sync(fpc->regmap);
  423. return 0;
  424. }
  425. #endif
  426. static const struct dev_pm_ops fsl_pwm_pm_ops = {
  427. SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
  428. };
  429. static const struct fsl_ftm_soc vf610_ftm_pwm = {
  430. .has_enable_bits = false,
  431. };
  432. static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
  433. .has_enable_bits = true,
  434. };
  435. static const struct of_device_id fsl_pwm_dt_ids[] = {
  436. { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
  437. { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
  438. { /* sentinel */ }
  439. };
  440. MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
  441. static struct platform_driver fsl_pwm_driver = {
  442. .driver = {
  443. .name = "fsl-ftm-pwm",
  444. .of_match_table = fsl_pwm_dt_ids,
  445. .pm = &fsl_pwm_pm_ops,
  446. },
  447. .probe = fsl_pwm_probe,
  448. .remove = fsl_pwm_remove,
  449. };
  450. module_platform_driver(fsl_pwm_driver);
  451. MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
  452. MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
  453. MODULE_ALIAS("platform:fsl-ftm-pwm");
  454. MODULE_LICENSE("GPL");