pwm-brcmstb.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Broadcom BCM7038 PWM driver
  4. * Author: Florian Fainelli
  5. *
  6. * Copyright (C) 2015 Broadcom Corporation
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/clk.h>
  10. #include <linux/export.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pwm.h>
  18. #include <linux/spinlock.h>
  19. #define PWM_CTRL 0x00
  20. #define CTRL_START BIT(0)
  21. #define CTRL_OEB BIT(1)
  22. #define CTRL_FORCE_HIGH BIT(2)
  23. #define CTRL_OPENDRAIN BIT(3)
  24. #define CTRL_CHAN_OFFS 4
  25. #define PWM_CTRL2 0x04
  26. #define CTRL2_OUT_SELECT BIT(0)
  27. #define PWM_CH_SIZE 0x8
  28. #define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
  29. #define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
  30. /* Number of bits for the CWORD value */
  31. #define CWORD_BIT_SIZE 16
  32. /*
  33. * Maximum control word value allowed when variable-frequency PWM is used as a
  34. * clock for the constant-frequency PMW.
  35. */
  36. #define CONST_VAR_F_MAX 32768
  37. #define CONST_VAR_F_MIN 1
  38. #define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
  39. #define PWM_ON_MIN 1
  40. #define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
  41. #define PWM_PERIOD_MIN 0
  42. #define PWM_ON_PERIOD_MAX 0xff
  43. struct brcmstb_pwm {
  44. void __iomem *base;
  45. spinlock_t lock;
  46. struct clk *clk;
  47. struct pwm_chip chip;
  48. };
  49. static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
  50. unsigned int offset)
  51. {
  52. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  53. return __raw_readl(p->base + offset);
  54. else
  55. return readl_relaxed(p->base + offset);
  56. }
  57. static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
  58. unsigned int offset)
  59. {
  60. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  61. __raw_writel(value, p->base + offset);
  62. else
  63. writel_relaxed(value, p->base + offset);
  64. }
  65. static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
  66. {
  67. return container_of(chip, struct brcmstb_pwm, chip);
  68. }
  69. /*
  70. * Fv is derived from the variable frequency output. The variable frequency
  71. * output is configured using this formula:
  72. *
  73. * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
  74. *
  75. * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
  76. *
  77. * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
  78. *
  79. * The PWM core framework specifies that the "duty_ns" parameter is in fact the
  80. * "on" time, so this translates directly into our HW programming here.
  81. */
  82. static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  83. int duty_ns, int period_ns)
  84. {
  85. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  86. unsigned long pc, dc, cword = CONST_VAR_F_MAX;
  87. unsigned int channel = pwm->hwpwm;
  88. u32 value;
  89. /*
  90. * If asking for a duty_ns equal to period_ns, we need to substract
  91. * the period value by 1 to make it shorter than the "on" time and
  92. * produce a flat 100% duty cycle signal, and max out the "on" time
  93. */
  94. if (duty_ns == period_ns) {
  95. dc = PWM_ON_PERIOD_MAX;
  96. pc = PWM_ON_PERIOD_MAX - 1;
  97. goto done;
  98. }
  99. while (1) {
  100. u64 rate, tmp;
  101. /*
  102. * Calculate the base rate from base frequency and current
  103. * cword
  104. */
  105. rate = (u64)clk_get_rate(p->clk) * (u64)cword;
  106. do_div(rate, 1 << CWORD_BIT_SIZE);
  107. tmp = period_ns * rate;
  108. do_div(tmp, NSEC_PER_SEC);
  109. pc = tmp;
  110. tmp = (duty_ns + 1) * rate;
  111. do_div(tmp, NSEC_PER_SEC);
  112. dc = tmp;
  113. /*
  114. * We can be called with separate duty and period updates,
  115. * so do not reject dc == 0 right away
  116. */
  117. if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
  118. return -EINVAL;
  119. /* We converged on a calculation */
  120. if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
  121. break;
  122. /*
  123. * The cword needs to be a power of 2 for the variable
  124. * frequency generator to output a 50% duty cycle variable
  125. * frequency which is used as input clock to the fixed
  126. * frequency generator.
  127. */
  128. cword >>= 1;
  129. /*
  130. * Desired periods are too large, we do not have a divider
  131. * for them
  132. */
  133. if (cword < CONST_VAR_F_MIN)
  134. return -EINVAL;
  135. }
  136. done:
  137. /*
  138. * Configure the defined "cword" value to have the variable frequency
  139. * generator output a base frequency for the constant frequency
  140. * generator to derive from.
  141. */
  142. spin_lock(&p->lock);
  143. brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
  144. brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
  145. /* Select constant frequency signal output */
  146. value = brcmstb_pwm_readl(p, PWM_CTRL2);
  147. value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
  148. brcmstb_pwm_writel(p, value, PWM_CTRL2);
  149. /* Configure on and period value */
  150. brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
  151. brcmstb_pwm_writel(p, dc, PWM_ON(channel));
  152. spin_unlock(&p->lock);
  153. return 0;
  154. }
  155. static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
  156. unsigned int channel, bool enable)
  157. {
  158. unsigned int shift = channel * CTRL_CHAN_OFFS;
  159. u32 value;
  160. spin_lock(&p->lock);
  161. value = brcmstb_pwm_readl(p, PWM_CTRL);
  162. if (enable) {
  163. value &= ~(CTRL_OEB << shift);
  164. value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
  165. } else {
  166. value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
  167. value |= CTRL_OEB << shift;
  168. }
  169. brcmstb_pwm_writel(p, value, PWM_CTRL);
  170. spin_unlock(&p->lock);
  171. }
  172. static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  173. {
  174. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  175. brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
  176. return 0;
  177. }
  178. static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  179. {
  180. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  181. brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
  182. }
  183. static const struct pwm_ops brcmstb_pwm_ops = {
  184. .config = brcmstb_pwm_config,
  185. .enable = brcmstb_pwm_enable,
  186. .disable = brcmstb_pwm_disable,
  187. .owner = THIS_MODULE,
  188. };
  189. static const struct of_device_id brcmstb_pwm_of_match[] = {
  190. { .compatible = "brcm,bcm7038-pwm", },
  191. { /* sentinel */ }
  192. };
  193. MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
  194. static int brcmstb_pwm_probe(struct platform_device *pdev)
  195. {
  196. struct brcmstb_pwm *p;
  197. struct resource *res;
  198. int ret;
  199. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  200. if (!p)
  201. return -ENOMEM;
  202. spin_lock_init(&p->lock);
  203. p->clk = devm_clk_get(&pdev->dev, NULL);
  204. if (IS_ERR(p->clk)) {
  205. dev_err(&pdev->dev, "failed to obtain clock\n");
  206. return PTR_ERR(p->clk);
  207. }
  208. ret = clk_prepare_enable(p->clk);
  209. if (ret < 0) {
  210. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  211. return ret;
  212. }
  213. platform_set_drvdata(pdev, p);
  214. p->chip.dev = &pdev->dev;
  215. p->chip.ops = &brcmstb_pwm_ops;
  216. p->chip.base = -1;
  217. p->chip.npwm = 2;
  218. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  219. p->base = devm_ioremap_resource(&pdev->dev, res);
  220. if (IS_ERR(p->base)) {
  221. ret = PTR_ERR(p->base);
  222. goto out_clk;
  223. }
  224. ret = pwmchip_add(&p->chip);
  225. if (ret) {
  226. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  227. goto out_clk;
  228. }
  229. return 0;
  230. out_clk:
  231. clk_disable_unprepare(p->clk);
  232. return ret;
  233. }
  234. static int brcmstb_pwm_remove(struct platform_device *pdev)
  235. {
  236. struct brcmstb_pwm *p = platform_get_drvdata(pdev);
  237. int ret;
  238. ret = pwmchip_remove(&p->chip);
  239. clk_disable_unprepare(p->clk);
  240. return ret;
  241. }
  242. #ifdef CONFIG_PM_SLEEP
  243. static int brcmstb_pwm_suspend(struct device *dev)
  244. {
  245. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  246. clk_disable(p->clk);
  247. return 0;
  248. }
  249. static int brcmstb_pwm_resume(struct device *dev)
  250. {
  251. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  252. clk_enable(p->clk);
  253. return 0;
  254. }
  255. #endif
  256. static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
  257. brcmstb_pwm_resume);
  258. static struct platform_driver brcmstb_pwm_driver = {
  259. .probe = brcmstb_pwm_probe,
  260. .remove = brcmstb_pwm_remove,
  261. .driver = {
  262. .name = "pwm-brcmstb",
  263. .of_match_table = brcmstb_pwm_of_match,
  264. .pm = &brcmstb_pwm_pm_ops,
  265. },
  266. };
  267. module_platform_driver(brcmstb_pwm_driver);
  268. MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
  269. MODULE_DESCRIPTION("Broadcom STB PWM driver");
  270. MODULE_ALIAS("platform:pwm-brcmstb");
  271. MODULE_LICENSE("GPL");