pwm-bcm-iproc.c 7.5 KB

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  1. /*
  2. * Copyright (C) 2016 Broadcom
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/math64.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #define IPROC_PWM_CTRL_OFFSET 0x00
  23. #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch))
  24. #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch))
  25. #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch)
  26. #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3))
  27. #define IPROC_PWM_PERIOD_MIN 0x02
  28. #define IPROC_PWM_PERIOD_MAX 0xffff
  29. #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3))
  30. #define IPROC_PWM_DUTY_CYCLE_MIN 0x00
  31. #define IPROC_PWM_DUTY_CYCLE_MAX 0xffff
  32. #define IPROC_PWM_PRESCALE_OFFSET 0x24
  33. #define IPROC_PWM_PRESCALE_BITS 0x06
  34. #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
  35. IPROC_PWM_PRESCALE_BITS)
  36. #define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \
  37. IPROC_PWM_PRESCALE_SHIFT(ch))
  38. #define IPROC_PWM_PRESCALE_MIN 0x00
  39. #define IPROC_PWM_PRESCALE_MAX 0x3f
  40. struct iproc_pwmc {
  41. struct pwm_chip chip;
  42. void __iomem *base;
  43. struct clk *clk;
  44. };
  45. static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip)
  46. {
  47. return container_of(chip, struct iproc_pwmc, chip);
  48. }
  49. static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel)
  50. {
  51. u32 value;
  52. value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
  53. value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel);
  54. writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
  55. /* must be a 400 ns delay between clearing and setting enable bit */
  56. ndelay(400);
  57. }
  58. static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel)
  59. {
  60. u32 value;
  61. value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
  62. value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel));
  63. writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
  64. /* must be a 400 ns delay between clearing and setting enable bit */
  65. ndelay(400);
  66. }
  67. static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  68. struct pwm_state *state)
  69. {
  70. struct iproc_pwmc *ip = to_iproc_pwmc(chip);
  71. u64 tmp, multi, rate;
  72. u32 value, prescale;
  73. value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
  74. if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
  75. state->enabled = true;
  76. else
  77. state->enabled = false;
  78. if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))
  79. state->polarity = PWM_POLARITY_NORMAL;
  80. else
  81. state->polarity = PWM_POLARITY_INVERSED;
  82. rate = clk_get_rate(ip->clk);
  83. if (rate == 0) {
  84. state->period = 0;
  85. state->duty_cycle = 0;
  86. return;
  87. }
  88. value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
  89. prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
  90. prescale &= IPROC_PWM_PRESCALE_MAX;
  91. multi = NSEC_PER_SEC * (prescale + 1);
  92. value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
  93. tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
  94. state->period = div64_u64(tmp, rate);
  95. value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
  96. tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
  97. state->duty_cycle = div64_u64(tmp, rate);
  98. }
  99. static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  100. const struct pwm_state *state)
  101. {
  102. unsigned long prescale = IPROC_PWM_PRESCALE_MIN;
  103. struct iproc_pwmc *ip = to_iproc_pwmc(chip);
  104. u32 value, period, duty;
  105. u64 rate;
  106. rate = clk_get_rate(ip->clk);
  107. /*
  108. * Find period count, duty count and prescale to suit duty_cycle and
  109. * period. This is done according to formulas described below:
  110. *
  111. * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
  112. * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
  113. *
  114. * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
  115. * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
  116. */
  117. while (1) {
  118. u64 value, div;
  119. div = NSEC_PER_SEC * (prescale + 1);
  120. value = rate * state->period;
  121. period = div64_u64(value, div);
  122. value = rate * state->duty_cycle;
  123. duty = div64_u64(value, div);
  124. if (period < IPROC_PWM_PERIOD_MIN)
  125. return -EINVAL;
  126. if (period <= IPROC_PWM_PERIOD_MAX &&
  127. duty <= IPROC_PWM_DUTY_CYCLE_MAX)
  128. break;
  129. /* Otherwise, increase prescale and recalculate counts */
  130. if (++prescale > IPROC_PWM_PRESCALE_MAX)
  131. return -EINVAL;
  132. }
  133. iproc_pwmc_disable(ip, pwm->hwpwm);
  134. /* Set prescale */
  135. value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
  136. value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);
  137. value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
  138. writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);
  139. /* set period and duty cycle */
  140. writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
  141. writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
  142. /* set polarity */
  143. value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
  144. if (state->polarity == PWM_POLARITY_NORMAL)
  145. value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm);
  146. else
  147. value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm));
  148. writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
  149. if (state->enabled)
  150. iproc_pwmc_enable(ip, pwm->hwpwm);
  151. return 0;
  152. }
  153. static const struct pwm_ops iproc_pwm_ops = {
  154. .apply = iproc_pwmc_apply,
  155. .get_state = iproc_pwmc_get_state,
  156. .owner = THIS_MODULE,
  157. };
  158. static int iproc_pwmc_probe(struct platform_device *pdev)
  159. {
  160. struct iproc_pwmc *ip;
  161. struct resource *res;
  162. unsigned int i;
  163. u32 value;
  164. int ret;
  165. ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL);
  166. if (!ip)
  167. return -ENOMEM;
  168. platform_set_drvdata(pdev, ip);
  169. ip->chip.dev = &pdev->dev;
  170. ip->chip.ops = &iproc_pwm_ops;
  171. ip->chip.base = -1;
  172. ip->chip.npwm = 4;
  173. ip->chip.of_xlate = of_pwm_xlate_with_flags;
  174. ip->chip.of_pwm_n_cells = 3;
  175. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  176. ip->base = devm_ioremap_resource(&pdev->dev, res);
  177. if (IS_ERR(ip->base))
  178. return PTR_ERR(ip->base);
  179. ip->clk = devm_clk_get(&pdev->dev, NULL);
  180. if (IS_ERR(ip->clk)) {
  181. dev_err(&pdev->dev, "failed to get clock: %ld\n",
  182. PTR_ERR(ip->clk));
  183. return PTR_ERR(ip->clk);
  184. }
  185. ret = clk_prepare_enable(ip->clk);
  186. if (ret < 0) {
  187. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  188. return ret;
  189. }
  190. /* Set full drive and normal polarity for all channels */
  191. value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
  192. for (i = 0; i < ip->chip.npwm; i++) {
  193. value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i));
  194. value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i);
  195. }
  196. writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
  197. ret = pwmchip_add(&ip->chip);
  198. if (ret < 0) {
  199. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  200. clk_disable_unprepare(ip->clk);
  201. }
  202. return ret;
  203. }
  204. static int iproc_pwmc_remove(struct platform_device *pdev)
  205. {
  206. struct iproc_pwmc *ip = platform_get_drvdata(pdev);
  207. clk_disable_unprepare(ip->clk);
  208. return pwmchip_remove(&ip->chip);
  209. }
  210. static const struct of_device_id bcm_iproc_pwmc_dt[] = {
  211. { .compatible = "brcm,iproc-pwm" },
  212. { },
  213. };
  214. MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt);
  215. static struct platform_driver iproc_pwmc_driver = {
  216. .driver = {
  217. .name = "bcm-iproc-pwm",
  218. .of_match_table = bcm_iproc_pwmc_dt,
  219. },
  220. .probe = iproc_pwmc_probe,
  221. .remove = iproc_pwmc_remove,
  222. };
  223. module_platform_driver(iproc_pwmc_driver);
  224. MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>");
  225. MODULE_DESCRIPTION("Broadcom iProc PWM driver");
  226. MODULE_LICENSE("GPL v2");