pwm-atmel.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Atmel Pulse Width Modulation Controller
  4. *
  5. * Copyright (C) 2013 Atmel Corporation
  6. * Bo Shen <voice.shen@atmel.com>
  7. *
  8. * Links to reference manuals for the supported PWM chips can be found in
  9. * Documentation/arm/microchip.rst.
  10. *
  11. * Limitations:
  12. * - Periods start with the inactive level.
  13. * - Hardware has to be stopped in general to update settings.
  14. *
  15. * Software bugs/possible improvements:
  16. * - When atmel_pwm_apply() is called with state->enabled=false a change in
  17. * state->polarity isn't honored.
  18. * - Instead of sleeping to wait for a completed period, the interrupt
  19. * functionality could be used.
  20. */
  21. #include <linux/clk.h>
  22. #include <linux/delay.h>
  23. #include <linux/err.h>
  24. #include <linux/io.h>
  25. #include <linux/module.h>
  26. #include <linux/mutex.h>
  27. #include <linux/of.h>
  28. #include <linux/of_device.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pwm.h>
  31. #include <linux/slab.h>
  32. /* The following is global registers for PWM controller */
  33. #define PWM_ENA 0x04
  34. #define PWM_DIS 0x08
  35. #define PWM_SR 0x0C
  36. #define PWM_ISR 0x1C
  37. /* Bit field in SR */
  38. #define PWM_SR_ALL_CH_ON 0x0F
  39. /* The following register is PWM channel related registers */
  40. #define PWM_CH_REG_OFFSET 0x200
  41. #define PWM_CH_REG_SIZE 0x20
  42. #define PWM_CMR 0x0
  43. /* Bit field in CMR */
  44. #define PWM_CMR_CPOL (1 << 9)
  45. #define PWM_CMR_UPD_CDTY (1 << 10)
  46. #define PWM_CMR_CPRE_MSK 0xF
  47. /* The following registers for PWM v1 */
  48. #define PWMV1_CDTY 0x04
  49. #define PWMV1_CPRD 0x08
  50. #define PWMV1_CUPD 0x10
  51. /* The following registers for PWM v2 */
  52. #define PWMV2_CDTY 0x04
  53. #define PWMV2_CDTYUPD 0x08
  54. #define PWMV2_CPRD 0x0C
  55. #define PWMV2_CPRDUPD 0x10
  56. #define PWM_MAX_PRES 10
  57. struct atmel_pwm_registers {
  58. u8 period;
  59. u8 period_upd;
  60. u8 duty;
  61. u8 duty_upd;
  62. };
  63. struct atmel_pwm_config {
  64. u32 period_bits;
  65. };
  66. struct atmel_pwm_data {
  67. struct atmel_pwm_registers regs;
  68. struct atmel_pwm_config cfg;
  69. };
  70. struct atmel_pwm_chip {
  71. struct pwm_chip chip;
  72. struct clk *clk;
  73. void __iomem *base;
  74. const struct atmel_pwm_data *data;
  75. unsigned int updated_pwms;
  76. /* ISR is cleared when read, ensure only one thread does that */
  77. struct mutex isr_lock;
  78. };
  79. static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
  80. {
  81. return container_of(chip, struct atmel_pwm_chip, chip);
  82. }
  83. static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
  84. unsigned long offset)
  85. {
  86. return readl_relaxed(chip->base + offset);
  87. }
  88. static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
  89. unsigned long offset, unsigned long val)
  90. {
  91. writel_relaxed(val, chip->base + offset);
  92. }
  93. static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
  94. unsigned int ch, unsigned long offset)
  95. {
  96. unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
  97. return atmel_pwm_readl(chip, base + offset);
  98. }
  99. static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
  100. unsigned int ch, unsigned long offset,
  101. unsigned long val)
  102. {
  103. unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
  104. atmel_pwm_writel(chip, base + offset, val);
  105. }
  106. static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
  107. const struct pwm_state *state,
  108. unsigned long *cprd, u32 *pres)
  109. {
  110. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  111. unsigned long long cycles = state->period;
  112. int shift;
  113. /* Calculate the period cycles and prescale value */
  114. cycles *= clk_get_rate(atmel_pwm->clk);
  115. do_div(cycles, NSEC_PER_SEC);
  116. /*
  117. * The register for the period length is cfg.period_bits bits wide.
  118. * So for each bit the number of clock cycles is wider divide the input
  119. * clock frequency by two using pres and shift cprd accordingly.
  120. */
  121. shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
  122. if (shift > PWM_MAX_PRES) {
  123. dev_err(chip->dev, "pres exceeds the maximum value\n");
  124. return -EINVAL;
  125. } else if (shift > 0) {
  126. *pres = shift;
  127. cycles >>= *pres;
  128. } else {
  129. *pres = 0;
  130. }
  131. *cprd = cycles;
  132. return 0;
  133. }
  134. static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
  135. unsigned long cprd, unsigned long *cdty)
  136. {
  137. unsigned long long cycles = state->duty_cycle;
  138. cycles *= cprd;
  139. do_div(cycles, state->period);
  140. *cdty = cprd - cycles;
  141. }
  142. static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
  143. unsigned long cdty)
  144. {
  145. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  146. u32 val;
  147. if (atmel_pwm->data->regs.duty_upd ==
  148. atmel_pwm->data->regs.period_upd) {
  149. val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
  150. val &= ~PWM_CMR_UPD_CDTY;
  151. atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
  152. }
  153. atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
  154. atmel_pwm->data->regs.duty_upd, cdty);
  155. }
  156. static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
  157. struct pwm_device *pwm,
  158. unsigned long cprd, unsigned long cdty)
  159. {
  160. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  161. atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
  162. atmel_pwm->data->regs.duty, cdty);
  163. atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
  164. atmel_pwm->data->regs.period, cprd);
  165. }
  166. static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
  167. bool disable_clk)
  168. {
  169. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  170. unsigned long timeout = jiffies + 2 * HZ;
  171. /*
  172. * Wait for at least a complete period to have passed before disabling a
  173. * channel to be sure that CDTY has been updated
  174. */
  175. mutex_lock(&atmel_pwm->isr_lock);
  176. atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
  177. while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
  178. time_before(jiffies, timeout)) {
  179. usleep_range(10, 100);
  180. atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
  181. }
  182. mutex_unlock(&atmel_pwm->isr_lock);
  183. atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
  184. /*
  185. * Wait for the PWM channel disable operation to be effective before
  186. * stopping the clock.
  187. */
  188. timeout = jiffies + 2 * HZ;
  189. while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
  190. time_before(jiffies, timeout))
  191. usleep_range(10, 100);
  192. if (disable_clk)
  193. clk_disable(atmel_pwm->clk);
  194. }
  195. static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  196. const struct pwm_state *state)
  197. {
  198. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  199. struct pwm_state cstate;
  200. unsigned long cprd, cdty;
  201. u32 pres, val;
  202. int ret;
  203. pwm_get_state(pwm, &cstate);
  204. if (state->enabled) {
  205. if (cstate.enabled &&
  206. cstate.polarity == state->polarity &&
  207. cstate.period == state->period) {
  208. cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
  209. atmel_pwm->data->regs.period);
  210. atmel_pwm_calculate_cdty(state, cprd, &cdty);
  211. atmel_pwm_update_cdty(chip, pwm, cdty);
  212. return 0;
  213. }
  214. ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
  215. &pres);
  216. if (ret) {
  217. dev_err(chip->dev,
  218. "failed to calculate cprd and prescaler\n");
  219. return ret;
  220. }
  221. atmel_pwm_calculate_cdty(state, cprd, &cdty);
  222. if (cstate.enabled) {
  223. atmel_pwm_disable(chip, pwm, false);
  224. } else {
  225. ret = clk_enable(atmel_pwm->clk);
  226. if (ret) {
  227. dev_err(chip->dev, "failed to enable clock\n");
  228. return ret;
  229. }
  230. }
  231. /* It is necessary to preserve CPOL, inside CMR */
  232. val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
  233. val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
  234. if (state->polarity == PWM_POLARITY_NORMAL)
  235. val &= ~PWM_CMR_CPOL;
  236. else
  237. val |= PWM_CMR_CPOL;
  238. atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
  239. atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
  240. mutex_lock(&atmel_pwm->isr_lock);
  241. atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
  242. atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
  243. mutex_unlock(&atmel_pwm->isr_lock);
  244. atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
  245. } else if (cstate.enabled) {
  246. atmel_pwm_disable(chip, pwm, true);
  247. }
  248. return 0;
  249. }
  250. static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  251. struct pwm_state *state)
  252. {
  253. struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
  254. u32 sr, cmr;
  255. sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
  256. cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
  257. if (sr & (1 << pwm->hwpwm)) {
  258. unsigned long rate = clk_get_rate(atmel_pwm->clk);
  259. u32 cdty, cprd, pres;
  260. u64 tmp;
  261. pres = cmr & PWM_CMR_CPRE_MSK;
  262. cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
  263. atmel_pwm->data->regs.period);
  264. tmp = (u64)cprd * NSEC_PER_SEC;
  265. tmp <<= pres;
  266. state->period = DIV64_U64_ROUND_UP(tmp, rate);
  267. cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
  268. atmel_pwm->data->regs.duty);
  269. tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
  270. tmp <<= pres;
  271. state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
  272. state->enabled = true;
  273. } else {
  274. state->enabled = false;
  275. }
  276. if (cmr & PWM_CMR_CPOL)
  277. state->polarity = PWM_POLARITY_INVERSED;
  278. else
  279. state->polarity = PWM_POLARITY_NORMAL;
  280. }
  281. static const struct pwm_ops atmel_pwm_ops = {
  282. .apply = atmel_pwm_apply,
  283. .get_state = atmel_pwm_get_state,
  284. .owner = THIS_MODULE,
  285. };
  286. static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
  287. .regs = {
  288. .period = PWMV1_CPRD,
  289. .period_upd = PWMV1_CUPD,
  290. .duty = PWMV1_CDTY,
  291. .duty_upd = PWMV1_CUPD,
  292. },
  293. .cfg = {
  294. /* 16 bits to keep period and duty. */
  295. .period_bits = 16,
  296. },
  297. };
  298. static const struct atmel_pwm_data atmel_sama5_pwm_data = {
  299. .regs = {
  300. .period = PWMV2_CPRD,
  301. .period_upd = PWMV2_CPRDUPD,
  302. .duty = PWMV2_CDTY,
  303. .duty_upd = PWMV2_CDTYUPD,
  304. },
  305. .cfg = {
  306. /* 16 bits to keep period and duty. */
  307. .period_bits = 16,
  308. },
  309. };
  310. static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
  311. .regs = {
  312. .period = PWMV1_CPRD,
  313. .period_upd = PWMV1_CUPD,
  314. .duty = PWMV1_CDTY,
  315. .duty_upd = PWMV1_CUPD,
  316. },
  317. .cfg = {
  318. /* 32 bits to keep period and duty. */
  319. .period_bits = 32,
  320. },
  321. };
  322. static const struct of_device_id atmel_pwm_dt_ids[] = {
  323. {
  324. .compatible = "atmel,at91sam9rl-pwm",
  325. .data = &atmel_sam9rl_pwm_data,
  326. }, {
  327. .compatible = "atmel,sama5d3-pwm",
  328. .data = &atmel_sama5_pwm_data,
  329. }, {
  330. .compatible = "atmel,sama5d2-pwm",
  331. .data = &atmel_sama5_pwm_data,
  332. }, {
  333. .compatible = "microchip,sam9x60-pwm",
  334. .data = &mchp_sam9x60_pwm_data,
  335. }, {
  336. /* sentinel */
  337. },
  338. };
  339. MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
  340. static int atmel_pwm_probe(struct platform_device *pdev)
  341. {
  342. struct atmel_pwm_chip *atmel_pwm;
  343. struct resource *res;
  344. int ret;
  345. atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
  346. if (!atmel_pwm)
  347. return -ENOMEM;
  348. mutex_init(&atmel_pwm->isr_lock);
  349. atmel_pwm->data = of_device_get_match_data(&pdev->dev);
  350. atmel_pwm->updated_pwms = 0;
  351. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  352. atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
  353. if (IS_ERR(atmel_pwm->base))
  354. return PTR_ERR(atmel_pwm->base);
  355. atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
  356. if (IS_ERR(atmel_pwm->clk))
  357. return PTR_ERR(atmel_pwm->clk);
  358. ret = clk_prepare(atmel_pwm->clk);
  359. if (ret) {
  360. dev_err(&pdev->dev, "failed to prepare PWM clock\n");
  361. return ret;
  362. }
  363. atmel_pwm->chip.dev = &pdev->dev;
  364. atmel_pwm->chip.ops = &atmel_pwm_ops;
  365. atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
  366. atmel_pwm->chip.of_pwm_n_cells = 3;
  367. atmel_pwm->chip.base = -1;
  368. atmel_pwm->chip.npwm = 4;
  369. ret = pwmchip_add(&atmel_pwm->chip);
  370. if (ret < 0) {
  371. dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
  372. goto unprepare_clk;
  373. }
  374. platform_set_drvdata(pdev, atmel_pwm);
  375. return ret;
  376. unprepare_clk:
  377. clk_unprepare(atmel_pwm->clk);
  378. return ret;
  379. }
  380. static int atmel_pwm_remove(struct platform_device *pdev)
  381. {
  382. struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
  383. clk_unprepare(atmel_pwm->clk);
  384. mutex_destroy(&atmel_pwm->isr_lock);
  385. return pwmchip_remove(&atmel_pwm->chip);
  386. }
  387. static struct platform_driver atmel_pwm_driver = {
  388. .driver = {
  389. .name = "atmel-pwm",
  390. .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
  391. },
  392. .probe = atmel_pwm_probe,
  393. .remove = atmel_pwm_remove,
  394. };
  395. module_platform_driver(atmel_pwm_driver);
  396. MODULE_ALIAS("platform:atmel-pwm");
  397. MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
  398. MODULE_DESCRIPTION("Atmel PWM driver");
  399. MODULE_LICENSE("GPL v2");